Preemption-Aware Caching for Predictability and Performance

Transcription

1 Selfish-LRU: Preemption-ware aching for Predictability and Performance Jan Reineke Sebastian ltmeyer aniel Grund Sebastian Hahn laire Maiza S a a r l a n d U n i v e r s i t y, G e r m a n y University of msterdam, Netherlands Thales Germany Saarland University, Germany INP Grenoble, Verimag, France 20th IEEE Real-Time and Embedded Technology and pplications Symposium pril 15-17, 2014 erlin, Germany

2 ontext: Preemptive Scheduling Non-preemptive Execution: Task 1 Task 2 2

3 ontext: Preemptive Scheduling Preemptive Execution: Task 1 Task 2 3

4 aveat: Preemptions are not free! Preemptive Execution: Task 1 Task 2 ache-related Preemption elay (RP) 4

5 ontribution of this paper Selfish-LRU: a new cache replacement policy, that Increases performance by reducing the RP Simplifies static analysis of the RP 5

6 ontribution of this paper Selfish-LRU: a new cache replacement policy, that Increases performance by reducing the RP Simplifies static analysis of the RP Selfish-LRU is a preemption-aware variant of least-recently used (LRU) 5

7 Least-Recently Used (LRU) Replace data that has not been used for the longest time E: miss : hit : hit most-recently used E E E least-recently used Usually works well due to temporal locality 6

8 RP Example under LRU Replacement ssume simple preempted task: for i in [1,10]:!!! do something() for i in [1,10]:!!! access!!! access!!! access!!! access 7

9 RP Example under LRU Replacement ssume simple preempted task: for i in [1,10]:!!! do something() for i in [1,10]:!!! access!!! access!!! access!!! access Without preemption (after warmup): 0 misses : hit : hit : hit : hit 7

10 RP Example under LRU Replacement ssume simple preempting task: do something_else() access X Preemption between loop iterations: 1 access X: miss X 8

11 RP Example under LRU Replacement First loop iteration after preemption: 4 misses : miss : miss : miss : miss X X X X 9

12 RP Example under LRU Replacement: Two types of misses related to preemption 1. Replaced Misses 2. Reordered Misses : miss : miss : miss : miss X X X X 10

13 RP Example under LRU Replacement: Two types of misses related to preemption 1. Replaced Misses 2. Reordered Misses : miss : miss : miss : miss X X X X Liu et al., PT 2008: reordered misses account for 10% to 28% of all preemption-related misses 10

14 Selfish-LRU: Idea Prioritize blocks of currently running task: E: miss : hit F: miss most-recently used E F E E least-recently used Intuition: Memory blocks of currently running task more likely to be accessed again soon. 11

15 Selfish-LRU: RP Example Revisited ssume simple preempted task: for i in [1,10]:!!! do something() for i in [1,10]:!!! access!!! access!!! access!!! access Without preemption (after warmup): 0 misses : hit : hit : hit : hit Same behavior as LRU 12

16 Selfish-LRU: RP Example Revisited ssume simple preempting task: do something_else() access X Preemption between loop iterations: 1 access X: miss X 13

17 Selfish-LRU: RP Example Revisited First loop iteration after preemption: 1 miss : miss : hit : hit : hit X No reordering misses 14

18 Selfish-LRU: Properties 15

19 Selfish-LRU: Properties Property 1: Selfish-LRU does not exhibit reordering misses. Often: smaller RP Simplifies static analysis of the RP 15

20 Selfish-LRU: Properties Property 1: Selfish-LRU does not exhibit reordering misses. Often: smaller RP Simplifies static analysis of the RP Property 2: In non-preempted execution, Selfish-LRU = LRU. No change in regular WET analysis 15

21 Selfish-LRU: RP nalysis Preempting Preempted 16

22 Selfish-LRU: RP nalysis 1. Number of useful cache blocks (Us)? Preempting Preempted 16

23 Selfish-LRU: RP nalysis 2. Number of evicting 1. Number of useful cache blocks (Us)? cache blocks (Es)? Smaller ound Preempting Preempted 16

24 Selfish-LRU: RP nalysis 2. Number of evicting 1. Number of useful cache blocks (Us)? cache blocks (Es)? Smaller ound Preempting Preempted 3. ombination of Es and Us based on Resilience Simplified and Smaller ound 16

25 Selfish-LRU: Implementation Required modifications: Manage task ids (TI) in operating system Make TI available to cache in TI register ugment cache lines with TI of owner task onservative estimate: < 3% space overhead Modified replacement logic Similar to virtually-addressed caches 17

26 Experimental Evaluation 18

27 Experimental Evaluation Main goal: ompare Selfish-LRU with LRU in terms of performance and predictability! 18

28 Experimental Evaluation Main goal: ompare Selfish-LRU with LRU in terms of performance and predictability! Modified MPRM simulator RP analyses implemented in bsint s ait 18

29 Experimental Evaluation Main goal: ompare Selfish-LRU with LRU in terms of performance and predictability! Modified MPRM simulator RP analyses implemented in bsint s ait Secondary goal: (see paper for details) ompare RP approach with cache partitioning 18

30 Experimental Evaluation: enchmarks and ache onfiguration enchmarks: Four of the largest Mälardalen benchmarks Four models from the SE distribution Two SE models from an embedded systems course ache configuration: apacity: 2 K, 4 K, 8 K ssociativity: 4, 8 Number of sets: 32, 64,

31 Experimental Evaluation: Simulation Results, Large Preempting Task ache configuration: apacity: 2 Ki, ssociativity 4, Number of sets: 32 Measured number of additional misses Preempted Tasks 20

32 Experimental Evaluation: Simulation Results, Large Preempting Task ache configuration: apacity: 2 Ki, ssociativity 4, Number of sets: 32 Measured number of additional misses Large share of replaced misses Fairly small improvement Preempted Tasks 20

33 Experimental Evaluation: Simulation Results, Small Preempting Task ache configuration: apacity: 2 Ki, ssociativity 4, Number of sets: 32 Measured number of additional misses Preempted Tasks 21

34 Experimental Evaluation: Simulation Results, Small Preempting Task ache configuration: apacity: 2 Ki, ssociativity 4, Number of sets: 32 Measured number of additional misses Small share of replaced misses Fairly significant improvement Preempted Tasks 21

35 Experimental Evaluation: nalysis Results, Large Preempting Task ache configuration: apacity: 2 Ki, ssociativity 4, Number of sets: 32 ound on number of additional misses Preempted Tasks 22

36 Experimental Evaluation: nalysis Results, Large Preempting Task ache configuration: apacity: 2 Ki, ssociativity 4, Number of sets: 32 ound on number of additional misses ll misses are replaced misses No improvement Preempted Tasks 22

37 Experimental Evaluation: nalysis Results, Small Preempting Task ache configuration: apacity: 4 Ki, ssociativity 8, Number of sets: 32 ound on number of additional misses Preempted Tasks 23

38 Experimental Evaluation: nalysis Results, Small Preempting Task ache configuration: apacity: 4 Ki, ssociativity 8, Number of sets: 32 ound on number of additional misses Small share of replaced misses Fairly large improvement Preempted Tasks 23

39 Summary and Future Work Selfish-LRU eliminates reordered misses: Increases performance by reducing the RP Simplifies static analysis of the RP Large improvements for small preempting tasks like interrupt handlers 24

40 Summary and Future Work Selfish-LRU eliminates reordered misses: Increases performance by reducing the RP Simplifies static analysis of the RP Large improvements for small preempting tasks like interrupt handlers pply same idea in shared caches in multi-cores? 24