Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation. Boris Dreyer, Christian Hochberger, Simon Wegener, Alexander Weiss
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1 Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation Boris Dreyer, Christian Hochberger, Simon Wegener, Alexander Weiss
2 This work was funded within the project CONIRAS by the German Federal Ministry for Education and Research with the funding ID 01IS The responsibility for the content remains with the authors.
3 The Setting
4 The Timing Problem
5 Problem Solved? Reinhard Wilhelm et al.: The Worst-case Execution Time Problem Overview of Methods and Survey of Tools CONCLUSIONS The problem of determining upper bounds on execution times for single tasks and for quite complex processor architectures has been solved. Several commercial WCET tools are available and have experienced very positive feedback from extensive industrial use. ACM Transactions on Embedded Computing Systems, Vol. 7, No. 3, April 2008.
6 Well, almost Unpredictable delays due to interference on multicores Unpredictable hardware (e.g. random replacement policies for caches) Undocumented hardware Very pessimistic results!
7 Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement ECRTS 14
8 PREDATOR : ICT project in the 7th Framework Program of the EU Predictability Considerations in the Design of Multi-core Embedded Systems ERTS 2010
9 Measurements? Karsten Schmidt et al.: Non-Intrusive Tracing at First Instruction In the selected use case, a simple regression test, first a function trace for a longer time span, and then later on an instruction trace for a dedicated time span were generated. This approach (instead of tracing everything across a long time span) is necessary due to the limited bandwidth to components outside of the microcontroller. SAE Technical Paper
10 Catching the Worst Case
11 Catching the Worst Case
12 Measurements? Karsten Schmidt et al.: Non-Intrusive Tracing at First Instruction The art of tracing lies in the selection of the proper abstraction level and time in order to perform safe regression tests or identify potential issues as fast as possible. Especially when working under high time pressure with high costs related to the tests, or when working under extreme conditions, [ ], efficiency in tracing is crucial. SAE Technical Paper
13 State of The Art: Embedded Trace embedded trace based emulation system Target Emulator MPSoC CPUs peripherals Embedded trace trace data Offline analysis Bandwith (average): 0,3.. 4 Bit / Instruction (non-cycle accurate) Bit / Instruction (cycle accurate) 8 Bit / Instruction (data trace) MPSoC, 4 CPUs, 1 GHz Cycle accurate instruction + data trace 4 x 14 Bit x 1 GHz => approx. 28 Gbit/s ( + timestamps) ( + bus master trace) ( + peak bandwidth) Time stamps Instructions Data read Data written Time stamps Instructions Data read Data written Time stamps Instructions Data read Data written Time stamps Instructions Data read Data written MPSoC (4 CPUs) CPU 0 CPU 1 CPU 2 CPU 3
14 Trace Recording and Offline Processing SoC Per CPU0 Trace tool Host Per Mem CPU1 CPU2 Trace port Trace data processing (offline) Results Mem CPU3 SDRAM Hard disc SoC vendor s responsibility Tool vendor s responsibility Drawbacks: - Not all trace messages go through the SoC s trace port due to limited bandwidth - Processing bandwidth of host trace port is smaller than trace port bandwidth - Huge latency for the detection of MPSoC internal states - Restricted to on-chip trigger logic
15 Solution: Online Analysis of Trace Data - Trace bandwidth processing bandwidth - µs latency for detection of MPSoC internal states - Parallel processing / parallel oberservations HLL propositions compiler CoreSight / Nexus via parallel, Aurora, PCIe lanes up to 20 Gbit/s Real-time processing trace tool Instrumentation Trace configuration Event processing SoC Per Per Mem Mem CPU0 CPU1 CPU2 CPU3 Trace port Message processing Data Trace Ownership Trace Watchpoint Trace Configurable generic event processing structures Custom programmable processor Custom programmable FPGA fabric Instruction Instrution Reconstruction
16 Our Approach
17 Workflow
18 Workflow
19 Measurement Configurator
20 Events (address, tag, level, distinctor, call, entry, exit, return) Events are generated for each basic block.
21 Events (address, tag, level, distinctor, call, entry, exit, return) The address of the basic block s first instruction.
22 Events (address, tag, level, distinctor, call, entry, exit, return) A custom field used to efficiently address statistic records in memory
23 Events (address, tag, level, distinctor, call, entry, exit, return) The loop nesting level of the basic block.
24 Events (address, tag, level, distinctor, call, entry, exit, return) A field to distinguish two loops with the same nesting level that lie directly after another.
25 Events (address, tag, level, distinctor, call, entry, exit, return) Is another routine called in the basic block?
26 Events (address, tag, level, distinctor, call, entry, exit, return) Is a routine entered with this basic block?
27 Events (address, tag, level, distinctor, call, entry, exit, return) Is a routine exited with this basic block?
28 Events (address, tag, level, distinctor, call, entry, exit, return) Did a return from a called routine happen?
29 Measurement Configurator Enter f, Call g (0x1004, 1, 0, 0, 1, 1, 0, 0)
30 Measurement Configurator Enter g, Enter L1 (0x2000, 2, 1, 0, 0, 1, 0, 0)
31 Measurement Configurator Enter L2 (0x202c, 3, 2, 0, 0, 0, 0, 0)
32 Measurement Configurator Leave L2, Enter L3 (0x2050, 5, 2, 1, 0, 0, 0, 0)
33 Measurement Configurator Leave g (0x207c, 8, 0, 0, 0, 0, 1, 0)
34 Workflow
35 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59
36 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59 Execution Time of 0x cycles
37 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59 Execution Time of 0x cycles
38 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59 Execution Time of 0x cycle
39 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59 Execution Time of 0x cycle Pure maximisation gives 2 cycles.
40 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59 Execution Time of 0x cycle Pure maximisation gives 2 cycles. We want to take typical cache behaviour into account!
41 Event Stream (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59 Execution Time of 0x cycle Pure maximisation gives 2 cycles. Idea: Distinguish between first and all other loop iterations.
42 Loop Iteration State Machine A state is a data structure that keeps track of the call stack, the loop nesting level and whether we are in the first or in a later iteration of a loop. Calling a routine / returning from a routine changes the state. Entering / leaving a loop changes the state.
43 States The pointer to the active row.
44 States Is the row valid?
45 States The id identifies a loop or a routine.
46 States The index discriminates between first and further iterations.
47 State Transformations (0x1004, 1, 0, 0, 1, 1, 0, 0) (0x2000, 2, 1, 0, 0, 1, 0, 0) Routine Call, Increased Loop Nesting Level
48 State Transformations (0x1004, 1, 0, 0, 1, 1, 0, 0) (0x2000, 2, 1, 0, 0, 1, 0, 0) Routine Call, Increased Loop Nesting Level
49 State Transformations (0x2000, 2, 1, 0, 0, 1, 0, 0) (0x202c, 3, 2, 0, 0, 0, 0, 0) Entering a loop
50 State Transformations (0x2000, 2, 1, 0, 0, 1, 0, 0) (0x202c, 3, 2, 0, 0, 0, 0, 0) Entering a loop
51 State Transformations (0x2034, 4, 2, 0, 0, 0, 0, 0) (0x202c, 3, 2, 0, 0, 0, 0, 0) Recursively entering a loop
52 State Transformations (0x2034, 4, 2, 0, 0, 0, 0, 0) (0x202c, 3, 2, 0, 0, 0, 0, 0) Recursively entering a loop
53 State Transformations (0x202c, 3, 2, 0, 0, 0, 0, 0) (0x2050, 5, 2, 1, 0, 0, 0, 0) Entering a different loop
54 State Transformations (0x202c, 3, 2, 0, 0, 0, 0, 0) (0x2050, 5, 2, 1, 0, 0, 0, 0) Entering a different loop
55 State Transformations (0x2050, 5, 2, 1, 0, 0, 0, 0) (0x206c, 7, 1, 0, 0, 0, 0, 0) Leaving a loop
56 State Transformations (0x2050, 5, 2, 1, 0, 0, 0, 0) (0x206c, 7, 1, 0, 0, 0, 0, 0) Leaving a loop
57 State Transformations (0x206c, 7, 1, 0, 0, 0, 0, 0) (0x207c, 8, 0, 0, 0, 0, 1, 0) Leaving a loop
58 State Transformations (0x206c, 7, 1, 0, 0, 0, 0, 0) (0x207c, 8, 0, 0, 0, 0, 1, 0) Leaving a loop
59 State Transformations (0x207c, 8, 0, 0, 0, 0, 1, 0) (0x101c, 9, 0, 0, 0, 0, 1, 1) Leaving a routine
60 State Transformations (0x207c, 8, 0, 0, 0, 0, 1, 0) (0x101c, 9, 0, 0, 0, 0, 1, 1) Leaving a routine
61 Example
62 Example first further (?,?,?,?, 1,?,?,?)
63 Example first further (?,?,?,?, 1,?,?,?) (0x1004, 1, 0, 0, 1, 1, 0, t+0
64 Example first further (0x1004, 1, 0, 0, 1, 1, 0, t+0 (0x2000, 2, 1, 0, 0, 1, 0, t+8
65 Example first further (0x2000, 2, 1, 0, 0, 1, 0, t+8 (0x202c, 3, 2, 0, 0, 0, 0, t+30
66 Example first further (0x202c, 3, 2, 0, 0, 0, 0, t+30 (0x2034, 4, 2, 0, 0, 0, 0, t+46
67 Example first further (0x2034, 4, 2, 0, 0, 0, 0, t+46 (0x202c, 3, 2, 0, 0, 0, 0, t+48
68 Example first further (0x202c, 3, 2, 0, 0, 0, 0, t+48 (0x2034, 4, 2, 0, 0, 0, 0, t+56
69 Example first further (0x2034, 4, 2, 0, 0, 0, 0, t+56 (0x202c, 3, 2, 0, 0, 0, 0, t+57
70 Example first further (0x202c, 3, 2, 0, 0, 0, 0, t+57 (0x2050, 5, 2, 1, 0, 0, 0, t+59
71 Example first further (0x2050, 5, 2, 1, 0, 0, 0, t+59 (0x205c, 6, 2, 1, 0, 0, 0, t+71
72 Example first further (0x205c, 6, 2, 1, 0, 0, 0, t+71 (0x2050, 5, 2, 1, 0, 0, 0, t+73
73 Example first further (0x2050, 5, 2, 1, 0, 0, 0, t+73 (0x205c, 6, 2, 1, 0, 0, 0, t+79
74 Example first further (0x205c, 6, 2, 1, 0, 0, 0, t+79 (0x2050, 5, 2, 1, 0, 0, 0, t+80
75 Example first further (0x2050, 5, 2, 1, 0, 0, 0, t+80 (0x206c, 7, 1, 0, 0, 0, 0, t+83
76 Example first further (0x206c, 7, 1, 0, 0, 0, 0, t+83 (0x2000, 2, 1, 0, 0, 1, 0, t+91
77 Example first further (0x2000, 2, 1, 0, 0, 1, 0, t+91 (0x202c, 3, 2, 0, 0, 0, 0, t+102
78 Example first further (0x202c, 3, 2, 0, 0, 0, 0, t+102 (0x2034, 4, 2, 0, 0, 0, 0, t+110
79 Example first further (0x2034, 4, 2, 0, 0, 0, 0, t+110 (0x202c, 3, 2, 0, 0, 0, 0, t+112
80 Example first further (0x202c, 3, 2, 0, 0, 0, 0, t+112 (0x2034, 4, 2, 0, 0, 0, 0, t+119
81 Example first further (0x2034, 4, 2, 0, 0, 0, 0, t+119 (0x202c, 3, 2, 0, 0, 0, 0, t+120
82 Example first further (0x202c, 3, 2, 0, 0, 0, 0, t+120 (0x2050, 5, 2, 1, 0, 0, 0, t+122
83 Example first further (0x2050, 5, 2, 1, 0, 0, 0, t+122 (0x205c, 6, 2, 1, 0, 0, 0, t+126
84 Example first further (0x205c, 6, 2, 1, 0, 0, 0, t+126 (0x2050, 5, 2, 1, 0, 0, 0, t+127
85 Example first further (0x2050, 5, 2, 1, 0, 0, 0, t+127 (0x205c, 6, 2, 1, 0, 0, 0, t+135
86 Example first further (0x205c, 6, 2, 1, 0, 0, 0, t+135 (0x2050, 5, 2, 1, 0, 0, 0, t+136
87 Example first further (0x2050, 5, 2, 1, 0, 0, 0, t+136 (0x206c, 7, 1, 0, 0, 0, 0, t+139
88 Example first further (0x206c, 7, 1, 0, 0, 0, 0, t+139 (0x207c, 8, 0, 0, 0, 0, 1, t+143
89 Example first further (0x207c, 8, 0, 0, 0, 0, 1, t+143 (0x101c, 9, 0, 0, 0, 0, 1, t+149
90 Example first further (0x101c, 9, 0, 0, 0, 0, 1, t+149 (?,?,?,?,?,?,?, t+155
91 Example first further Overall execution time estimate: Our method: 191 cycles Context insensitive: 258 cycles
92 Implementation
93 FPGA Implementation We are currently building a prototype based on a Xilinx Virtex 7 FPGA (xc7v585t) and RLDRAM. Most complicated part is the connection to the SoC s trace interface (i.e. event generation).
94 Resource Usage on FPGA Loop Iteration State Machine (~ 180 MHz) 3 BRAMs 470 Registers 398 LUTs Statistics Module (~ 130 MHz) 7 BRAMs 481 Registers 406 LUTs
95 Conclusion
96 The CONIRAS Approach Precise We account for typical (instruction) cache behaviour. Continuous We perform direct online aggretation at runtime. Non-intrusive We use the hardware support of modern SoCs. Measurement-Based Execution Time Estimation
97 The CONIRAS Approach Reduced pessimism Improved observability Scalability Statistics instead of piles of data
98 98
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