MCF5206 ColdFire Integrated Microprocessor User s Manual

Transcription

1 MCF5206 ColdFire Integrated Microprocessor User s Manual TM Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and µ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA, 1997 All Rights Reserved.

2

3 DOCUMENTATION FEEDBACK FAX Documentation Comments Only (no technical questions please) http: / / Documentation Feedback Only The Technical Communications Department welcomes your suggestions for improving our documentation and encourages you to complete the documentation feedback form at the World Wide Web address listed above. In return for your efforts, you will receive a small token of our appreciation. Your help helps us measure how well we are serving your information requirements. The Technical Communications Department also provides a fax number for you to submit any questions or comments about this document or how to order other documents. Please provide the part number and revision number (located in upper right-hand corner of the cover) and the title of the document. When referring to items in the manual, please reference by the page number, paragraph number, figure number, table number, and line number if needed. Please do not fax technical questions to this number. When sending a fax, please provide your name, company, fax number, and phone number including area code. For Internet Access: Web Only: http: // For Hotline Questions: FAX (US or Canada): MOTOROLA MCF5206 USER S MANUAL iii

4 Applications and Technical Information For questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. Sales Offices Field Applications Engineering Available Through All Sales Offices UNITED STATES ALABAMA, Huntsville (205) ARIZONA, Tempe (602) CALIFORNIA, Agoura Hills (818) CALIFORNIA, Los Angeles (310) CALIFORNIA, Irvine (714) CALIFORNIA, Rosevllle (916) CALIFORNIA, San Diego (619) CALIFORNIA, Sunnyvale (408) COLORADO, Colorado Springs (719) COLORADO, Denver (303) CONNECTICUT, Wallingford (203) FLORIDA, Maitland (407) FLORIDA, Pompano Beach/ Fort Lauderdale (305) FLORIDA, Clearwater (813) GEORGlA, Atlanta (404) IDAHO, Boise (208) ILLINOIS, Chicago/Hoffman Estates (708) INDlANA, Fort Wayne (219) INDIANA, Indianapolis (317) INDIANA, Kokomo (317) IOWA, Cedar Rapids (319) KANSAS, Kansas City/Mission (913) MARYLAND, Columbia (410) MASSACHUSETTS, Marborough (508) MASSACHUSETTS, Woburn (617) MICHIGAN, Detroit (313) MINNESOTA, Minnetonka (612) MISSOURI, St. Louis (314) NEW JERSEY, Fairfield (201) NEW YORK, Fairport (716) NEW YORK, Hauppauge (516) NEW YORK, Poughkeepsie/Fishkill (914) NORTH CAROLINA, Raleigh (919) OHIO, Cleveland (216) OHIO, Columbus/Worthington (614) OHIO, Dayton (513) OKLAHOMA, Tulsa (800) OREGON, Portland (503) PENNSYLVANIA, Colmar (215) Philadelphia/Horsham (215) TENNESSEE, Knoxville (615) TEXAS, Austin (512) TEXAS, Houston (800) TEXAS, Plano (214) VIRGINIA, Richmond (804) WASHINGTON, Bellevue (206) Seattle Access (206) WISCONSIN, Milwaukee/Brookfield (414) CANADA BRITISH COLUMBIA, Vancouver (604) ONTARIO, Toronto (416) ONTARIO, Ottawa (613) QUEBEC, Montreal (514) INTERNATIONAL AUSTRALIA, Melbourne (61-3) AUSTRALIA, Sydney (61(2) BRAZIL, Sao Paulo 55(11) CHINA, Beijing FINLAND, Helsinki Car Phone 358(49) FRANCE, Paris/Vanves 33(1) GERMANY, Langenhagen/ Hanover 49(511) GERMANY, Munich GERMANY, Nuremberg GERMANY, Sindelfingen GERMANY, Wiesbaden HONG KONG, Kwai Fong Tai Po INDIA, Bangalore (91-812) ISRAEL, Tel Aviv 972(3) ITALY, Milan 39(2)82201 JAPAN, Aizu 81(241) JAPAN, Atsugi 81(0462) JAPAN, Kumagaya 81(0485) JAPAN, Kyushu 81(092) JAPAN, Mito 81(0292) JAPAN, Nagoya 81(052) JAPAN, Osaka 81(06) JAPAN, Sendai 81(22) JAPAN, Tachikawa 81(0425) JAPAN, Tokyo 81(03) JAPAN, Yokohama 81(045) KOREA, Pusan 82(51) KOREA, Seoul MALAYSIA, Penang 82(2) (4) MEXICO, Mexico City 52(5) MEXICO, Guadalajara 52(36) Marketing 52(36) Customer Service 52(36) NETHERLANDS, Best (31) PUERTO RICO, San Juan (809) SINGAPORE (65) SPAIN, Madrid 34(1) or 34(1) SWEDEN, Solna 46(8) SWITZERLAND, Geneva 41(22) SWITZERLAND, Zurich 41(1) TAlWAN, Taipei 886(2) THAILAND, Bangkok (66-2) UNITED KINGDOM, Aylesbury 44(296) FULL LINE REPRESENTATIVES COLORADO, Grand Junction Cheryl Lee Whltely (303) KANSAS, Wichita Melinda Shores/Kelly Greiving (316) NEVADA, Reno Galena Technology Group (702) NEW MEXICO, Albuquerque S&S Technologies, lnc. (505) UTAH, Salt Lake City Utah Component Sales, Inc. (801) WASHINGTON, Spokane Doug Kenley (509) ARGENTINA, Buenos Aires Argonics, S.A. (541) HYBRID COMPONENTS RESELLERS Elmo Semiconductor (818) Minco Technology Labs Inc. (512) Semi Dice Inc. (310) iv MCF5206 USER S MANUAL MOTOROLA

5 PREFACE The MCF5206 ColdFire Integrated Microprocessor User s Manual describes the programming, capabilities, and operation of the MCF5206 device. Refer to the MCF5200 ColdFire Family Programmer s Reference Manual for information on the ColdFire Family of microprocessors. TRADEMARKS All trademarks reside with their respective owners. CONTENTS This user manual is organized as follows: Section 1: Introduction Section 2: Signal Description Section 3: ColdFire Core Section 4: Instruction Cache Section 5: SRAM Section 6: Bus Operation Section 7: System Integration Module (SIM) Section 8: Chip-Select Module Section 9: Parallel Port (General-Purpose I/O) Module Section 10: DRAM Controller Section 11: UART Module Section 12: M-Bus Module Section 13: Timer Module Section 14: Debug Support Section 15: IEEE Test Access Port (JTAG) Section 16: Electrical Characteristics Section 17: Mechanical Characteristics Appendix A: Memory Map Appendix B: Porting from M68K Architectures Index MOTOROLA MCF5206 USER S MANUAL v

6 TABLE OF CONTENTS Paragraph Page Number Title Number Section 1 Introduction 1.1 Background MCF5206 Features Functional Blocks ColdFire Processor Core Processor States Programming Model Data Format Summary Addressing Capabilities Summary Notational Conventions Instruction Set Overview Instruction Cache Internal SRAM DRAM Controller DUART Module Timer Module Motorola Bus (M-Bus) Module System Interface External Bus Interface Chip-Selects Bit Parallel Port (General-Purpose I/O) Interrupt Controller System Protection JTAG System Debug Interface Pinout and Package Section 2 Signal Description 2.1 Introduction Address Bus Address Bus - (A[27:24]/ CS[7:4]/ WE[0:3]) Address Bus - (A[23:0]) Data Bus - (D[31:0]) Chip-Selects Chip-Selects - (A[27:24]/ CS[7:4]/ WE[0:3]) MOTOROLA USER S MANUAL vii

7 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Chip-Selects - (CS[3:0]) Byte Write-Enables - (A[27:24]/ CS[7:4]/ WE[0:3]) Interrupt Control Signals Interrupt Priority Level/ Interrupt Request (IPL[2]/IRQ[7],IPL[1]/IRQ[4], IPL[0]/IRQ[1]) Bus Control Signals Read/Write (R/W) Size (SIZ[1:0]) Transfer Type (TT[1:0]) Access Type and Mode (ATM) Transfer Start (TS) Transfer Acknowledge (TA) Asynchronous Transfer Acknowledge (ATA) Transfer Error Acknowledge (TEA) Bus Arbitration Signals Bus Request (BR) Bus Grant - (BG) Bus Driven (BD) Clock and Reset Signals Clock Input (CLK) Reset (RSTI) Reset Out (RTS[2]/RSTO) Dram Controller Signals Row Address Strobes (RAS[1:0]) Column Address Strobes (CAS[3:0]) DRAM Write (DRAMW) UART Module Signals Receive Data (RxD[1], RxD[2]) Transmit Data (TxD[1], TxD[2]) Request To Send (RTS[1], RTS[2]/RSTO) Clear To Send (CTS[1], CTS[2]) Timer Module Signals Timer Input (TIN[2], TIN[1]) Timer Output (TOUT[2], TOUT[1]) M-Bus Module Signals M-Bus Serial Clock (SCL) M-Bus Serial Data (SDA) General-Purpose I/O Signals General-Purpose I/O (PP[7:4]/PST[3:0]) Parallel Port (General-Purpose I/O) (PP[3:0]/DDATA[3:0]) Debug Support Signals Processor Status (PP[7:4]/PST[3:0]) viii USER S MANUAL MOTOROLA

8 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Debug Data (PP[3:0]/DDATA[3:0]) Development Serial Clock (TRST/DSCLK) Break Point (TMS/BKPT) Development Serial Input (TDI/DSI) Development Serial Output (TDO/DSO) JTAG Signals Test Clock (TCK) Test Reset (TRST/DSCLK) Test Mode Select (TMS/BKPT) Test Data Input (TDI/DSI) Test Data Output (TDO/DSO) Test Signals Motorola Test Mode (MTMOD) High Impedance (HIZ) Signal Summary Section 3 ColdFire Core 3.1 Processor Pipelines Processor Register Description User Programming Model Data Registers (D0 D7) Address Registers (A0 A6) Stack Pointer (A7) Program Counter Condition Code Register Supervisor Programming Model Status Register Vector Base Register (VBR) Exception Processing Overview Exception Stack Frame Definition Processor Exceptions Access Error Exception Address Error Exception Illegal Instruction Exception Privilege Violation Trace Exception Debug Interrupt RTE and Format Error Exceptions TRAP Instruction Exceptions Interrupt Exception MOTOROLA USER S MANUAL ix

9 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Fault-on-Fault Halt Reset Exception Instruction Execution Timing Timing Assumptions MOVE Instruction Execution Times Section 4 Instruction Cache 4.1 Features Of Instruction Cache Instruction Cache Physical Organization Instruction Cache Operation Interaction With Other Modules Memory Reference Attributes Cache Coherency and Invalidation Reset Cache Miss Fetch Algorithm/Line Fills Instruction Cache Programming Model Instruction Cache Registers Memory Map Instruction Cache Register Cache Control Register (CACR) Access Control Registers (ACR0, ACR1) Section 5 SRAM 5.1 SRAM Features SRAM Operation Programming Model SRAM Register Memory Map SRAM Registers SRAM Base Address Register (RAMBAR) SRAM Initialization Power Management Section 6 Bus Operation 6.1 Features Bus And Control Signals Address Bus (A[27:0]) Data Bus (D[31:0]) x USER S MANUAL MOTOROLA

10 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Transfer Start (TS) Read/Write (R/W) Size (SIZ[1:0]) Transfer Type (TT[1:0]) Access Type and Mode (ATM) Asynchronous Transfer Acknowledge (ATA) Transfer Acknowledge (TA) Transfer Error Acknowledge (TEA) Bus Exceptions Double Bus Fault Bus Characteristics Data Transfer Mechanism Bus Sizing Bursting Read Transfers: Word, Longword, and Line Bursting Write Transfers: Word, Longword, and Line Burst-Inhibited Read Transfer: Word, Longword, and Line Burst-Inhibited Write Transfer: Word, Longword, and Line Asynchronous-Acknowledge Read Transfer Asynchronous Acknowledge Write Transfer Bursting Read Transfers: Word, Longword, and Line with Asynchronous Acknowledge Bursting Write Transfers: Word, Longword, and Line with Asynchronous Acknowledge Burst-Inhibited Read Transfers: Word, Longword, and Line with Asynchronous Acknowledge Burst-Inhibited Write Transfers: Word, Longword, and Line with Asynchronous Acknowledge Termination Tied to GND Misaligned Operands Acknowledge Cycles Interrupt Acknowledge Cycle Bus Errors Bus Arbitration Two Master Bus Arbitration Protocol (Two-Wire Mode) Multiple External Bus Master Arbitration Protocol (Three-Wire Mode) Alternate Bus Master Operation Alternate Master Read Transfer Using MCF5206 Termination Alternate Master Write Transfer Using MCF5206 Termination MOTOROLA USER S MANUAL xi

11 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Alternate Master Bursting Read Using MCF5206-Generated Transfer Termination Alternate Master Bursting Write Using MCF5206-Generated Transfer Termination Reset Operation Master Reset Normal Reset Software Watchdog Timer Reset Operation Section 7 System Integration Module 7.1 Introduction Features SIM Operation Module Base Address Register (MBAR) Bus Time-Out Monitor Spurious Interrupt Monitor Software Watchdog Timer Interrupt Controller Programming Model SIM Registers Memory Map SIM Registers Module Base Address Register (MBAR) SIM Configuration Register (SIMR) Interrupt Control Register (ICR) Interrupt Mask Register (IMR) Interrupt-Pending Register (IPR) Reset Status Register (RSR) System Protection Control Register (SYPCR) Software Watchdog Interrupt Vector Register (SWIVR) Software Watchdog Service Register (SWSR) Pin Assignment Register (PAR) Section 8 Chip-Select Module 8.1 Introduction Features Chip-Select Module I/O Control Signals xii USER S MANUAL MOTOROLA

12 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Chip-Select (CS[7:0]) Write Enable (WE[3:0]) Address Bus Data Bus Transfer Acknowledge (TA) Chip-Select Operation Chip-Select Bank Definition Base Address and Address Masking Access Permissions Control Features , 16-, and 32-Bit Port Sizing Termination Bursting Control Address Setup and Hold Control Global Chip-Select Operation General Chip-Select Operation NonBurst Transfer with No Address Setup and No Address Hold NonBurst Transfer with Address Setup NonBurst Transfer With Address Setup and Hold Burst Transfer Burst Transfer With Address Setup Burst Transfer With Address Setup and Hold Alternate Master Chip-select Operation Alternate Master NonBurst Transfer Alternate Master Burst Transfer Alternate Master Burst Transfer With Address Setup and Hold Programming Model Chip-Select Registers Memory Map Chip-Select Controller Registers Chip-Select Address Register (CSAR0 - CSAR7) Chip-Select Mask Register (CSMR0 - CSMR7) chip-select Control Register (CSCR0 - CSCR7) DeFAULT MEMORY Control Register (DMCR) Section 9 Parallel Port (General-Purpose I/O) Module 9.1 Introduction Parallel Port Operation Programming Model MOTOROLA USER S MANUAL xiii

13 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Parallel Port Registers Memory Map Parallel Port Registers Port A Data Direction Register (PADDR) Port A Data Register (PADAT) Section 10 DRAM Controller 10.1 Introduction Features DRAM Controller I/O Control Signals Row Address Strobes (RAS[0], RAS[1]) Column Address Strobes (CAS[0], CAS[1], CAS[2], CAS[3]) DRAM Write (DRAMW) Address Bus Data Bus DRAM Controller Operation Reset Operation Master Reset Normal Reset Definition of DRAM Banks Base Address and Address Masking Access Permissions Timing Page Mode Port Size/Page Size Address Multiplexing Normal Mode Operation NonBurst Transfer In Normal Mode Burst Transfer In Normal Mode Fast Page Mode Operation Burst Transfer In Fast Page Mode Page Hit Read Transfer In Fast Page Mode Page Hit Write Transfer in Fast Page Mode Page Miss Transfer in Fast Page Mode Bus Arbitration Burst Page Mode Operation Extended Data-Out (EDO) DRAM Operation Refresh Operation Alternate Master Use of the DRAM Controller xiv USER S MANUAL MOTOROLA

14 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Alternate Master Non-Burst Transfer in Normal Mode Alternate Master Burst Transfer in Normal Mode Alternate Master Burst Transfer in Burst Page Mode Limitations Programming Model DRAM Controller Registers Memory Map DRAM Controller Registers DRAM Controller Refresh Register (DCRR) DRAM Controller Timing Register (DCTR) DRAM Controller Address Registers (DCAR0 - DCAR1) DRAM Controller Mask Register (DCMR0 - DCMR1) DRAM Controller Control Register (DCCR0 - DCCR1) DRAM Initialization Example Section 11 UART Modules 11.1 Module Overview Serial Communication Channel Baud-Rate Generator/Timer Interrupt Control Logic UART Module Signal Definitions Transmitter Serial Data Output (TxD) Receiver Serial Data Input (RxD) Request-to-Send (RTS) Clear-to-Send (CTS) Operation Baud-Rate Generator/Timer Transmitter and Receiver Operating Modes Transmitter Receiver FIFO Stack Looping Modes Automatic Echo Mode Local Loopback Mode Remote Loopback Mode Multidrop Mode Bus Operation MOTOROLA USER S MANUAL xv

15 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Read Cycles Write Cycles Interrupt Acknowledge Cycles Register Description and Programming Register Description Mode Register 1 (UMR1) Mode Register 2 (UMR2) Status Register (USR) Clock-Select Register (UCSR) Command Register (UCR) Receiver Buffer (URB) Transmitter Buffer (UTB) Input Port Change Register (UIPCR) Auxiliary Control Register (UACR) Interrupt Status Register (UISR) Interrupt Mask Register (UIMR) Timer Upper Preload Register 1 (UBG1) Timer Upper Preload Register 2 (UBG2) Interrupt Vector Register (UIVR) Input Port Register (UIP) Output Port Data Registers (UOP1, UOP0) Programming UART Module Initializatin I/O Driver Example Interrupt Handling UART Module Initialization Sequence Section 12 M-Bus Module 12.1 Overview Interface Features M-Bus System Configuration M-Bus Protocol START Signal Slave Address Transmission Data Transfer Repeated START Signal STOP Signal Arbitration Procedure Clock Synchronization Handshaking xvi USER S MANUAL MOTOROLA

16 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Clock Stretching Programming Model M-Bus Address Register (MADR) M-Bus Frequency Divider Register (MFDR) M-Bus Control Register (MBCR) M-Bus Status Register (MBSR) M-Bus Data I/O Register (MBDR) M-Bus Programming Examples Initialization Sequence Generation of START Post-Transfer Software Response Generation of STOP Generation of Repeated START Slave Mode Arbitration Lost Section 13 Timer Module 13.1 Overview of the Timer Module Overview of Key Features Understanding the General-Purpose Timer Units Selecting the Prescaler Working with Capture Mode Configuring the Timer for Reference Compare Configuring the Timer for Output Mode Programming Model Understanding the General-Purpose Timer Registers Timer Mode Register (TMR) Timer Reference Register (TRR) Timer Capture Register (TCR) Timer Counter (TCN) Timer Event Register (TER) Section 14 Debug Support 14.1 Real-Time Trace Background Debug Mode CPU Halt BDM Serial Interface BDM Command Set MOTOROLA USER S MANUAL xvii

17 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number BDM Command Set Summary ColdFire BDM Commands Command Sequence Diagram Command Set Descriptions Read A/D Register (RAREG/RDREG) Write A/D Register (WAREG/WDREG) Read Memory Location (READ) Write Memory Location (WRITE) Dump Memory Block (DUMP) Fill Memory Block (FILL) Resume Execution (GO) No Operation (NOP) Read Control Register (RCREG) Write Control Register (WCREG) Read Debug Module Register (REMREG) Write Debug Module Register (WDMREG) Unassigned Opcodes Real-Time Debug Support Programming Model Address Breakpoint Registers (ABLR, ABHR) Address Attribute Breakpoint Register (AATR) Program Counter Breakdown Register (PBR, PBMR) Data Breakpoint Register (DBR, DBMR) Trigger Definition Register (TDR) Configuration/Status Register (CSR) Theory of Operation Reuse of Debug Module Hardware Concurrent BDM and Processor Operation Motorola Recommended BDM Pinout Differences Between the ColdFire BDM and a CPU32 BDM Section 15 IEEE Test Access Port (JTAG) 15.1 Overview JTAG Pin Descriptions JTAG Register Descriptions JTAG Instruction Shift Register EXTEST Instruction ID Code SAMPLE/PRELOAD Instruction HIGHZ Instruction xviii USER S MANUAL MOTOROLA

18 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number CLAMP Instruction BYPASS Instruction ID Code Register JTAG Boundary-Scan Register JTAG Bypass Register TAP Controller Restrictions Disabling the IEEE Standard Operation Motorola MCF5206 BSDL Description Obtaining the IEEE Standard Section 16 Electrical Characteristics 16.1 Maximum Ratings Supply, Input Voltage and Storage Temperature Operating Temperature Thermal Resistance Output Loading DC Electrical Specifications AC Electrical Specifications Clock Input Timing Specifications Clock Input Timing Diagram Processor Bus Input Timing Specifications Input Timing Waveform Diagram Processor Bus Output Timing Specifications Output Timing Waveform Diagram Processor Bus Timing Diagrams Timer Module AC Timing Specifications Timer Module Timing Diagram UART Module AC Timing Specifications UART Module Timing Diagram M-BUS Module AC Timing Specifications INPUT Timing Specifications Between SCL and SDA Output Timing Specifications Between SCL and SDA Timing Specifications Between CLK and SCL, SDa M-Bus Module Timing Diagram General Purpose I/O Port AC Timing Specifications General Purpose I/O Port Timing Diagram MOTOROLA USER S MANUAL xix

19 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number IEEE (JTAG) AC Timing Specifications IEEE (JTAG) Timing Diagram Section 17 Mechanical Data Appendix A McF5206 Memory Map Summary Appendix B Porting From M68K Architecture B0.1 C Compilers and Host Software... B-1 B0.2 Target Software Port...B-1 B0.3 Initialization Code...B-2 B0.4 Exception Handlers...B-2 B0.5 Supervisor Registers...B-3 Index xx USER S MANUAL MOTOROLA

20 LIST OF ILLUSTRATIONS Figure Page Number Title Number 1-1. MCF5206 Block Diagram Programming Model ColdFire Processor Core Pipelines User Programming Model Supervisor Programming Mode Status Register Exception Stack Frame Form Instruction Cache Block Diagram Signal Relationships to CLK Internal Operand Representation MCF5206 Interface to Various Port Sizes Byte-, Word-, and Longword-Read Transfer Flowchart Longword-Read Transfer From a 32-Bit Port (No Wait States) Byte-, Word-, and Longword-Write Transfer Flowchart Word-Write Transfer to a 16-Bit Port (No Wait States) Bursting Word-, Longword-, and Line-Read Transfer Flowchart Bursting Word-Read From an 8-Bit Port (No Wait States) Word-, Longword-, and Line-Write Transfer Flowchart Line-Write Transfer to a 32-Bit Port (No Wait States) Burst-Inhibited Word-, Longword-, and Line-Read Transfer Flowchart Burst-Inhibited Longword Read From an 8-Bit Port (No Wait States) Burst-Inhibited Byte-, Word-, and Longword-Write Transfer Flowchart Burst-Inhibited Longword-Write Transfer to a 16-Bit Port (No Wait States) Byte-, Word-, and Longword-Read Transfer with Asynchronous Termination Flowchart (One Wait State) Byte-Read Transfer from an 8-Bit Port Using Asynchronous Termination (One Wait State) Byte-, Word-, and Longword-Write Transfer with Asynchronous Termination Flowchart Byte-Write Transfer to a 32-Bit Port Using Asynchronous Termination (One Wait State) PRE-FINAL DRAFT MOTOROLA USER S MANUAL xxi

21 LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number Bursting Word-, Longword-, and Line-Read Transfer with Asynchronous Termination Flowchart Bursting Longword-Read from 16-Bit Port Using Asynchronous Termination (One Wait State) Word-, Longword-, and Line-Write Transfer Flowchart with Asynchronous Termination Bursting Line-Write from 32-Bit Port Using Asynchronous Termination (One Wait State) Burst-Inhibited Word-, Longword-, and Line-Read Transfer with Asynchronous Termination Flowchart Burst-Inhibited Word Read from 8-Bit Port Using Asynchronous Termination Burst-Inhibited Word-, Longword-, and Line-Write Transfer with Asynchronous Termination Flowchart Burst-Inhibited Longword-Write Transfer to 16-Bit Port Using Asynchronous Termination (One Wait State) Example of a Misaligned Longword Transfer Example of a Misaligned Word Transfer Interrupt-Acknowledge Cycle Flowchart Interrupt Acknowledge Bus Cycle Timing (No Wait States) Bursting Longword-Read Access from 16-Bit Port Terminated with TEA Timing MCF5206 Two-Wire Mode Bus Arbitration Interface Two-Wire Implicit and Explicit Bus Ownership Two-Wire Bus Arbitration with Bus Lock Negated Two-Wire Bus Arbitration with Bus Lock Bit Asserted MCF5206 Two-Wire Bus Arbitration Protocol State Diagram Three-Wire Implicit and Explicit Bus Ownership Three-Wire Bus Arbitration with Bus Lock Bit Asserted MCF5206 Bus Arbitration Protocol State Diagram Alternate Master Read Transfer using MCF5206-Generated Transfer Acknowledge Flowchart Alternate Master Read Transfer Using MCF5206 Transfer Acknowledge Timing (No Wait States) Alternate Master Write Transfer Using MCF5206-Generated Transfer Acknowledge Flowchart Alternate Master Write Transfer Using MCF5206 Transfer-Acknowledge Timing (No Wait States) Alternate Master Bursting Read Transfer Using MCF5206-Generated Transfer-Acknowledge Flowchart Alternate Master Bursting Longword Read Transfer to an 8-Bit Port Using MCF5206 Transfer-Acknowledge Timing (No Wait States) PRE-FINAL DRAFT xxii USER S MANUAL MOTOROLA

22 LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number Alternate Master Bursting Write Transfer using MCF5206-Generated Transfer-Acknowledge Flowchart Alternate Master Bursting Longword Write Transfer to a 16-Bit Port Using MCF5206 Transfer Acknowledge Timing (No Wait States) Master Reset Timing Normal Reset Timing Software Watchdog Timer Reset Timing MCF5206 Interface to Various Port Sizes Longword Write Transfer from a 32-Bit Port (No Wait State, No Address Setup, No Address Hold) Word Write Transfer to a 16-Bit Port (One Wait State, Address Setup, No Address Hold) Byte Write Transfer from an 8-Bit Port (One Wait State, Address Setup, Address Hold) Longword Burst Read Transfer from a 16-Bit Port (No Wait States, No Address Setup, No Address Hold) Longword Burst Read Transfer from a 16-Bit Port (No Wait States, Address Setup, No Address Hold) Word Burst Read Transfer from an 8-Bit Port (No Wait States, Address Setup, Address Hold) Alternate Master Longword Read Transfer from a 32-Bit Port (No Wait State, No Address Setup, No Address Hold) Alternate Master Longword Read Transfer from a 16-bit Port (no wait state, no address setup, no address hold) Alternate Master Longword Read Transfer from a 16-Bit Port (No Wait State, With Address Setup Or Read Address Hold) Chip-Select and Write-Enable Assertion with ASET = 0 Timing Chip-Select and Write-Enable Assertion with ASET = 1Timing Address Hold Timing with WRAH = Address Hold Timing with WRAH = Address Hold Timing with RDAH = Address Hold Timing with RDAH = Default Memory Address Hold Timing with WRAH = Default Memory Address Hold Timing with WRAH = Default Memory Address Hold Timing with RDAH = Default Memory Address Hold Timing with RDAH = PRE-FINAL DRAFT MCF5206 Interface to Various Port Sizes Address Multiplexing For 8-bit DRAM With 512 byte Page Size Connection Diagram for 4 Mbyte DRAM with 8-bit Port and 1 kbyte Page MOTOROLA USER S MANUAL xxiii

23 LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number Connection Diagram for 1Mbyte DRAM with 8-bit Port and 1 kbyte Page Byte Read Transfers in Normal Mode with 8-bit DRAM Longword Write Transfer in Normal Mode with 16-bit DRAM Word Write Transfer in Fast Page Mode with 8-bit DRAM Longword Read Transfer Followed by a Page Hit Longword Read Transfer in Fast Page Mode with 32-bit DRAM Word Write Transfer Followed by a Page Hit Word Write Transfer in Fast Page Mode with 16-bit DRAM Byte Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page Mode with 8-bit DRAM Bus Arbitration in Fast Page Mode Longword Write Transfer Followed by a Word Read Transfer in Burst Page Mode with 16-bit DRAM Word Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page Mode with 8-bit EDO DRAM Alternate Master Byte Read Transfer Followed by Byte Write Transfer in Normal Mode with 16-bit DRAM Alternate Master Longword Write Transfer in Normal Mode with 16-bit DRAM Alternate Master Word Read Transfer in Burst Page Mode with 8-bit DRAM Normal Mode DRAM Transfer Timing Fast Page Mode or Burst Page Mode DRAM Transfer Timing Fast Page Mode or Burst Page Mode DRAM Transfer Timing Fast Page Mode Page Hit and Page Miss DRAM Transfer Timing Fast Page Mode or Burst Page Mode EDO DRAM Transfer Timing CAS before RAS Refresh Cycle Timing UART Block Diagram External and Internal Interface Signals Baud-Rate Timer Generator Diagram Transmitter and Receiver Functional Diagram Transmitter Timing Diagram Receiver Timing Diagram Looping Modes Functional Diagram Multidrop Mode Timing Diagram UART Software Flowchart PRE-FINAL DRAFT xxiv USER S MANUAL MOTOROLA

24 LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number M-Bus Module Block Diagram M-Bus Standard Communication Protocol Synchronized Clock SCL Flow-Chart of Typical M-Bus Interrupt Routine Timer Block Diagram Module Operation Processor/Debug Module Interface Pipeline Timing Example (Debug Output) BDM Signal Sampling Command Sequence Diagram Debug Programming Model pin Berg Connector Arranged 2 x Serial Transfer Illustration JTAG Test Logic Block Diagram JTAG TAP Controller State Machine Disabling JTAG in JTAG mode Disabling JTAG in Debug Mode MCF5206 Pin-out PRE-FINAL DRAFT MOTOROLA USER S MANUAL xxv

25 LIST OF TABLES Table Page Number Title Number 1-1. ColdFire MCF5206 Data Formats ColdFire Effective Addressing Modes Specific Effective Addressing Modes MOVE Specific Effective Addressing Modes Notational Conventions Supervisor-Mode Instruction Summary User-Mode Instruction Summary MCF5206 Signal Index Address Bus Byte Write-Enable Signals Boot CS[0] Automatic Acknowledge (AA) Enable Interrupt Request Encodings for CS[0] Data Transfer Size Encoding Bus Cycle Transfer Type Encoding ATM Encoding CAS Assertion Processor Status Encodings MCF5206 Signal Summary Exception Vector Assignments Format Field Encodings Fault Status Encodings Misaligned Operand References Move Byte and Word Execution Times Move Long Execution Times One Operand Instruction Execution Times Two Operand Instruction Execution Times Miscellaneous Instruction Execution Times General Branch Instruction Execution Times BRA, Bcc Instruction Execution Times Initial Fetch Offset vs. CLNF Bits Instruction Cache Operation as Defined by CACR[31, 10] Memory Map of I-Cache Registers External Fetch Size Based on Miss Address and CLNF MOTOROLA MCF5206 USER S MANUAL xxvii

26 LIST OF TABLES (Continued) Figure Page Number Title Number 5-1. Memory Map of SIM Registers Examples of Typical RAMBAR Settings SIZx Encoding Transfer Type Encoding ATM Encoding Chip Select, DRAM and Default Memory Address Decoding Priority SIZx Encoding for Burst- and Bursting-Inhibited Ports Address Offset Encoding Data Bus Requirement for Read Cycles Internal to External Data Bus Multiplexer - Write Cycle SIZx Encoding for Burst- and Bursting-Inhibited Ports MCF5206 Two-Wire Bus Arbitration Protocol Transition Conditions MCF5206 Two-Wire Arbitration Protocol State Diagram MCF5206 Three-Wire Bus Arbitration Protocol Transition Conditions MCF5206 Three-Wire Arbitration Protocol State Diagram Signal Source During Alternate Master Accesses Interrupt Levels for Encoded External Interrupts Interrupt Control Register Assignments Interrupt Mask Register Bit Assignments Interrupt Pending Register Bit Assignments PAR3 - PAR0 Pin Assignment Data Bus Byte Write-Enable Signals Maximum Memory Bank Sizes Chip-select, DRAM and Default Memory Address Decoding Priority Memory Map of Chip-select Registers BA Field Comparisons for Alternate Master Transfers IRQ4 and IRQ1 Selection of CS[0] Port Size IRQ7 Selection of CS[0] Acknowledge Generation Port Size Encodings Port Size Encodings Data Direction Register Bit Assignments Data Register Bit Assignments CAS Assertion Maximum DRAM Bank Sizes DRAM Bank Programming Example Chip-select, DRAM and Default Memory Address Decoding Priority DRAM Bank Programming Example xxviii MCF5206 USER S MANUAL MOTOROLA

27 LIST OF TABLES (Continued) Figure Page Number Title Number bit Port Size Address Multiplexing Configurations bit Port Size Address Multiplexing Configurations bit Port Size Address Multiplexing Configurations Bank Page Size Versus Actual DRAM Page Size Memory Map of DRAM Controller Registers UART Module Programming Model PMx and PT Control Bits B/CX Control Bits CMx Control Bits SBx Control Bits RCSx Control Bits TCSx Control Bits MISCx Control Bits TCx Control Bits RCx Control Bits M-Bus Interface Programmer s Model MBUS Prescalar Values Programming Model for Timers Processor PST Definition CPU-Generated Message Encoding BDM Command Summary BDM Size Field Encoding Control Register Map Definition of DRc Encoding - Read Definition of DRc Encoding - Write SZ Encodings Transfer Type Encodings Transfer Modifier Encodings for Normal Transfers Transfer Modifier Encodings for Alternate Access Transfers Core Address, Access Size, and Operand Location DDATA, CSR[31:28] Breakpoint Response Shared BDM/Breakpoint Hardware JTAG Pin Descriptions JTAG Instructions Boundary Scan Bit Definitions A--1. MCF5206 User Programming Model... A-1 MOTOROLA MCF5206 USER S MANUAL xxix

28 1 2 SECTION 1 INTRODUCTION 1.1 BACKGROUND The MCF5206 integrated microprocessor combines a ColdFire ª processor core with several peripheral functions such as a DRAM controller, timers, general-purpose I/O and serial interfaces, debug module, and system integration. Designed for embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system costs. To speed program execution, the on-chip instruction cache and SRAM provide one-cycle access to critical code and data. The MCF5206 greatly reduces the time required for system design and implementation by packaging common system functions onchip and providing glueless interfaces to 8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices. The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume applications new levels of price and performance. Based on the concept of variable-length RISC technology, ColdFire combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. The denser binary code for ColdFire processors consumes less valuable memory than any fixed-length instruction set RISC processor available. This improved code density means more efficient system memory use for a given application and requires slower, less costly memory to help achieve a target performance level. The integrated peripheral functions provide high performance and flexibility: The DRAM controller supports as much as 512 Mbytes of DRAM; support for both page-mode and extended-data-out DRAMs; programmable full duplex DUART and a separate I 2 C 1 - compatible Motorola bus (M-Bus interface). Two 16-bit general-purpose multimode timers provide separate input and output signals. For system protection, the processor includes a programmable 16-bit software watchdog timer and several bus monitors. In addition, common system functions such as chip-selects, interrupt control, bus arbitration, and IEEE Test (JTAG) support are included. A sophisticated debug interface supports both background-debug mode and real-time trace. This interface is common to all ColdFire-based processors and allows common emulator support across the entire ColdFire family. 1.2 MCF5206 FEATURES The primary features of the MCF5206 integrated processor include the following: 1. I 2 C is a trademark of Phillips MOTOROLA MCF5206 USERÕS MANUAL Rev

29 Introduction ColdFire Processor Core Ñ Variable-length RISC Ñ 32-bit internal address bus with 28 bit external bus Ñ chip-select and DRAM Ñ internal 32-bit decoding Ñ 32-bit data bus Ñ 16 user-visible 32-bit wide registers Ñ Supervisor / User modes for system protection Ñ Vector base register to relocate exception-vector table Ñ Optimized for high-level language constructs Ñ 17 MIPS at 33Mhz 512-Byte Direct-mapped instruction cache 512-Byte on-chip SRAM Ñ Provides one-cycle access to critical code and data DRAM Controller Ñ Programmable refresh timer provides CAS-before-RAS refresh Ñ Support for 2 separate memory banks Ñ Support for page-mode DRAMs and extended-data-out (EDO) DRAMs Ñ Allows external bus master access Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART) Ñ Full duplex operation Ñ Baud-rate generator Ñ Modem control signals available (CTS, RTS) Ñ Processor-interrupt capability Dual 16-Bit General-Purpose Multimode Timers Ñ 8-bit prescaler Ñ Timer input and output pins Ñ 30ns resolution with 33MHz system clock Ñ Processor-interrupt capability Motorola Bus (M-Bus) Module Ñ Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads Ñ Compatible with industry-standard I 2 C Bus Ñ Master or slave modes support multiple masters Ñ Automatic interrupt generation with programmable level System Interface Ñ Glueless bus interface to 8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices Ñ 8 programmable chip-select signals Ñ Programmable wait states and port sizes Ñ Allows external bus masters to access chip-selects Ñ System protection 1-2 MCF5206 USERÕS MANUAL Rev 1.0 MOTOROLA

30 Introduction 16-bit software watchdog timer with prescaler Double bus fault monitor Bus timeout monitor Spurious interrupt monitor Ñ Programmable interrupt controller Low interrupt latency 3 external interrupt inputs Programmable interrupt priority and autovector generator Ñ IEEE test (JTAG) support Ñ 8-bit general-purpose I/O interface System Debug Support Ñ Real-time trace Ñ Background debug interface Fully Static 5.0-Volt Operation 160 Pin QFP Package MOTOROLA MCF5206 USERÕS MANUAL Rev

31 Introduction FUNCTIONAL BLOCKS Figure 1-1 is a block diagram of the MCF5206 processor. The paragraphs that follow provide an overview of the integrated processor. 3 CLOCK INPUT CLOCK DRAM CONTROLLER DRAM CONTROL 4 JTAG INTERFACE JTAG SYSTEM B US CONTR OLLER CHIP SELECTS INTERRUPT CONTROLLER CHIP SELECTS INTERRUPT SUPPORT BDM INTERFACE 512 BYTE ICACHE 512 BYTE SRAM COLDFIRE CORE EXTERNAL BUS INTERFACE PARALLEL PORT DUART TIMERS M-BUS MODULE EXTERNAL BUS PARALLEL INTERFACE SERIAL INTERFACE TIMER SUPPORT M-BUS INTERFACE ColdFire Processor Core Figure 1-1. MCF5206 Block Diagram The ColdFire processor core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.the instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional RISC datapath with a dual-read-ported register file feeding an arithmetic/logic unit PROCESSOR STATES. The processor is always in one of four states: normal processing, exception processing, stopped, or halted. It is in the normal processing state 1-4 MCF5206 USERÕS MANUAL Rev 1.0 MOTOROLA