MCF5307 DRAM CONTROLLER. MCF5307 DRAM CTRL 1-1 Motorola ColdFire

Transcription

1 MCF5307 DRAM CONTROLLER MCF5307 DRAM CTRL 1-1

2 MCF5307 DRAM CONTROLLER MCF5307 MCF5307 DRAM Controller I Addr Gen Supports 2 banks of DRAM Supports External Masters Programmable Wait States & Refresh Timer 8K Unified Cache I Fetch1 I Fetch2 I Decode Instr Buf System Bus Controller Supports Page Mode and Burst Page Mode Supports 8-, 16-, & 32-bit wide DRAM banks 4K SRAM DUART Dec&Sel Op A Gen & Ex MAC DRAM Cntr & Chip Selects Interrupt Ctr Supports Extended Data Out DRAMs Supports Asynchronous or Synchronous DRAMs 2 Timers Debug Rev B Module General Purpose I/O 4 DMA JTAG PLL M-Bus MCF5307 DRAM CTRL 1-2

3 MCF5307 ASYNCHRONOUS & SYNCHRONOUS OPERATION THE DRAM CONTROLLER HAS 2 MAJOR MODES OF OPERATION: 1) ASYNCHRONOUS. Has 4 basic modes of operation: Non-page mode Burst page mode Contiguous page mode Extended Data Out mode 2) SYNCHRONOUS. Supports common SDRAM implementations. Burst page mode Continuous Page mode THESE 2 MODES WORK VERY DIFFERENTLY. The DRAM registers are used differently The DRAM pins are used differently Both banks of DRAM will be in the same mode of operation based on programming the DRAM Configuration Register s (DCR) Synchronous Operation bit (SO bit) MCF5307 DRAM CTRL 1-3

4 MCF5307 DRAM CONTROL REGISTER: ASYNC MODE When DCR[SO]=0, this register is defined as follows: DCR - DRAM CONTROL REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 SO - NAM RRA RRP RC Master RST: RRP- REFRESH PRECHARGED 00-1 CLOCK 01-2 CLOCKS 10-3 CLOCKS 11-4 CLOCKS RC- REFRESH COUNT CONTROLS THE FREQUENCY OF REFRESH PERFORMED BY THE DRAM CONTROLLER: (RC + 1) * 16 = REFRESH CLOCKS RRA- REFRESH ASSERTED 00-2 CLOCKS 01-3 CLOCKS 10-4 CLOCKS 11-5 CLOCKS NAM- NO ADDRESS MULTIPLEXING 1 - THE DRAM CONTROLLER WILL NOT MULTIPLEX THE EXTERNAL ADDRESS BUS 0 - THE DRAM CONTROLLER WILL MULTIPLEX THE EXTERNAL ADDRESS BUS SO- SYNCHRONOUS OPERATION 1 - SYNCHRONOUS MODE 0 - ASYNCHRONOUS MODE MCF5307 DRAM CTRL 1-4

5 MCF5307 ADDRESS & CONTROL REGISTERS: ASYNC MODE When DCR[SO]=0, this register is defined as follows: ACR0[31:0] & ACR1[31:0]-ADDRESS & CONTROL REGISTERS B31...B18 B17 B16 BA [31:18] - - RST: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RE - RP RNCN RCD - EDO PS PM - - RST: BA RE RP RNCN RCD EDO PS PM BASE ADDRESS. USED IN CONJUNCTION WITH THE BAM (MASK) BITS IN THE DCMR. COMPARED WITH BUS ADDRESS & MASK TO DETERMINE DRAM HIT OR MISS. REFRESH ENABLE (1 = Refresh associated DRAM bank 0 = Do not Refresh associated DRAM bank) COLUMN ADDRESS STROBE TIMING (00 = 1 CLK; 01 = 2 CLKS; 10 = 3 CLKS; 11 = 4 CLKS) PRECHARGE ENCODING (00 = 1 CLK; 01 = 2 CLKS; 10 = 3 CLKS; 11 = 4 CLKS) NEGATE TO NEGATE (0 = negated concurrently with ; 1= negated 1 CLK before ) TO DELAY (0 = 1 CLK; 1 = 2 CLK) EXTENDED DATA OUT (0 = EDO operation disabled; 1 = EDO operation enabled) PORT SIZE (00 = 32-bit port; 01 = 8-bit port; 10 =16-bit port; 11 =16-bit port) PAGE MODE (00 = No page mode; 01 =Page mode or bursts only; 10 = Reserved; 11 = Continuous page mode) MCF5307 DRAM CTRL 1-5

6 MCF5307 DRAM CONTROLLER MASK REGISTERS: ASYNC MODE When DCR[SO]=0, this register is defined as follows: DCMR0[31:0] & DCMR BASE[31:0]-DRAM CONTROLLER MASK REGISTERS B31...B18 B17 B16 BAM [31:18] - - RST: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RESERVED WP - C/I AM SC SD UC UD V RST: BAM BASE ADDRESS MASK. (0 =Associated address bit is compared in DRAM hit; 0 =Associated address bit is ignored in DRAM hit) WP WRITE PROTECT. (0 =Allow write accesses; 1 =Ignore write accesses) ADDRESS MODIFIER MASKS: (0 =Allow associated access type; 1 =Ignore associated access type) C/I CPU SPACE/ INTERRUPT ACKNOWLEDGE) AM ALTERNATE MASTER SC SD UC UD SUPERVISOR CODE SUPERVISOR DATA USER CODE USER DATA V VALID BIT ENCODING 0 = DRAM Accesses not decoded; 1 = DRAM Accesses decoded) MCF5307 DRAM CTRL 1-6

7 MCF5307 ASYNCHRONOUS MODE: SIGNAL DESCRIPTION TA M C F ADDR [A25-A17] TS [1:0] [3:0] DRAMRW DATA [31-0] [1:0] - ROW ADDRESS STROBE - USED TO SELECT 1 OF 2 DRAM BANKS. [3:0] - COLUMN ADDRESS STROBE - USED TO SELECT 1 OF 4-BYTE LANES IN A 32-BIT ORGANIZED MEMORY. DRAMRW - DRAM WRITE, ASSERTS TO SIGNIFY A WRITE OPERATION TO DRAM AND ALLOWS SEPARATE REFRESH CYCLES REGARDLESS TO R/W STATE. MCF5307 DRAM CTRL 1-7

8 MCF5307 ASYNCHRONOUS MODE: DRAM CONTROLLER INTERFACE TO 1 OF 2-BANKS TO OTHER DEVICES [3:0] M C F ADDR_BUS 0 WE 1 WE 2 3 WE 256Kx8 DRAM WE G [D24:31] [D16:23] [D8:15] [D0:7] D A T A B U DRAMW S DATA [31:0] CLOCK TS(OPTIONAL) ADDR ROW COLUMN ROW COLUMN RNCN =0 RNCN =0 DATA Data Data DRAMW TWO CONSECUTIVE READ CYCLES MCF5307 DRAM CTRL 1-8

9 MCF5307 ASYNC BURST PAGE MODE READ CLOCK TS ADDR ROW COLUMN COLUMN COLUMN DATA DRAMW RCD=0 =01 TA INTERNAL MCF5307 DRAM CTRL 1-9

10 MCF5307 ASYNC BURST PAGE MODE WRITE CLOCK TS ADDR ROW COLUMN COLUMN COLUMN DATA DRAMW TA RCD=0 =01 DATA DATA DATA MCF5307 DRAM CTRL 1-10

11 MCF5307 CONTINUOUS PAGE MODE CLOCK AS ADDR ROW COLUMN COLUMN COLUMN RCD=0 =01 PAGE HIT RNCN=1 PAGE MISS DATA DATA DATA DATA DRAMW TA MCF5307 DRAM CTRL 1-11

12 MCF5307 EDO READ OPERATION CLOCK TS ADDR ROW COLUMN DATA DRAMW RCD=0 =00 TA INTERNAL MCF5307 DRAM CTRL 1-12

13 MCF5307 ASYNCHRONOUS DRAM REFRESH CYCLE CLOCK DRAMW BEFORE REFRESH TIMING MCF5307 DRAM CTRL 1-13

14 MCF5307 DRAM CONTROL REGISTER: SYNCHRONOUS MODE When DCR[SO]=1, this register is defined as follows: DCR - DRAM CONTROL REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 SO IS NAM COC IP RTIM RC Master RST: RTIM- REFRESH TIMING (REFRESH TO ACTV, i.e. T RC ) 00-3 CLOCKS 01-6 CLOCKS 10,11-9 CLOCKS IP- INITIATE PRECHARGE ALL COMMAND 0 - TAKE NO ACTION 1 - INITIATE PALL COMMAND RC- REFRESH COUNT CONTROLS THE FREQUENCY OF REFRESH PERFORMED BY THE DRAM CONTROLLER: (RC + 1) * 16 = REFRESH CLOCKS COC- COMMAND ON CLOCK ENABLE 0 - CLOCK ENABLE ON SCKE PIN 1 - COMMAND ON SCKE PIN IS- INITIATE SELF REFRESH COMMAND 1 - INITIATE SELF REFRESH OR STAY IN SELF REFRESH 0 - TAKE NO ACTION OR EXIT SELF REFRESH SO- SYNCHRONOUS OPERATION 1 - SYNCHRONOUS MODE 0 - ASYNCHRONOUS MODE MCF5307 DRAM CTRL 1-14

15 MCF5307 ADDRESS & CONTROL REGISTERS: SYNC MODE When DCR[SO]=1, this register is defined as follows: ACR0[31:0] & ACR1[31:0]-ADDRESS & CONTROL REGISTERS B31...B18 B17 B16 BA [31:18] - - RST: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RE - L - CBM - IMRS PS1 PS0 - PM - - RST: BA RE L CBM PS PM BASE ADDRESS. USED IN CONJUNCTION WITH THE BAM (MASK) BITS IN THE DCMR. COMPARED WITH BUS ADDRESS & MASK TO DETERMINE DRAM HIT OR MISS. REFRESH ENABLE (1 = Refresh associated DRAM bank 0 = Do not Refresh associated DRAM bank) COLUMN ADDRESS STROBE LATENCY. DETERMINES HOW LONG THE DATA IS DELAYED AFTER THE SIGNAL IS ASSERTED. THIS CORRESPONDS TO THE t RCD SPECIFICATION. THIS ALSO IMPLIES OTHER TIMINGS, INCLUDING t, t RP, t RWL, & t EP. COMMAND & BANK MUX. SINCE DIFFERENT DRAM CONFIGURATIONS WILL CAUSE THE BANK & COLUMN BITS TO CORRESPOND TO DIFFERENT ADDRESSES, THESE BITS DETERMINE WHICH ADDRESS BITS THESE FUNCTIONS WILL BE MULTIPLEXED TO. PORT SIZE (00 = 32-bit port; 01 = 8-bit port; 10 =16-bit port; 11 =16-bit port) PAGE MODE (0 =Page mode or bursts only; 1= Continuous page mode) MCF5307 DRAM CTRL 1-15

16 MCF5307 DRAM CONTROLLER MASK REGISTERS: SYNC MODE When DCR[SO]=1, this register is defined as follows: This register is defined the same in Asynchronous & Synchronous modes DCMR0[31:0] & DCMR BASE[31:0]-DRAM CONTROLLER MASK REGISTERS B31...B18 B17 B16 BAM - - RST: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RESERVED WP - C/I AM SC SD UC UD V RST: BAM BASE ADDRESS MASK. (0 =Associated address bit is compared in DRAM hit; 0 =Associated address bit is ignored in DRAM hit) WP WRITE PROTECT. (0 =Allow write accesses; 1 =Ignore write accesses) ADDRESS MODIFIER MASKS: (0 =Allow associated access type; 1 =Ignore associated access type) C/I CPU SPACE/ INTERRUPT ACKNOWLEDGE) AM ALTERNATE MASTER SC SD UC UD SUPERVISOR CODE SUPERVISOR DATA USER CODE USER DATA V VALID BIT ENCODING 0 = DRAM Accesses not decoded; 1 = DRAM Accesses decoded) MCF5307 DRAM CTRL 1-16

17 POWER ON SEQUENCE Synchronous DRAMs have a prescribed power on sequence. The 5307 DRAM Controller supports this sequence by using the following procedure: Synchronous DRAM control signals are reset to the idle state. Firmware should wait the prescribed period before taking any action on the SDRAMs. Firmware should now: - Set up the DCR, ACR, & DCMR registers in their operational configuration. Do not yet enable refresh commands. - Issue the PALL command to the SDRAMs by setting the associated bit in the DCR. - Enable refresh & wait a period long enough for at least 8 refreshed to take place. - Issue the MRS command by setting the IMRS bit in the ACRs. MCF5307 DRAM CTRL 1-17

18 MODE REGISTER SET (MRS) COMMAND CLOCK ADDR TS DRAMR/W DATA CS MRS The DRAM Controller can configure SDRAMs with the MRS command. The MRS command is used to set burst operation & latency of 1, 2 or 3. The MRS command should set burst operation to a burst length of 1, or no burst. Addresses are incremented internally to the DRAM controller to allow fast accesses. Transfer size is 1, 2, 4 or 16 bytes. SDRAM mode register is written by: setting the base address & mask registers & the associated CBM bits, & setting ACR[IMRS]. MCF5307 DRAM CTRL 1-18

19 BURST PAGE MODE The advantage of synchronous DRAMs is the speed of data transfer once a page is opened. Once has been issued the SDRAM will accept a new address & every clock for accesses on that page. In burst page mode, if the transfer size is greater than the port size of the SDRAM, there will be multiple read or write operations for every ACTV command. As soon as the transfer is completed, the PALL command is generated to prepare for the next access. Synchronous Burst Page Mode accesses always follow this sequence: ACTV command NOP commands to ensure to delay Read or Write commands Sometimes NOPs are required here to ensure the ACTV to Precharge delay PALL command Required number of idle clocks to ensure Precharge to ACTV delay MCF5307 DRAM CTRL 1-19

20 BURST READ SDRAM ACCESS CLOCK ADDR TS DRAMR/W DATA Latency=2 Command Address CS DQM ACTV NOP READ PALL MCF5307 DRAM CTRL 1-20

21 BURST WRITE SDRAM ACCESS CLOCK ADDR TS DRAMR/W Latency=2 DATA Command Address CS DQM ACTV NOP WRITE PALL MCF5307 DRAM CTRL 1-21

22 CONTINUOUS PAGE MODE Continuous Page Mode is a variation in page mode which tries to balance performance complexity and size. With the internal pipelined bus of the Core, the DRAM Controller will predict whether the next bus cycle will hit in the same SDRAM: If the next bus cycle is not pending or misses in the page, the PALL command is generated to the SDRAM. This allow the precharge to be hidden in the current cycle. If the next bus cycle is pending and hits in the page, the page is left open & the next SDRAM access will begin with a read or write command. MCF5307 DRAM CTRL 1-22

23 SYNCHRONOUS CONTINUOS PAGE MODE ACCESS- READ FOLLOWED BY READ CLOCK ADDR TS DRAMR/W Latency=2 DATA Command Address CS DQM ACTV NOP READ NOP READ PALL Note there is no precharge between the 2 accesses. Also note the 2nd cycle begins with a read operation with no ACTV command. MCF5307 DRAM CTRL 1-23

24 CLOCK SYNCHRONOUS CONTINUOS PAGE MODE ACCESS- WRITE FOLLOWED BY READ ADDR TS DRAMR/W Latency=2 DATA Command Address CS DQM ACTV NOP WRITE NOP READ PALL Note that the 2nd cycle begins sooner after a write than after a read, since a read requires data to be returned before the bus cycle is terminated. In Continuous page mode, 2nd accesses will present multiplexed addresses. MCF5307 DRAM CTRL 1-24

25 AUTO-REFRESH OPERATION The DRAM Controller provides timing & control to refresh the SDRAM. If the refresh counter is set & refresh is enabled, the counter counts down to zero, an internal refresh request flag is set & the counter is reloaded & begins counting down again. When the refresh request flag is set, the DRAM Controller completes any active burst operation & then performs a precharge all operation, initiates a refresh cycle & clears the refresh request flag. MCF5307 DRAM CTRL 1-25

26 AUTO-REFRESH OPERATION CLOCK ADDR TS DRAMR/W Latency=2 Command Address CS PALL DESL REF DESL ACTV The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the bits. The REF command is then generated & the delay required by the DCR[RTIM] is inserted before the next ACTV command. MCF5307 DRAM CTRL 1-26

27 SELF REFRESH OPERATION CLOCK DRAMR/W Command Address CS CKE Latency=2 T RC = 6 PALL DESL SELF Self SELFX DESL First Refresh Possible Active ACTV Self-refresh is a method of allowing the SDRAM to enter a low power state & at the same time doing an internal refresh operation & maintaining the integrity of SDRAM data. The DCR[IS] bit turns on the Self-refresh operation. MCF5307 DRAM CTRL 1-27