DEVELOPMENT SUPPORT Development Support 1-1 Motorola ColdFire
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1 DEVELOPMENT SUPPORT 5307 Development Support 1-1
2 BACKGROUND DEBUG FEATURES REAL-TIME TRACE SUPPORT BDM SUPPORT REAL-TIME DEBUG SUPPORT - CONFIGURABLE HARDWARE BKPT - ADDRESS BKPT WITH RANGE CAPABILITY - DATA BKPT ON BYTE, WORD OR LONGWORD DATA INVERT BREAKPOINTS PROGRAM COUNTER BREAKPOINTS MASKING ON DATA AND PROGRAM COUNTER SINGLE AND DOUBLE LEVEL TRIGGERS ARE AVAILABLE PROGRAMMABLE TRIGGER RESPONSES - SHOW TRIGGER ON DDATA AND CAUSE NO INTERNAL RESPONSE - CAUSE A DEBUG INTERRUPT TO CPU - HALT CPU AND ENTER BDM BDM IS ENTERED FOR A VARIETY OF CONDITIONS AND EVENTS HIGH SPEED SYNCHRONOUS SERIAL BUS FOR COMMANDS & RESPONSES TRANSMISSION AND RECEPTION 5307 Development Support 1-2
3 DEVELOPMENT SUPPORT INTERFACE PINS DSO DSI DSCLK COLDFIRE C P U BKPT PST [3:0] PP[3:0]/ DDATA [3:0] BACKGROUND DEBUG PINS: DSO - DEBUG SERIAL DATA OUT DSI - DEBUG SERIAL DATA IN DSCLK - DEBUG SERIAL CLOCK BKPT - BREAK POINT INPUT BDM IS ENABLED BY ASSERTING BKPT PIN AT RESET BDM MAY BE IF BKPT ASSERTED WITHIN 8-CLK CYCLES AFTER RSTI NEGATES PST[3:0] DEFINITION 0000 CONTINUE EXECUTION 0001 BEGIN EXECUTION OF AN INSTRUCTION 0010 RESERVED 0011 ENTRY INTO USER MODE 0100 BEGIN EXECUTION OF PULSE INSTRUCTION 0101 BEGIN A BRANCH TAKEN INSTRUCTION 0110 RESERVED 0111 BEGIN EXECUTION OF AN RTE INSTRUCTION 1000 OUTPUT 1-BYTE TO DDATA PORT 1001 OUTPUT 2-BYTES TO DDATA PORT 1010 OUTPUT 3-BYTES TO DDATA PORT 1011 OUTPUT 4-BYTES TO DDATA PORT 1100 EXCEPTION PROCESSING 1101 EMULATOR-MODE ENTRY EXCEPTION PROC PROCESSOR STOPPED, WAITING FOR IRQ PROCESSOR IS HALTED OPCODE TRACKING PINS ENCODING 5307 Development Support 1-3
4 BREAKPOINT STATUS FIELD BREAKPOINT CSR [31:28] STATUS 0000 NO BREAKPOINTS ENABLED 0001 WAITING FOR LEVEL 1 BREAK POINT 0010 LEVEL 1 BREAKPOINT TRIGGERED 0011 RESERVED 0100 RESERVED 0101 WAITING FOR LEVEL 2 BREAKPOINT 0110 LEVEL 2 BREAKPOINT TRIGGERED 0111 RESERVED RESERVED 5307 Development Support 1-4
5 DEBUG PROGRAMMING MODEL DSCLK DSI DSO KDATA KADDR STALL CPU KDATA KADDR SERIAL PORT C O N T R O L CONT/STATUS HARDWARE REGISTERS TDR ABLR ABHR CSR DBR DBMR PBR PBMR AABR RDATA C O N T R O L FIFO MUXES PST FROM CPU 4 4 DDATA PST BDM MAY BE USEFUL FOR LOADING A TEST PROGRAM INTO MEMORY. EXTERNAL BREAKPOINT CAN HALT THE CPU BEFORE RESET EXCEPTION. BDM CAN CONFIGURE MEMORY AND REGISTERS AND THEN RESTART CPU WITH THE GO COMMAND Development Support 1-5
6 DEBUG REGISTERS B31...B0 ADDRESS BREAKPOINT REGISTER (ABLR) B31...B0 ADDRESS BREAKPOINT REGISTER (ABHR) B RM - READ/WRITE MASK SZM - SIZE MASK RM SZM TTM TMM R SZ TT TM ADDRESS ATTRIBUTE BREAKPOINT REG.(AABR) ( SETTING A MASK BIT WILL IGNORE COMPARISON) TTM - TRANSFER TYPE MASK TMM - TRANSFER MODIFIER TYPE R = READ/WRITE - COMPARED WITH K_BUS R/W SIGNAL SZ = SIZE - COMPARED WITH K_BUS SIZE SIGNALS TT = TRANSFER TYPE - COMPARED WITH K_BUS TT SIGNALS TM = TRANSFER MODIFIER - COMPARED WITH K_BUS TM SIGNALS 5307 Development Support 1-6
7 DEBUG REGISTERS (CONT d) B31...B0 PC BREAKPOINT REGISTER (PBR) B31...B0 PC BREAKPOINT MASK REGISTER (PBMR) TDR - TRIGGER DEFINITION REGISTER B TRC EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI B EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI B[31:16] DEFINE SECOND LEVEL TRIGGER B[15:0] DEFINE FIRST LEVEL TRIGGER TRC - TRIGGER RESPONSE 0 1 = PROCESSOR HALT 1 0 = DEBUG INTERRUPT 0 0 = SHOW ON DDATA LINES ONLY EBL - ENABLE BREAKPOINT LEVEL 1 = ENABLE GLOBAL BREAKPOINTS TRIGGER 0 = ALL BREAKPOINTS ARE DISABLED EDLW - ENABLE DATA BKPT FOR LONGWORD DATA EDWL - ENABLE DATA BKPT FOR LOWER DATA WORD EDWU - ENABLE DATA BKPT FOR UPPER DATA WORD EDLL - ENABLE DATA BKPT FOR LSB EDLM - ENABLE DATA BKPT FOR MLB DI - DATA BKPT INVERT EAI - ENABLE ADDRESS BKPT INVERTED EAR - ENABLE ADDRESS BKPT RANGE IN ABLR & ABHR EAL - ENABLE BKPT ADDRESS CONTAINED IN ABLR EPC - ENABLE PC BKPT PCI - ENABLE PC BKPT INVERTED 1 = ENABLE TRIGGER OUTSIDE REGION DEFINED BY PBR & PBMR 0 = ENABLE TRIGGER WITHIN REGION DEFINED BY PBR & PBMR EDUM - ENABLE DATA BKPT FOR MUB EDUU - ENABLE DATA BKPT FOR MSB 5307 Development Support 1-7
8 DEBUG CONFIGURATION AND STATUS CSR - CONFIGURATION/STATUS REGISTER B STATUS FOF TRG HALT BKPT RESERVED IPW B MAP TRC EMU DDC RFU BTB END NPL IPI SSM SBD KAD KOD KCD STATUS - BREAKPOINT STATUS 0000 = NO BREAKPOINTS ENABLED 0001 = WAITING FOR LEVEL 1 BREAK POINT 0010 = LEVEL 1 BREAKPOINT TRIGGERED 0101 = WAITING FOR LEVEL 2 BREAKPOINT 0110 = LEVEL 2 BREAKPOINT TRIGGERED FOF - FAULT ON FAULT STATUS 1 = FOF FORCED ENTRY INTO BDM, BIT IS CLEARED WHEN CSR IS READ TRG - HARDWARE BREAKPOINT TRIGGER 1 = HARDWARE BKPT HALTED CPU & FORCED BDM ENTRY BIT IS CLEARED WHEN CSR IS READ HALT - PROCESSOR HALT 1 = CPU EXECUTED HALT & FORCED BDM ENTRY BIT IS CLEARED WHEN CSR IS READ BKPT - BKPT ASSERT 1 = BKPT SIGNAL WAS ASSERTED & FORCED BDM ENTRY BIT IS CLEARED WHEN CSR IS READ IPW - INHIBIT CPU WRITES TO DEBUG REGISTERS BIT CAN ONLY BE SET BY A COMMAND ISSUED BY EXTERNAL DEVELOPMENT SYSTEM 5307 Development Support 1-8
9 DEBUG STATUS & CONFIGURATION (CONT d) B STATUS FOF TRG HALT BKPT RESERVED IPW B MAP TRC EMU DDC UHE BTB 0 NPL IPI SSM MAP - FORCE PROCESSOR REFERENCES IN EMULATOR MODE 1 = FORCE CPU TO MAP REFERENCES INTO SPECIAL ADDRESS 0 = ALL EMULATOR MODE REFERENCES ARE MAPPED TO SUPERVISOR DATA SPACE TRC - FORCE EMULATION MODE ON TRACE EXCEPTION EMU - FORCE CPU TO BEGIN EXECUTION IN EMULATOR MODE THIS BIT IS EXAMINED WHEN RSTI PIN IS NEGATED IPI - IGNORE PENDING INTERRUPTS 1 = IGNORE INTERRUPTS DURING SINGLE-INSTRUCTION-STEP MODE SSM - SINGLE-STEP MODE 1 = EXECUTE 1-INSTRUCTION AND HALT UPON HALT, BDM COMMANDS MAY BE EXECUTED DDC - DEBUG DATA CONTROL TO CAPTURE & DISPLAY DATA ON DDATA PORT 00 = NO OPERAND IS DISPLAYED 01 = CAPTURE ALL M-BUS WRITE DATA 10 = CAPTURE ALL M-BUS READ DATA 11 = CAPTURE ALL M-BUS READ/WRITE DATA UHE - USER HALT ENABLE MAKE HALT INSTRUCTION NON-PRIVILEGED BTB - BRANCH TARGET BYTES TO BE DISPLAYED ON DDATA PORT 00 = 0 BYTES 01 = LOWER 2-BYTES OF TARGET ADDRESS 10 = LOWER 3-BYTES OF TARGET ADDRESS 11 = ALL 4-BYTES OF TARGET ADDRESS NPL - NON-PIPLINED MODE 1 = NO OVERLAP OF INSTRUCTION EXECUTION 5307 Development Support 1-9
10 BACKGROUND MODE Program Execution HW BKPT or HALT Instruction or Fault On Fault or BKPT Signal PST = $F PST = $0 Background mode CPU HALTED WAITING FOR COMMANDS GO COMMAND Commands Responses BACKGROUND MODE IS ENTERED WHEN: BKPT SIGNAL IS ASSERTED HARDWARE BREAK POINT TRIGGERED FAULT ON FAULT CONDITION IS DETECTED HALT INSTRUCTION IS EXECUTED Target System DSCLK MCF5200 PST BKPT DSCLK DSI DSO HALT Development System view/modify registers dump memory etc Development Support 1-10
11 DEBUG MODE INSTRUCTIONS INSTRUCTION SIZE OPERATION! HALT UNSIZED HALT CPU AFTER ALL INSTRUCTIONS COMPLETE, AND DRIVE PST PINS WITH $F *PULSE UNSIZED TRIGGER EXTERNAL LOGIC BY POSTING $4 TO PST PORT WDDATA B, W, L SOURCE DDATA SIGNAL PINS *WDEBUG L WRITES TO DEBUG CONTROL REGISTER * PRIVILEGED INSTRUCTIONS! PRIVILEGE BY DEFAULT 5307 Development Support 1-11
12 BACKGROUND MODE COMMANDS COMMAND OPERATION RDREG Read Data Register RAREG Read Address Register WDREG Write Data Register WAREG Write Address Register RCREG Read System Control Register WCREG Write System Control Register READ Read Memory Location WRITE Write Memory Location DUMP Dump Memory Block FILL Fill Memory Block GO Resume Execution WDMREG Write Debug Register RDMREG Read Debug Register NOP No Operation SYNC Synchronize Instr. Pipeline 5307 Development Support 1-12
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