bdigdb for BDI3000 ARM11 / Cortex
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1 V1.01 V1.06 April 10, 2008 Error Correction Cortex-A8: Correct fast/stalled memory access sequences.
2 V1.01 V1.07 July 9, 2008 Support for ARM1176 and Cortex-M3 (STM32) added. Support for STM32F10xx internal flash programming added.
3 V1.01 V1.08 Aug. 29, 2008 Support for Luminary Micro Stellaris LM3S internal flash programming added. Support for Cortex-M3 / Cortex-A8 Single Wire Debug Mode added (different firmware).
4 V1.02 V1.09 Febr. 25, 2009 Support for Cortex-R4 added Support for ARM7 connected via JTAG-AP added (see manual). New parameter to select the single step mode added (see manual). New Telnet commands INTENA and INTDIS added. Error Correction Correct single step of newer ARMv6/v7 instructions.
5 V1.02 V1.10 Sept. 29, 2009 Support for DAP-Lite module added. Support for multiple A8/A9 debug components behind one DAP added. Support for searching nested ROM tables added. APB base address of the debug component can be preset (no ROM table search). Download speed via GDB improved. Support for a different reset type for the initial power-up reset added (see manual).
6 V1.02 V1.11 May 17, 2010 Support for Atmel SAM3U / SAM3S internal flash programming added. SWD: Single Wire Output can be routed to a TCP/IP channel (see manual).
7 V1.02 V1.12 August 20, 2010 Support for Cortex-M0 added. Support for LPC1xxx flash programming added.
8 V1.03 V1.13 Dec. 23, 2010 Support for STM32L15 internal flash programming added. Support for EFM32 internal flash programming added. A8: Correct handling of synchronous watchpoints (step over during a restart). Get actual number of implemented break/watch points from DIDR register. Error Correction M3: Correct sequence to set debug control bits (e.g. C_MASKINTS) before resume. A8/R4: Correct sequence to set PC before resume (use mov pc,r0 instead of bx r0).
9 V1.03 V1.14 April 1, 2011 Support for Cortex-M4 added. Support for Freescale Kinetis internal flash programming added. New EXEC init list entry added (see manual). Special DAPPC configuration parameter added for TI processors (see manual). New Telnet MMU command allows to disable / enable the MMU. New PMM (Physical Memory Mapped) register type accesses memory always with disabled MMU. The BDI no longer automatically steps over a GDB set breakpoint at the current PC. This allows to use the GDB jump command. Error Correction A8/R4: Correct setting of instruction HWBP (Byte Select in BCR) for Thumb / Big Endian code.
10 V1.03 V1.15 November 29, 2011 Support for STM32F2 and STM32F4 internal flash programming added.
11 V1.05 V1.16 June 22, 2012 New startup mode idle added. An idle core will not be accesses until attached via Telnet. New Telnet command state shows the state of all cores. New Telnet commands attach and detach added. New SCANINIT command m allows to write to AHB memory space. Windows setup tool works now also with COM ports >= 10. Windows setup tool accepts the config file name as command line parameter. Support for Spansion S29VS-R flash added (S29VSRX16 algorithm) The JTAG clock frequency can be entered in Hertz and not only as an index. GDB: The BDI now answers with 1 to the GDB qattached packet.
12 V1.05 V1.17 April 2, 2013 Support for STM32W internal flash added. Support for STM32F10 dual bank flash (XL-density) added. Maximal Telnet and GDB remote command length increased to 256 characters. Telnet command UPDATE added that allows to reload the configuration file without booting the BDI. The reset pin is no longer observed when reset mode NONE is defined. The Telnet commands attach and detach accept a core number as parameter. Kinetis: FSEC is programmed to unsecure also after a chip erase. Kinetis: Programming FSEC to a secure state is refused. Kinetis: Info about how to unsecure a secured device added (see kinetis_unsecure.cfg). Accept APB debug base addresses below 0x in order to support BCM5301x. Telnet access to FP registers for Cortex-A and Cortex-R added (rdfp and rmfp command). Support for Cortex-A5, Cortex-A7 and Cortex-A15 added. Cortex-A: Clear OS Lock Access bit after target power-up. Support for Cortex-M external flash programming with workspace added (Thumb algorithm). Output an error for not supported Flash/Buswidth combinations instead of simply loading the ARM algorithm. Support for simple bit manipulation (read/modify/write) via init list added. The RMx entry defines the address, the size and an optional XOR pattern. RM8 <address> [<xor<] RM16 <address> [<xor<] RM32 <address> [<xor<] WMX <and> <or> Example: RM32 0x x WMX 0xff00ff00 0x ;read and XOR ;AND, OR and write back Init list entry added that waits until memory becomes a defined value. The RMx entry defines the address and the size for the following WAIT. RM8 <address> RM16 <address> RM32 <address> WAIT <mask> <equal> Example: RM16 0x a WAIT 0x0000f0ff 0x ;define address and size ;wait until ((value & mask) == equal)
13 V1.05 V1.18 August 9, 2013 Support for STM32F0 internal flash added. Support for Kintetis FTFE and FTFA internal flash added. The WREG init list entry now accepts all names from the register definition file. Telnet access to 64-bit CPxx registers added (see user s manual). New Telnet command MODE allows to switch current processor mode. Cortex-A: New Telnet commands SECURE and NONSECURE allows to switch secure state. Cortex-M: AHB access port select parameter added. Used for Vybrid Cortex-M4 debug accesses.
14 V1.06 V1.19 March 5, 2014 Support for ARM BE8 big endian mode added. Cortex-A: Improved core halted detection. Cortex-A: A new configuration parameter enables CTI support and defines the APB base address of the CTI component. It also defines the core group used when GDB sends the "continue" command. New and changed Multi-Core related Telnet commands. Configuration and register definitions can be stored in the BDI internal Flash memory. In this case no TFTP server is necessary to load the configuration files.
15 V1.06 V1.20 May 30, 2014 The BREAKMODE configuration parameter allows to set the break/watch control bits SSC, HMC and PMC in DBGBCR and DBGWCR: BREAKMODE {SOFT HARD} [{HYP <control>}] HYP adds the hypervisor mode bit to the control value <control> defines the SSC, HMC and PMC bits in DBGBCR and DBGWCR Default is SSC=00, HMC=0 and PMC=11 (0x ) Examples: BREAKMODE SOFT BREAKMODE HARD BREAKMODE HARD HYP BREAKMODE HARD 0x ;control = 0x ;control = 0x ;control = 0x ;control = 0x New Telnet QUERY command to display parts of the configuration. QUERY [<core>] Examples: BDI> query displays common and core specific configuration for all cores BDI> query 1 displays the core specific configuration of the selected core Error Correction The CTI registers of not attached cores are no longer accessed during multi-core restart.
16 V1.06 V1.21 Nov. 4, 2014 Support for Freescale LS1 (ARMv7, LS1021A,...) added. SWAP option for register definitions added. Useful when accessing big endian registers from a little endian core or vice versa. A new configuration parameter option allows to define the protection bits for AHB/AXI accesses. For LS1, memory accesses via System Access Port (SAP) are supported. Maximal number of cores increased to 16.
17 V1.06 V1.22 July 3, 2015 Core halted detection: Check only HALT bit in DSCR, ignore Monitor Debug Mode. Process init list entries for running cores if possible (memory access AHB/SAP). Error Correction Cortex-R4: Correct handling of instruction big endian mode. Display correct STEPMODE in Telnet QUERY command. Display correct CPUTYPE in Telnet QUERY command for LS1000. Correct handling of core numbers > 9 (#nbr) in the configuration file.
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