Ultimate1MB expansion features

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Garey Stevenson
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Ultimate1MB expansion features Ultimate1MB expansion was designed with few things in my mind: to be as much solderless as possible (only RW, PHI2, HALT and RESET lines need soldering) fully flashable

1 Ultimate1MB expansion features Ultimate1MB expansion was designed with few things in my mind: to be as much solderless as possible (only RW, PHI2, HALT and RESET lines need soldering) fully flashable SpartaDOS-X with up to 256kbytes for its purposes additional 64k space for GUI RTC module for SDX with battery backup and NVRAM fully flashable 4 OS ROM slots hardware WRITE PROTECT for whole Flash array configurable memory expansion with 4 modes of operation: disabled - no extra memory is visible to the system 320k RAMBO - 256k of extra memory is visible both to CPU and ANTIC chips 578k COMPY SHOP - 512k of extra memory is visible to CPU and ANTIC chip, bit 4 and 5 works in 130XE compatibility mode 1088k RAMBO - 1MB of extra memory is visible to CPU and ANTIC chips customizable BASIC and MISSLE COMMAND slots (also flashable) PBI frontend for non-pbi devices (namely SIDE cartridge) BIOS to enable jumperless operation and configuration for the board, plus some means of controlling external hardware (VBXE, SimpleStereo, or any other hardware that takes binary signals for configuration) 1 of 8

2 How it works? Since solderless approach was the main driving force behind this, some portions of PIA and GTIA chips had to be simulated within the CPLD chip. When PORTB write is detected, hardware checks if internal shadow of PBCTL (D303) allows writes, and if so, value from Data bus is written to PORTB shadow. In the parallel, last value of PORTB shadow registers is stored into internal MMU CONTROL register to preserve current status of system ROM, basic, self-test and Missle Command ROM chips mappings, thus allowing flowless access to whole extended memory array. Since there is internal SDX module care had to be taken for GTIA TRIG3 register. Normally RD5 line from cartridge port is connected both to MMU chip and GTIA TRIG3 lines and since the goal was to incorporate this extension without the need of cutting any traces on motherboard, this register had to be shadowed (OS checks for TRIG3 status on every NMI, if there is a change on state of this line, OS assumes that cartridge was put in/removed and to prevent failures goes into endless loop). With this shadow of TRIG3 register system can be fooled, and enabling or disabling "external" (to SDX module) cartridges can be done. Lastly, there is configuration register which is used for configuring the extension according to configuration data stored in NVRAM - user can choose which OS ROM should be booted on power-on, what memory size machine should have and if SDX and RTC modules should be enabled. Every time RESET button is pressed, Ultimate1MB BIOS kicks in, and checks if HELP key is pressed. If so, then interactive menu pops up, enabling user to change current configuration. Otherwise, checksum is calculated from the bytes read from NVRAM, if this matches checksum read from NVRAM, then configuration is assumed as valid one, and written into configuration registers. Then normal boot follows. 2 of 8

3 Registers description D301 D303 PORTBS (WO) Bits are mapped according to Atari mappings PBCTLS (WO) Bit 2 - if set to zero, PORTB writes are disabled, also at D380 UCTL register is enabled, also physical PIA chip won't be read or written to at D380 D380 UCTL (WO) Bits Memory expansion configuration mode 00 - Memory disabled k RAMBO k COMPY SHOP K RAMBO Bits System Select 00 - ROM Slot ROM Slot ROM Slot ROM Slot 4 Bit 4 - SDX disable, when set, SDX module is disabled Bit 5 reserved, should be written 0 Bit 6 IO RAM if set, 0xD000-0xD7FF becomes RAM Bit 7 CONFIG_L if set, futher writes to D380 are disabled, making configuration permanent until next RESET D381 UAUX (WO) Bit 0 state of pin M0 Bit 1 state of pin M1 Bit 2 state of pin S0 Bit 3 state of pin S1 Bits 4-5 VBXE decoder mode 00 - Decoder enabled, 0xD6xx as base address 01 Decoder enabled, 0xD7xx as base address 3 of 8

4 1x Decoder disabled, VBXE writes prohibited Bit 6 SoundBoard decoder (0xD2C0-0xD2FF) (0) disabled, (1) enabled Bit 7 Write protect if set, flash array is protected, and can't be written or erased D382 UPBI/UCAR (WO) Bits 0-1 Side PBI BUS ID 00 Bus ID 0 01 Bus ID 2 10 Bus ID 4 11 Bus ID 6 Bit 2 Side PBI Driver Enable (1) or Disable (0) Bit 3 Side button operation, if set (1), Side button operates as ATR cycle button, enabling multi-disk games to work without the need of getting into interactive menu for swapping the disks, else Side button works as normal Bits 4-5 Basic Slot select 00 Slot 0 01 Slot 1 10 Slot 2 11 Slot 3 Bits 6-7 Missle command Slot Select (XEGS mode only) 00 Slot 0 01 Slot Slot 2 11 Slot 3 4 of 8

5 SDX Registers D5E0 D5E1 D5E2 D5E2 Bits 5-0 BANKNO (WO) Bank number. Banks 0-53 are valid for SDX module. Bank 54 is BASIC ROM, bank 55 is MISSILE COMMAND or any other 8k game ROM image, banks are for OS ROM slots. Access to all banks is provided through this port for flashing purposes Bits 7-6 Reserved for future use, should be written 0 Bit 0 Bit 1 SDXCTL (WO) External Cartridge. When set (1), and bit 1 is set, external cartridge is OFF, SDX is OFF When reset (0), and bit 1 is set, external cartridge is ON, SDX is OFF SDX Disable. When reset (0), SDX is ON, external cartridge is always OFF When set (1), SDX is OFF, external cartridge is controlled via bit 1 Bits 6-2 Reserved for future use, should be written 0 Bit 7 Reserved for future use, should be written 1 Bit 0 Bit 1 Bit 2 Bits 7-3 Bit 0-2 Bit 3 Bit 7-4 RTCOUT (W) Chip Enable SPI Clock SPI MOSI (Master Out, Slave In) Reserved RTCIN (R) Reserved SPI MISO (Master In, Slave Out) Reserved 5 of 8

6 PBI frontend registers D1BF Bits 0-1 Bits 2-7 UPBIBANK (WO) Bank number, bank number gets reset to 00 when device is deactivated, or RESET was pressed Reserved When PBI frontend is activated (by OS writing appropriate value to 0xD1FF), 0xD500-0xD5BF, 0xD100-0xD1BE and 0xD600-0xD7FF becomes RAM of PBI device allowing it to use it as buffers and general data holders. Note should be made, that 0xD600-0xD7FF is also used as space for BIOS initialisation, and thus should be treated as VIOLATE are (gets wiped each time RESET is pressed). 6 of 8

7 Ultimate1MB FLASH Chip Memory Map 0x x03FFFF SDX 0x x04FFFF Reserved for GUI 0x x053FFF BIOS code space 0x x05FFFF PBI driver (each bank is padded to full 8k) 0x x067FFF BASIC slots 0x x06FFFF 8k GAME cartridge (Missle Command) 0x x073FFF 1st OS slot 0x x077FFF 2nd OS slot 0x x07BFFF 3rd OS slot 0x07C000-0x07FFFF 4th OS slot Ultimate1MB BIOS details When building an image for flashing whole flash array, it may be convinient to change default labels for things like OS slots or BASIC/GAME slots, to do so, one needs to know where they are located. Each entry is 32 bytes long, and consist of ANTIC internal character codes, here are their offsets in BIOS space area: 0x x0520A0 0x0520C0 0x0520E0 0x x x x x x0524A0 0x0524C0 0x0524E0 First OS slot Second OS slot Third OS slot Fourth OS slot First BASIC slot Second BASIC slot Third BASIC slot Fourth BASIC slot First GAME slot Second GAME slot Third GAME slot Fourth GAME slot 7 of 8

8 Another customizable lines are Stereo sound and Covox lines, their defined as follows: 0x Stereo sound Options 1-4 (each option is 32 bytes long ANTIC internal character string) 0x Covox Options 1-4 Since these options, change values of S0-S1 and M0-M1 pins, there is a table that is used for mapping these options to respective pins (see UAUX register description) 0x05078D 0x Stereo sound pin definitions (4 bytes, with bit mask defined at 0x0507A9) Covox pin definitions (4 bytes, with bit mask defined at 0x0507AA) Example: You want to have Expansion1 or and off from BIOS level, you need to define 4 (number of available options is always 4, if there is a less than that, you'll have to repeat them), so you'll need to modify BIOS ROM image like this: Starting at 0x052200: dta d'expansion1: Disabled ' dta d'expansion1: Enabled ' dta d'expansion1: Disabled ' dta d'expansion1: Enabled ' Also, you want it to be controlled through M1 pin, lets say that logic 1 corresponds to expansion turned off, and 0 for on: Starting at 0x05078D dta b(0x02,0x00,0x02,0x00) ; bit 1 of UAUX is M1 We also need to define MASK for these values, so only bits we're intend to change get changed: at 0x0507A9 dta b(0x02) 8 of 8

The 9S12 in Expanded Mode - Using MSI logic to build ports Huang Chapter 14

The 9S12 in Expanded Mode - Using MSI logic to build ports Huang Chapter 14 Using MSI Logic To Build An Output Port Many designs use standard MSI logic for microprocessor expansion This provides an inexpensive