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1 T1X1.3/98-022R2 CONTRIBUTION TO T1 STANDARDS PROJECT **************************************************************************************************** STANDARDS PROJECT: Specification and Allocation of Integrated Services Digital Networks Performance (T1Q1 10) **************************************************************************************************** TITLE: Initial Draft Text for T1 Technical Report on the Effect of ATM Network Timing on CBR Service Clock Recovery and Synchronization Performance **************************************************************************************************** AUTHOR: SOURCE: Geoffrey Garner (Editor) CONTACT: S. J. (John) Chen Lucent Technologies 101 Crawfords Corner Road, Room 4L-332 Holmdel, NJ (908) **************************************************************************************************** Date: September, 1998 **************************************************************************************************** DISTRIBUTION: T1X1.3 Working Group **************************************************************************************************** ABSTRACT This contribution contains revised draft text for the T1 Technical Report on the Effect of ATM Network Timing on CBR Service Clock Recovery and Synchronization Performance. The latest revisions are based on discussion during the presentation at the July, 1998 T1X1.3 meeting. **************************************************************************************************** NOTICE This document has been prepared to assist the Standard Committee T1- Telecommunications. It is offered to the Committee as a basis for discussion and is not a binding proposal on Lucent Technologies. The requirements presented in this document are subject to change in form and numerical value after more study. Lucent Technologies specifically reserves the right to add to, or amend the statements contained within.

2 T1X1.3/98-022R2 1. SUMMARY This contribution contains revised draft text for the T1 Technical Report on the Effect of ATM Network Timing on CBR Service Clock Recovery and Synchronization Performance. The latest revisions are based on discussion during the presentation at the July, 1998 T1X1.3 meeting. In many instances, T1X1.3 indicated the nature of the change needed but not the detailed text. It was initially decided that a breakout group would be formed to make the detailed modifications and report back to the group before the end of the meeting. However, interest in participating in the breakout group was limited, and the few who were interested were eventually unable to participate because they needed to participate in other breakout groups. Eventually, it was decided that the editor would make the changes indicated during the initial presentation and present the revised document at the following T1X1.3 meeting (September, 1998). Text for Section on MPEG-2 Video was supplied by [1]. 2. REFERENCES [1] Al White, of September 10, 1998.

3 A TECHNICAL REPORT ON THE EFFECT OF ATM NETWORK TIMING ON ATM CONSTANT BIT RATE SERVICE CLOCK RECOVERY AND SYNCHRONIZATION PERFORMANCE Abstract This technical report assesses the effects of differences in distinct timing sources on services supported by existing ATM Synchronous Residual Time Stamp (SRTS) methodology, and explores potential enhancements to AAL Type 1. The report describes the effects of these network timing differences on synchronous clock recovery techniques, the possible use of asynchronous (adaptive) techniques and/or recentering heuristics to mitigate the effects of these timing differences, and the effect of ATM cell delay variability (CDV) on the adaptive techniques and recentering heuristics. As part of the latter, the report considers the characterization of CDV (both peak-to-peak CDV and the correlation of the delays of successive cells) and its dependence on network connection and traffic mix models. Document T1X1.3/ Prepared by T1X1.3 Working Group on Synchronization and Tributary Analysis

4 T1X1.3/98-022R2 Foreword This technical report assesses the effects of differences in distinct timing sources on services supported by existing ATM Synchronous Residual Time Stamp (SRTS) methodology, and explores potential enhancements to AAL Type 1. The report describes the effects of these network timing differences on synchronous clock recovery techniques, the possible use of asynchronous (adaptive) techniques and/or recentering heuristics to mitigate the effects of these timing differences, and the effect of ATM cell delay variability (CDV) on the adaptive techniques and recentering heuristics. As part of the latter, the report considers the characterization of CDV (both peak-to-peak CDV and the correlation of the delays of successive cells) and its dependence on network connection and traffic mix models. This work was initiated and completed by the T1X1.3 Working Group between 1997 and 19. The decision to initiate this work was taken at the joint T1X1.3/T1A1.3 meeting held in Plano, TX, in January, This document represents the information developed by Working Group T1X1.3 at this time. Please contact Working Group.T1X1.3 to verify that the information contained in this document is current.

5 1. SCOPE ABBREVIATIONS AND ACRONYMS DEFINITIONS INTRODUCTION TYPES OF CIRCUIT EMULATION SERVICES SYNCHRONOUS CIRCUIT TIMING ASYNCHRONOUS CIRCUIT TIMING CLOCK RECOVERY FOR CONSTANT BIT RATE SERVICES TRANSPORTED OVER ATM NETWORKS SYNCHRONOUS METHODS SRTS (Requires AAL Type 1) ASYNCHRONOUS METHODS Adaptive Clock Recovery Methods Recentering Heuristics EFFECT OF DIFFERENCES IN TIMING AT AAL TRANSMITTER AND RECEIVER ON RECOVERED CBR SERVICE CLOCK TIMING SOURCES PRS-TRACEABLE DS1 Wander DS1 Jitter DS3 Wander DS3 Jitter DS3 Video IMPACT OF NETWORK CLOCK IMPAIRMENTS ON SERVICE CLOCK RECOVERY ONE OR BOTH TIMING SOURCES IN HOLDOVER OR TRACEABLE TO CLOCK(S) IN HOLDOVER DS1 and DS3 Misframes SRTS Method - Plesiochronous mode of operation SRTS and Clock Failures Use of Adaptive Clock Recovery Techniques Use of Controlled Slip Mechanism in AAL Type Use of AAL Type 1 Receiver Buffer Recentering Heuristics DS1 and DS3 Jitter DS1 and DS3 Wander DS3 Video MPEG-2 Video CHARACTERIZATION OF ATM CELL DELAY VARIABILITY AND EFFECT ON CBR CLOCK RECOVERY PEAK-TO-PEAK CDV (1-POINT AND 2-POINT) TDEV MTIE DEPENDENCE ON ATM NETWORK TRAFFIC MIX, TRAFFIC VOLUME, AND TRAFFIC MODELS REFERENCES APPENDIX 1. AAL MEASUREMENT POINTS AND REFERENCE EVENTS

6 APPENDIX 2. DESCRIPTION OF SYNCHRONOUS RESIDUAL TIME STAMP METHOD APPENDIX 3. DESCRIPTION OF STATISTICS AND ESTIMATORS FOR CHARACTERIZING POWER- LAW TYPE NOISE PROCESSES APPENDIX 4. HYPOTHETICAL REFERENCE MODELS AND JITTER AND WANDER BUDGETS A4.1 DS1 REFERENCE MODEL AND JITTER AND WANDER BUDGETS A4.2 DS3 REFERENCE MODEL AND JITTER AND WANDER BUDGETS A4.3 MPEG-2 VIDEO REFERENCE MODEL AND APPROPRIATE BUDGETS APPENDIX 5. DESCRIPTION OF SIMULATION MODELS FOR ATM NETWORK DELAY PERFORMANCE

7 1. SCOPE The scope of this technical report is to assess the effects of differences in distinct timing sources on services supported by existing ATM Synchronous Residual Time Stamp (SRTS) methodology, and to explore potential enhancements to AAL Type ABBREVIATIONS AND ACRONYMS [Editor s Note: This is an initial list. It is intended that, prior to completion of this TR, acronyms will be added as needed and deleted if they do not appear in the TR.] AAL ATM Adaptation Layer ADEV Allan Deviation ATM Asynchronous Transfer Mode AVAR Allan Variance CBR CDV CER CES CLR CMR Constant Bit Rate Cell Delay Variation Cell Error Ratio Circuit Emulation Service Cell Loss Ratio Cell Misinsertion Rate CPCS Common Part Convergence Sublayer CPS CTD CS FFM FPM Common Part Sublayer Cell Transfer Delay Convergence Sublayer Flicker Frequency Modulation Flicker Phase Modulation MDEV Modified Allan Deviation MVAR Modified Allan Variance MP MTIE PSD PCI PDU PRE QoS Measurement Point Maximum Time Interval Error Power Spectral Density Protocol Control Information Protocol Data Unit PDU Reference Event Quality of Service RWFM Random Walk Frequency Modulation 517

8 SAP SAR SDU SECBR SRE Service Access Point Segmentation and Reassembly Sublayer Service Data Unit Severely Errored Cell Block Ratio SDU Reference Event SSCS Service Specific Convergence Sublayer TDEV Time Deviation TVAR Time Variance VBR VC VP WFM WPM Variable Bit Rate Virtual Channel Virtual Path White Frequency Modulation White Phase Modulation 3. DEFINITIONS [Editor s Note: During the discussion at the July, 1998 T1X1.3 meeting, it was indicated that figures should be added to illustrate Definitions below.] 3.1 Synchronous Circuit Timing: A mode of Circuit Emulation Service (CES) timing where the source timing for the transported service (CES) is not preserved; rather, the recovered CES timing is taken from the network. This mode requires a common clock frequency between the ingress and egress points. If the rate of the segmentation of the CES at the source AAL entity is appreciably different from the rate clocking for data removed from the buffer, slips will occur at the AAL receiver buffer. Note that this use of synchronous differs from the use in the term synchronous clock recovery methods below. 3.2 Synchronous Clock Recovery Method: A type of clock recovery method that requires synchronized network clocks. More precisely, the timing signals at the AAL transmitter and the AAL receiver must both be traceable to a primary reference source. However, it is, in general, not required that the timing signals be traceable to the same primary reference source. As an example, SRTS is a synchronous clock recovery method that provides asynchronous circuit timing. 3.3 Asynchronous Circuit Timing: A mode of Circuit Emulation Service timing where the source timing for the transported service (CES) is preserved. The source of timing for the Asynchronous Circuit Timing is the service rate at the ingress AAL. Typical service clock recovery algorithms for this mode are the Synchronous Residual Time stamp (SRTS) algorithm and the adaptive clock algorithm. Note that this use of asynchronous differs from the use in the term asynchronous clock recovery methods below. 3.4 Asynchronous Clock Recovery Method: A type of clock recovery method that is independent of the network clocks. More precisely, this type of clock recovery method does not 617

9 depend on PRS-traceable network timing signals at the AAL transmitter and receiver. As an example, the adaptive clock method is an asynchronous clock recovery method that provides asynchronous circuit timing. 4. INTRODUCTION 5. TYPES OF CIRCUIT EMULATION SERVICES There are currently two types ofstructures defined to carry Circuit Emulationed Services (CES). across an ATM network. They are Structured and Unstructured and Structured services, respectively. Each type of CES uses a specific type of circuit timing. This section first describes the two types of circuit timing, and then describes the Structured and Unstructured CES. 5.1 Types of Circuit Timing Synchronous Circuit Timing As indicated in Definition Section 3.1, synchronous circuit timing is a mode where the source timing for the transported CES is not preserved; rather, the recovered CES timing is taken from the network. In this mode, the timing is passed from the AAL to the end equipment by means of the CES interface. Therefore the source of the timing is the clock provided to the AAL entity at the egress. If the end office equipment uses timing from the CES interface, then it would be also operating synchronous with the network clock (i.e., clock providing timing to the ATM NE). This mode does require a common clock frequency between the egress and ingress points. If the rate of the segmentation of the CES at the source AAL entity is appreciably different from the rate clocking for data removed from the buffer - slips will occur at the ATM receiver buffer Asynchronous Circuit Timing As indicated in Definition Section 3.2, asynchronous circuit timing is a mode where the source timing for the transported CES is preserved. The source of timing for the Asynchronous Circuit Timing is the service rate at the ingress AAL. Typical service clock recovery algorithms for this mode are the SRTS algorithm and the adaptive clock algorithm. The SRTS mechanism does require a common, synchronous clock frequency between the egress and ingress points to recreate the original service clock frequency. However, there may be situations where the two edges of the network will operate plesiochronously (see Section 7.1). If the rate of the segmentation of the CES at the source AAL entity is appreciably different from the rate clocking for data removed from the buffer - slips will occur at the ATM receiver buffer. This may result in uncontrolled slips, which will cause down stream equipment to lose framing (see section 7.3.1). Synchronous Residual Time Stamp SRTS - A detailed explanation of the SRTS mechanism can be found in Appendix 2 Adaptive clock - T1X1.3 is currently investigating the use of adaptive clocking during backup scenarios; that is during the loss of PRS traceability to the AAL 5.2 Structured Circuit Emulation Services 717

10 A sstructured CES is typically are defined to be a fractional DS1, which provides a switched Nx64 kbs. This is used in applications where one to twenty-four N DS0 time slots will be sent across the ATM network. In this application, synchronization is provided by the network to the end user equipment (e.g., Private Branch Exchange). In other words, synchronous circuit timing is assumed to be the prevalent operating mode for structured CES. Alternatively, unstructured CES will be either a transparent DS1 or DS3 service. Therefore, the network will not provide timing for the service. Service clock timing is derived from the source and is recreated at the AAL1 by a timing recovery mechanism (i.e., SRTS or Adaptive Clock). Structured Data Transfer - The transfer of AAL user information is supported by the CBR AAL and is organized into data blocks with a fixed length corresponding to an integral number of octets. The process can be used with CBR services that have a fixed length, octet based block structure (e.g., Nx64 kbps services). Due to the synchronous need for such services, it is expected that the prevalent operating condition for the structured data transfer will be synchronous circuit timing (see Section 2.1.1). 5.3 Unstructured Circuit Emulation Services Unstructured CES is either a transparent DS1 or DS3 service. Asynchronous circuit timing is used, i.e., the network does not provide timing for the service. Service clock timing is derived from the source and is recreated at the AAL1 by a timing recovery mechanism (i.e., SRTS or Adaptive Clock). Unstructured Data Transfer - The transfer of AAL user information is not organized into data blocks. Unstructured CES will be either a transparent DS1 or DS3 service. Therefore, it is assumed that asynchronous circuit timing will typically be used for unstructured data transfer (see Section 2.1.2). 5.1 Synchronous Circuit Timing [Editor s Note: The term synchronous is used here to indicate that the source timing for the transported service (CES) is not preserved; rather, the recovered CES timing is taken from the network (this is described in the following paragraph). This use of synchronous differs from the use in the term synchronous clock recovery methods elsewhere in the TR. There, synchronous refers to the fact that the clock recovery methods require synchronized network clocks. Note that, with these uses of synchronous, SRTS would be a synchronous clock recovery method that provides asynchronous circuit timing. At the January, 1998 T1X1.3 meeting, it was decided to use the terms synchronous and asynchronous to refer to the clock recovery method (the latter use above) rather than the circuit timing (former use above, or the use in the current section). Appropriate terminology that will not cause confusion is needed for the circuit timing use of this section. See also the Editor s Note for Section 5.2.] In this mode, the timing is passed from the AAL to the end equipment by means of the CES interface. Therefore the source of the timing is the clock provided to the AAL entity at the egress. If the end office equipment uses timing from the CES interface, then it would be also operating synchronous with the network clock (i.e., clock providing timing to the ATM NE). Synchronous circuit timing is assumed to be the prevalent operating mode for structured CES. This mode does require a common clock frequency between the egress and ingress points. If 817

11 the rate of the segmentation of the CES at the source AAL entity is appreciably different from the rate clocking for data removed from the buffer - slips will occur at the ATM receiver buffer. 5.2 Asynchronous Circuit Timing [Editor s Note: The term asynchronous is used here to indicate that the source timing for the transported service (CES) is preserved. This use of asynchronous differs from the use in the term asynchronous clock recovery methods elsewhere in the TR. There, asynchronous refers to the fact that the clock recovery methods are independent of the network clocks. Note that, with these uses of synchronous and asynchronous, SRTS would be a synchronous clock recovery method that provides asynchronous circuit timing; adaptive clock recovery methods would be asynchronous clock recovery methods that provide asynchronous circuit timing. At the January, 1998 T1X1.3 meeting, it was decided to use the terms synchronous and asynchronous to refer to the clock recovery method (the latter use above) rather than the circuit timing (former use above, or the use in the current section). Appropriate terminology that will not cause confusion is needed for the circuit timing use of this section. See also the Editor s Note for Section 5.1.] The source of timing for the Asynchronous Circuit Timing is service rate at the ingress AAL. The typically used service clock recovery algorithms for this mode are the Synchronous Residual Time Stamp SRTS (See attached Annex A) and adaptive clock. The SRTS mechanism does require a common, synchronous clock frequency between the egress and ingress points to recreate the original service clock frequency. However, there may be situations where the two edges of the network will operate plesiochronously (see Section 6.1). If the rate of the segmentation of the CES at the source AAL entity is appreciably different from the rate clocking for data removed from the buffer - slips will occur at the ATM receiver buffer. This may result in uncontrolled slips, which will cause down stream equipment to lose framing (see section 6.2.1). Synchronous Residual Time Stamp SRTS - A detailed explanation of the SRTS mechanism can be found in Appendix 2 Adaptive clock - T1X1.3 is currently investigating the use of adaptive clocking during backup scenarios; that is during the loss of PRS traceability to the AAL 6. CLOCK RECOVERY FOR CONSTANT BIT RATE SERVICES TRANSPORTED OVER ATM NETWORKS [Editor s Note: The following material (up to Section 6.1) is from T1X1.3/ ] When transporting PDH signals such as DS1s and DS3s over ATM networks using the AAL-1 protocol, a clock recovery method is needed to recreate the nominal frequency of the original signal at the egress ATM switch. Clock recovery methods fall into two categories -- synchronous methods and asynchronous methods. Note that the use of the terms synchronous and asynchronous here differs from the use in synchronous and asynchronous circuit timing (see Sections and 5.1.2). 6.1 Synchronous Clock Recovery Methods 917

12 Synchronous clock recovery methods, such as SRTS, use ATM network timing information at the AAL-1 transmitter and receiver. Their jitter, wander, and slip performance depends on the quality of the ATM network timing/synchronization. They are, in general, independent of cell delay variability and loss SRTS (Requires AAL Type 1) [Editor s Note: Related material will be in Appendix 2.] [Editor s Note: The following material is from T1X1.3/ ] The Synchronous Residual Time Stamp (SRTS) is such a method can be that is used with AAL Type 1 when a common network clock is available at the edge nodes of the ATM network (i.e., at the AAL Type 1 mapper and demapper). The role of the synchronization network in the SRTS method is shown in Figures and Note that SRTS cannot be used with AALs other than AAL Type 1. [Editor s Note: There is some redundancy between Figures and It would be desirable to combine the two into a single figure. For Figure 6.1.2, there was some discussion at the April, 1998 T1X1.3 meeting on splitting the figure; some participants felt it should be split. In addition, some participants felt that Figure should not indicate that the synchronization network times the ATM network. ] Networ k Clock Synchronizatio n Network Network Clock DS1 ATM ingress switch ATM Switch ATM egress switch DS1 ATM Network Figure The role of the synchronization network in the SRTS method. (Only one direction of the DS1 signal is shown.) [Editor s Note: The following material (up to Section 6.2) is from T1X1.3/ ] The SRTS method is described in detail in Annex 2. The SRTS algorithm essentially measures the frequency difference between the ingress service clock and the network clock and encodes the frequency difference. This frequency difference is transferred from the source ATM Adaptation Layer (AAL-1) byin the Convergence Sublayer Indication (CSI) bit in every odd 1017

13 sequence number cell to the destination AAL-1ATM Adaptation Layer. At the destinationegress AAL-1, the service clock frequency is adjusted to the source clock frequency (at the ingress AAL) by adding the frequency offset to the local network clock. In recreating To recreate the source clock frequency in this manner, SRTS assumes that the network clock timing the source and destination AALs each of the ATM adaptation layers is common. Figure provides a visual description of the SRTS timing recovery process. In this figure, the service clock and network clock frequencies are indicated as Fs and Fn. For typical implementations, the source of the network clock will either be derived from the physical media or from a dedicated timing source, such as a Building Integrated Timing Supply (BITS). In either case, the network clock s synchronization performance must be bounded or impairments can occur as described in this Technical Report. [Editor s Note: The following figure is from T1X1.3/ There was some discussion at the April, 1998 T1X1.3 meeting on splitting the figure; some participants felt it should be split. In addition, some participants felt that the figure should not indicate that the synchronization network times the ATM network. Finally, there were comments that there is some redundancy between this figure and Figure above.] 1117

14 AAL - Mapper Sync Network AAL - Demapper CBR Service f s f n s Time Stamp Generation ATM Network s f n f s Service CBR Time Stamp Recovery Traffic Sync Figure Functional Description of SRTS Timing Recovery 1217

15 6.2 Asynchronous Clock Recovery Methods Asynchronous clock recovery methods, such as adaptive clock, are independent of ATM network timing/synchronization. They typically recover the service clock using cell arrival time and/or AAL-1 receiver buffer fill information. They are sensitive to cell delay variability and loss Adaptive Clock Recovery Methods [Editor s Note: The following material (up to Section 6.2.2) is from T1X1.3/ ] In contrast to SRTS, the adaptive method does not rely on the availability of a common network clock. In the adaptive method, the inter-arrival times of ATM cells at the egress ATM switch are averaged to construct the nominal frequency of the original signal Recentering Heuristics [Editor s Note: The discussion at the July, 1998 T1X1.3 meeting indicated that the editor should create text for this section based on his understanding of this topic from discussions at the joint T1X1.3/T1A1.3 meeting in January, 1997 and at the subsequent T1A1.3 meeting in January, It was noted that recentering heuristics were first suggested by one of the participants of T1A1.3, and that T1A1.3 should be asked for any comments on this material.] Recentering heuristics are intended to be used with synchronous clock recovery methods, and relate to the manner in which the AAL-1 receiver buffer is recentered after an uncontrolled slip has occurred. Recentering heuristics attempt to allow for the fact that one would like to recenter the buffer if the buffer overflow is due to a frequency offset between the AAL-1 transmitter and receiver clocks (e.g., due to one or both being traceable to a clock in holdover), but not if the overflow is due to random CDV. Note that adaptive clock recovery techniques attempt to filter the relatively fast CDV; it is likely that recentering heuristics, which must distinguish relatively fast CDV from the slower buffer fill variations due to a frequency offset, could use similar approaches. In a more general sense, recentering heuristics can be considered as any techniques used with synchronous clock recovery methods that distinguish relatively slow buffer fill changes due to a frequency offset between the AAL-1 transmitter and receiver from fast buffer fill changes due to CDV, and adjust the recovered clock rate to account for the frequency offset. In other words, it is not necessary to wait for an uncontrolled slip to occur before employing recentering heuristics; they can be employed continuously with the intention of avoiding uncontrolled slips. 7. EFFECT OF DIFFERENCES IN TIMING AT AAL TRANSMITTER AND RECEIVER ON RECOVERED CBR SERVICE CLOCK 7.1 Timing Sources PRS-Traceable DS1 Wander 1317

16 The longer-term (> 1 s) phase variation of a DS1 transported over an SRTS connection is dominated by the phase noise of the AAL-1 transmitter and receiver clocks and not the dynamics of the SRTS mechanism. Phase noise from the network clocks can be characterized using the TDEV metric. Figure shows three reference TDEV curves that are convenient for analyzing the overall wander performance of SRTS. The curves are taken from T1.101, T , and GR-2830, and reflect worst-case levels of wander on network clock reference signals. The dashed lines are used to extrapolate the curves beyond their definitions. Simulation and supportive analysis have demonstrated that the peak-to-peak phase for one day for one ATM island is under 100 µs if the network clocks meet the T1.101 DS1 TDEV mask and under 10 µs if the network clocks meet the T SMC TDEV mask. [Editor s Note: References were provided here to contributions T1X1.3/94-078, T1X1.3/95-013, T1X1.3/96-041, and T1X1.3/ These contributions contain these relevant simulations and supporting material. There was some discussion in the January, 1998 T1X1.3 meeting that relevant portions of this material should be included in appropriate annexes in the TR.] By extrapolation, the peak-to-peak phase is under 1 µs if the network clocks meet the GR PRS TDEV mask. For DS1 signals traversing several ATM islands, the peak-to-peak phase grows as the square root of the number of islands in the connection. [Editor s Note: The contribution T1X1.3/ was referenced here. As above, relevant material from this contribution may be included in appropriate annexes in the TR.] These observations can be used to assess the quality of DS1 signals vis-a-vis typical wander requirements. As specified in T1.403, the allowable wander on a traffic-carrying DS1 signal, not used for timing distribution, is 18 µs over any 24-hour period. To meet this requirement, the results indicate that the network clock wander must be near or below the T SMC TDEV level. Figure Reference TDEV Masks DS1 Jitter DS1 jitter is dependent on the design of the SRTS receiver. Simulation and supportive analysis have demonstrated that for a properly designed receiver the peak-to-peak jitter over a single ATM island is less than 1 UI. [Editor s Note: References were provided here to contributions T1X1.3/96-012, T1X1.3/95-068, T1X1.3/97-084, and the Bellcore paper on SRTS from IEEE Trans. Comm., vol.43, No. 2/3/4, February/March/April, These documents contain these relevant simulations and supporting material. There was some 1417

17 discussion in the January, 1998 T1X1.3 meeting that relevant portions of this material should be included in appropriate annexes in the TR.] This meets the requirements for DS1 signals as specified in T1.403 (5 UI) and GR-9 (1 UI for a mux/demux pair) DS3 Wander [Editor s Note: It was noted during the discussion at the July, 1998 T1X1.3 meeting that work is needed on this section DS3 Jitter [Editor s Note: It was noted during the discussion at the July, 1998 T1X1.3 meeting that work is needed on this section. [Editor s Note: Contribution T1X1.3/98-005, whose content was to be included as specified in the January, 1998 T1X1.3 meeting, referenced contributions T1X1.3/ and T1X1.3/ Both of these contributions addressed aspects of DS3 jitter for transport over ATM. As with other references in T1X1.3/98-005, it may be appropriate that relevant portions of this material should be included in appropriate annexes in the TR.] DS3 Video 7.2 Impact of Network Clock Impairments on Service Clock Recovery There are instances in which network level impairments, such as phase transients, will occur at the edges of the network responsible for mapping and demapping the constant rate. Testing has shown that phase transients can be translated through the SRTS timing recovery algorithm to the CBR service. 7.3 One or Both Timing Sources in Holdover or Traceable to Clock(s) in Holdover [Editor s Note following the July, 1998 T1X1.3 meeting: This sections is restructured following discussion at the July, 1998 meeting. The material on uncontrolled slips from Nortel and AT&T, respectively, is placed in separate subsections at the same heading level, with a statement of the relevant assumptions (from the previous Editor s Notes). The material in the section SRTS Method - Plesiochronous mode of operation is moved to the main Section 7.3, and text is added indicating that, while the term plesiochronous is used in some of the literature to describe this situation, this use of the term is not the same as the use in T1.101 (and T1X1.3 must confirm whether this is or is not a correct interpretation).] [Editor s Note (general note on Sections 7.3.1, , and ): The material in Section is from T1X1.3/ (Nortel), the material in Section is from T1X1.3/ (Bellcore), and the material in Section is from T1X1.3/ (AT&T). Each section has some general discussion of the situation where the AAL-1 transmitter and receiver do not have a common reference clock or where one or both is traceable to a clock in holdover. There is some overlap among these general discussions. In addition, Sections and present the results of uncontrolled slip rate calculations based on different assumptions. Consequently, the results in the two sections are not identical; in particular, the numbers of Loss of Frame (LOF) events per 1517

18 day given in Figure (T1X1.3/98-005, Nortel) are somewhat higher than the rates corresponding to the times between uncontrolled slips given in Table 7.1 (T1X1.3/98-010, AT&T). The Nortel calculations assumed no buffer recentering after an uncontrolled slip; the buffer fill was simply assumed to move 376 bits (47 octets, or 1 AAL-1 Convergence Sublayer PDU (or 1 AAL-1 SAR SDU); see T1X1.3/ (T1A1.3/98-068) and T1A1.3/ for a more detailed discussion of this terminology). Thus, for a frequency offset of y, where y is expressed in ppm, and DS1 transport at the nominal rate of Mbps, the time, in s, for the buffer fill to change by 376 bits is 376/1.544y = 243.5/y. Then the number of LOF events per day is 86400y/243.5 =354.8y. For example, for a frequency offset of 0.37 ppm, the number of LOF events per day is (354.8)(0.37) = 131. Note that the results are independent of actual buffer size (the buffer must be large enough to hold 1 AAL-1 CS PDU; this is required by ITU-T Recommendation I.363.1, which states that one of the functions of the CS is to form a 47-octet block of SAR-PDU payload (i.e., SAR SDU)). The AT&T calculations use the formula given in Section , T = B/( f/f) (the notation is given in Section ). Thus, B is the amount of buffer recentering; essentially, the total buffer is of size 2B, and the buffer recenters after an uncontrolled slip. Table 7.1 gives results for B equal to both 3 ms and 1 ms; at the DS1 rate, these correspond to 1544 bits and 4632 bits, respectively (alternatively, 376 bits corresponds to µs). In general, a model for the uncontrolled slip rate must account for whether the buffer is recentered (in addition to the magnitude of the holdover). More generally, the model must account for buffer fill variations due to ATM cell delay variation (CDV) (neither the AT&T nor Nortel calculations account for CDV). The presence of CDV will, in general, increase the uncontrolled slip rate compared to the rate due only to frequency offset (if all other assumptions are the same). This is because the CDV gives rise to a random component of buffer fill variation that is added to the deterministic component due to frequency offset. Finally, the model must account for whether or not recentering heuristics are employed and, if so, the nature and magnitude of these heuristics. Recentering heuristics attempt to allow for the fact that one would like to recenter the buffer if the buffer overflow is due to a frequency offset between the AAL-1 transmitter and receiver clocks (e.g., due to one or both being traceable to a clock in holdover), but not if the overflow is due to random CDV. Note that adaptive clock recovery techniques attempt to filter the relatively fast CDV; it is likely that recentering heuristics, which must distinguish relatively fast CDV from the slower buffer fill variations due to a frequency offset, could use similar approaches. Recentering heuristics were discussed very briefly at the January, 1997 joint T1X1.3/T1A1.3 meeting. Section contains a placeholder for recentering heuristics.] DS1 and DS3 Misframes [Editor s Note: The following material (up to the next Editor s Note) is from T1X1.3/ Note that there is some overlap with the material in Sections and ] During normal operation, the transport of a CBR signal using SRTS depends on the timing signals at the AAL-1 transmitter and receiver being either PRS-traceable or traceable to a common network clock. When one or both timing signals ends of the SRTS connection are in 1617

19 holdover or traceable to clock(s) in holdover, equipment at the terminating ends of the CBR service a DS1 connection will experience uncontrolled frame slips. [Editor s Note: The contribution T1X1.3/ was referenced here. This contribution contains relevant supporting material. There was some discussion in the January, 1998 T1X1.3 meeting that relevant portions of this material should be included in appropriate annexes in the TR.] This occurs because any frequency offset between the transmitter and receiver is added to the recreated nominal frequency of the CBR signal egressing the ATM network. This results in a difference between the rate at which data enters the AAL-1 receiver buffer and the rate at which it is read from the AAL-1 receiver buffer, which leads Frequency differences between the transmitter and receiver lead to buffer over/under flows in the receiver. In turn, these cause uncontrolled frame slips in attached equipment because the buffer over/under flows are not aligned with CBR service DS1 frame boundaries. The rate of uncontrolled slips depends on the frequency offset, whether and how the buffer is recentered following an uncontrolled slip, and the statistics of the. The presence of CDV will, in general, increase the uncontrolled slip rate compared to the rate due only to frequency offset (if all other assumptions are the same). This is because the CDV gives rise to a random component of buffer fill variation that is added to the deterministic component due to frequency offset. Any model must account for whether or not recentering heuristics are employed and, if so, the nature and magnitude of these heuristics (see Section 6.2.2). The cause of frequency offsets between edge ATM switch clocks is failures in the synchronization network or failures of timing signals synchronizing the ATM switches. (In what follows, these failures are referred to as type 1 and type 2 failures, respectively). During a type 1 failure, the network clock would operate in the holdover mode and the ATM switch clock would follow the network clock in holdover. During a type 2 failure, the ATM switch clock would operate in the holdover mode or free-run mode. These two types of failures are shown in Figures 7.3.1(a) and 7.3.1(b) below. Depending on the architecture of the synchronization network, one or the other type of failures would be more likely. In a highly reliable synchronization network, where a network clock is collocated with each ATM switch and there are independent redundant timing signals synchronizing the ATM switch, both these types of failures are extremely rare. 1717

20 Network Clock Synchronization Network Network Clock Network Clock Synchronization Network Network Clock DS1 ATM ingres s ATM egress DS1 ATM ingres s ATM egress Figure 7.3.1(a). Failure in synchronization network Figure 7.3.1(b). Failure of timing signal During a clock failure, the frequency offset added onto the DS1 signal depends on the holdover performance of the network clock (type 1 failure) or the holdover or free-run performance of the ATM switch clock (type 2 failure). In the past, the internal clocks of ATM switches were stratum 3 or stratum 4. Recently, some ATM switch vendors have installed or have plans to install stratum 3E internal clocks in their high-end switches. The following two subsections present DS1 uncontrolled slip rate results assuming (1) no buffer recentering, and (2) immediate buffer recentering, respectively, following an uncontrolled slip. In both cases, it is assumed there is no CDV DS1 Uncontrolled Slip Rate Assuming No Buffer Recentering Following the Slip In this case, it is assumed there is no buffer recentering after an uncontrolled slip. Following the slip the buffer fill is assumed to move 376 bits (47 octets, or 1 AAL-1 Convergence Sublayer PDU (or 1 AAL-1 SAR SDU); see T1X1.3/ (T1A1.3/98-068) and T1A1.3/ for a more detailed discussion of this terminology). In addition, as indicated above, it is assumed there is no CDV. Thus, for a frequency offset of y, where y is expressed in ppm, and DS1 transport at the nominal rate of Mbps, the time, in s, for the buffer fill to change by 376 bits is 376/1.544y = 243.5/y. Then the number of LOF events per day is 86400y/243.5 =354.8y. For example, for a frequency offset of 0.37 ppm, the number of LOF events per day is (354.8)(0.37) = 131. Note that the results are independent of actual buffer size (the buffer must be large enough to hold 1 AAL-1 CS PDU; this is required by ITU-T Recommendation I.363.1, which states that one of the functions of the CS is to form a 47-octet block of SAR-PDU payload (i.e., SAR SDU)). Figure shows the expected number of loss of frame (LOF) events per day as a function of frequency offset, using the above result. The graph indicates that an unacceptable state of operation may result, and a backup mechanism be needed to mitigate the effects of holdover or free-running clocks. 1817

21 Figure Loss of Frame Events Caused by Holdover [Editor s Note: The following material (up to the next Editor s Note) is from T1X1.3/ This appears to be the appropriate subsection; note that there is some overlap with the material above and with Section ] SRTS Method - Plesiochronous mode of operation [Editor s Note: It is not clear whether this section refers only to the case where the AAL- 1 transmitter and/or receiver clocks are in holdover, or also includes the case where they are both PRS-traceable but traceable to different PRSs. The latter case should actually be covered in Section 7.1; it should be clearly indicated there that that section (and all its subsections) apply to the case where the AAL-1 transmitter and receiver are traceable to different PRSs. In addition, depending on what case this section refers to, some text may be needed explaining that this use of the term plesiochronous differs from the definition in T1.101 (see definition 4.17 of T1X1.3/98-002R1). Depending on the resolution, the text of this section should be moved and merged in Section 7.1 or the main part of Section 7.3.] The SRTS method may not always have a common network reference clock available at both the transmitting and receiving AAL entities. The issue of the accommodation of plesiochronous operation needs to be addressed. This scenario must be accommodated in such a way that the received clock satisfies the jitter requirements for the MHz hierarchy in CCITT Recommendation G.824 and ANSI T1.102, T1.403, and T The control of wander (i.e., jitter below 10 Hz) in the piesiochronous mode of operation requires further study. The detailed method of dealing with the plesiochronous mode of operation is not standardized. [Editor s Note: The following material (up to Section 7.3.2) is from T1X1.3/ Note that there is some overlap with the material above, in Sections and ] DS1 Uncontrolled Slip Rate Assuming Immediate Buffer Recentering Following the Slip SRTS and Clock Failures Let the size of the slip buffer be 2B, expressed in units of time, and assume that the buffer is immediately recentered when an uncontrolled slip occurs. Then, if the frequency offset between the AAL-1 transmitter and receiver is y (expressed as a fraction), the time T to the next uncontrolled slip is given by 1917

22 T= B/y The time T is the time between uncontrolled slips, and 1/T is the uncontrolled slip rate. This result assumes there is no CDV. The AT&T calculations use the formula given in Section , T = B/( f/f) (the notation is given in Section ). Thus, B is the amount of buffer recentering; essentially, the total buffer is of size 2B, and the buffer recenters after an uncontrolled slip. Table 7.1 gives results for B equal to both 3 ms and 1 ms; at the DS1 rate, these correspond to 1544 bits and 4632 bits, respectively (alternatively, 376 bits corresponds to µs). In the following, only DS1 signals are discussed. With modifications of numerical examples, the discussion applies to any PDH signal carried over an ATM network using SRTS. During normal operation, the SRTS scheme transports a DS1 signal asynchronous to the network clock, i.e. the original frequency of the DS1 signal (the DS1 service clock) entering the ATM network is recreated at the egress edge of the ATM network. [Editor s Note: This use of the term asynchronous is that of Section 5, which discussion synchronous and asynchronous circuit timing, and not that of Section 6, which talks of synchronous and asynchronous clock recovery methods.] However, the asynchronous transport of customer signals using SRTS depends on the edge ATM switches being synchronized to a common network clock. When there is a frequency offset between the edge ATM switch clocks, this frequency offset will be added onto the recreated nominal frequency of the DS1 egressing the ATM network. Such a frequency offset will cause slips in the AAL1 buffer of the egress ATM switch. Slips in the AAL1 buffer lead to uncontrolled slips in the DS1 terminating equipment. The time between slips in the AAL1 buffer is given by the following formula: T = B/( f/f), where T is the time between slips, B is the effective AAL1 buffer size in units of time and f/f is the fractional frequency offset between the edge ATM switch clocks. The effective buffer size is determined by the starting position of the fill level in the buffer following buffer slips. Both centered and off-center starting positions have been implemented. In some implementations, this position is user-adjustable. Typically, the effective AAL1 buffer size is several milliseconds at the DS1 rate. The cause of frequency offsets between edge ATM switch clocks is failures in the synchronization network or failures of timing signals synchronizing the ATM switches. (In what follows, these failures are referred to as type 1 and type 2 failures, respectively). During a type 1 failure, the network clock would operate in the holdover mode and the ATM switch clock would follow the network clock in holdover. During a type 2 failure, the ATM switch clock would operate in the holdover mode or free-run mode. These two types of failures are shown in Figures 7.3.2(a) and 7.3.2(b) below. Depending on the architecture of the synchronization network, one or the other type of failures would be more likely. In a highly reliable synchronization network, where a network clock is collocated with each ATM switch and there are independent redundant timing signals synchronizing the ATM switch, both these types of failures are extremely rare. 2017

23 Network Clock Synchronization Network Network Clock Network Clock Synchronization Network Network Clock DS1 ATM ingres s ATM egress DS1 ATM ingres s ATM egress Figure 7.3.2(a). Failure in synchronization network Figure 7.3.2(b). Failure of timing signal During a clock failure, the frequency offset added onto the DS1 signal depends on the holdover performance of the network clock (type 1 failure) or the holdover or free-run performance of the ATM switch clock (type 2 failure). In the past, the internal clocks of ATM switches were stratum 3 or stratum 4. Recently, some ATM switch vendors have installed or have plans to install stratum 3E internal clocks in their high-end switches. Table 7.1 shows the time between slips in a three milliseconds and one millisecond AAL1 buffer corresponding to frequency offsets due to a clock in holdover. The maximum frequency offset allowed for clock strata at the end of 24 hours of holdover operation is used to calculate the time between slips. Synchronization Fractional Frequency Offset Time between slips (B = 3 milliseconds) Time between slips (B = 1 millisecond) 1x days 115 days 1x days 27 hours 3.7x hours 45 minutes Table 7.1. Example of time between slips in an AAL1 buffer due to synchronization fractional frequency offsets (i.e., clocks in holdover or free-run) when using SRTS Use of Adaptive Clock Recovery Techniques Use of Controlled Slip Mechanism in AAL Type 1 [Editor s Note: This is a possible mechanism that could be used. However, AAL Type 1 currently does not have a facility for controlled slips at the payload level. Such a facility would have to be added to AAL-1 for this to be used. In addition, it was noted at the July, 1998 T1X1.3 meeting that this could be done at the DS1 superframe level.] 2117

24 7.3.4 Use of AAL Type 1 Receiver Buffer Recentering Heuristics DS1 and DS3 Jitter DS1 and DS3 Wander DS3 Video MPEG-2 Video [Editor s Note: This topic is included here and not in Section 7.1 (i.e., unlike the previous three subsections, there is no corresponding subsection under Section 7.1) because MPEG-2 video is to be carried using AAL Type 5. Therefore, there is no possibility of using SRTS for timing recovery; only asynchronous (e.g., adaptive) timing recovery methods are possible.] Mapping of MPEG-2 in AAL-1 The quality of a video service can be influenced drastically by various ATM layer impairments, One way to minimize these effects is to use a combination of AAL Type 1 and an error correcting scheme. By using the time stamp carried in the CSI field of the AAL-1 SAR PDU it is possible to emulate a constant end-to-end delay scenario. ITU-T Recommendation J.82 [18] includes a method of using AAL-1 for this encapsulation as well as an AAL-5 implementation. It is necessary to consider both the AAL type and the QoS specified on a given ATM facility in order to determine its applicability to MPEG-2 transport. 8. CHARACTERIZATION OF ATM CELL DELAY VARIABILITY AND EFFECT ON CBR CLOCK RECOVERY 8.1 Peak-to-Peak CDV (1-point and 2-point) 8.2 TDEV 8.3 MTIE 8.4 Dependence on ATM Network Traffic Mix, Traffic Volume, and Traffic Models [Editor s Note: Related material will be in Appendix 5.] 9. REFERENCES [Editor s Note: The following references are from T1X1.3/98-005, and are preserved here. There was discussion at the January, 1998 T1X1.3 meeting that appropriate material 2217

25 contained in the T1X1.3 contributions below, which is referenced in various sections of the TR, should be preserved in appropriate Annexes.] [1] GTE, TDEVs of Recovered Timing by SRTS Synchronization Scheme with Non-ideal Source and Network Clocks: Some Preliminary Results, Contribution to T1 Standards Project, T1X1.3/94-078, July 1994 [2] GTE, Simulation Results on the Recovered Timing by SRTS with Non-ideal Source and Reference Clocks, Contribution to T1 Standards Project, T1X1.3/95-013, January 1995 [3] Lucent, DS1 and DS3 Jitter Accumulation in a Network of ATM Islands with SRTS Timing Recovery -- Initial Results, Contribution to T1 Standards Project, T1X1.3/96-012, January 1996 [4] Lucent, Total Phase Accumulation in a Network of ATM Islands with SRTS Timing Recovery -- Initial Results, Contribution to T1 Standards Project, T1X1.3/96-041, April 1996 [5] Lucent, Application of Time and Frequency Stability Parameters to the Characterization of ATM Cell Delay Variation and Traffic, Contribution to T1 Standards Project, T1X1.3/96-068, October 1996 [6] AT&T, Simulation of Jitter of a DS3 over ATM with Adaptive Clock Frequency Recovery, Contribution to T1 Standards Project, T1X1.3/95-079, July 1995 [7] AT&T, Waiting-Time Jitter for the ATM AAL1 Operation, Contribution to T1 Standards Project, T1X1.3/96-075, July 1996 [8] Tektronix, Jitter Due to ATM AAL1 SRTS Algorithm, Contribution to T1 Standards Project, T1X1.3/97-084, October 1997 [9] Bellcore, Synchronous Techniques for Timing Recovery in BISDN, IEEE Trans on Comm, vol 43, No 2/3/4, February/March/April 1995 [10] Bellcore, Observations of DS1 Circuit Emulation in Presence of Frequency Offsets, Contribution to T1 Standards Project, T1X1.3/96-024, April 1996 [Editor s Note: The following references are from T1X1.3/98-014, and are preserved here.] [11] ANSI T1X , Initial Draft Material and Template for T1 Technical Report on the effect of ATM Network Timing on CBR Service Clock Recovery and Synchronization Performance (October, 1996) [12] ITU-T I. 363 B-ISDN ATM Layer Adaptation Layer (AAL) Specification, (March, 1993) [13] ANSI T Adaptation Layer for Constant Bit Rate Services Functionality and Specification, (1993) [14] GR CORE ATM and ATM Protocols, Issue 1 (Bellcore, July 1994) [15] GR CORE Broadband Switching Systems Generic Requirements, Issue 1 (Bellcore, August 1994) [16] GR ATM Service Access Multiplexer (SAM) Generic Requirements, Issue 2 (November, 1996) [17] ANSI T1X , Observations of DS1 Circuit Emulation in the Presence of Frequency [18] ITU-T J.82, Transport of MPEG-2 Constant Bit Rate Television Signals in B-ISDN (07/96) 2317