The Heptane Static Worst-Case Execution Time Estimation Tool
|
|
|
- Job Franklin
- 5 years ago
- Views:
Transcription
1 The Heptane Static Worst-Case Execution Time Estimation Tool Damien Hardy Benjamin Rouxel Isabelle Puaut Institut de Recherche en Informatique et Systèmes Aléatoires
2 Introduc>on Real->me system Timing guarantees Worst-Case Execu>on Time (WCET) Sta>c methods Measurement-based Probabilis>c 2
3 Heptane: a sta>c analysis tool Program structure analysis Flow informa>on Binary level Model of the architecture 3
4 About HEPTANE Developed at IRISA/University of Rennes Stable research prototype Licenced under GPL C++ code Supported architectures MIPS Par>ally: ARM v7, Patmos (under construc>on) The first version has been designed around 2000 Many updates since then! Available online hzps://team.inria.fr/pacap/so[ware/heptane/ 4 4
![Heptane toolchain Function: Multiply loop [maxiter=20] loop [maxiter=20].](/docs-images/91/106594303/images/5-2.jpg "c file Compiler (gcc/llvm) Binary CFG extraction loop [maxiter=20] @0x400310 (BB) @0x40025c (BB)")
5 Heptane toolchain Function: Multiply loop [maxiter=20] loop [maxiter=20].c file Compiler (gcc/llvm) Binary CFG extraction loop (BB) & loops bounds (BB) XML file HeptaneAnalysis Low-Level Analysis High-Level Analysis WCET Statistics HTML 5 5
6 How to use it Source code in C (alterna>vely binary) With annota>on for the loops bounds: ANNOT_MAXITER(cst) Include needed ANNOT_MAXITER for each loop Some restric>ons : No pointers No malloc No recursion Natural loops 6 6
7 How to use it: HeptaneExtract.c file & loops bounds Compiler (gcc/llvm) HeptaneExtract Binary CFG extraction.xml CFG configuration file (.xml) + optional files (binary, objdump ) 7 7
8 CFG.xml overview 1 cfg per func>on Instruc>on lis>ng filling basic-blocks Instruc>on addresses Edges between basic-blocks AZributes (e.g. loop bounds) 8 8
9 How to use it: HeptaneAnalysis.xml HeptaneAnalysis CFG Low Level Analysis High Level Analysis WCET Statistics HTML configuration file (.xml) 9 9
10 Low-level analysis Account for micro-architecture Timing informa>on per basic-block Enrich the CFG.xml Address Analysis Cache Analysis Pipeline Analysis 10
11 Data address analysis Conserva>vely determines addresses of referenced data Instruc>on addresses from the binary Stack analysis per func>on first instruc>on of func>ons calling context Basic block granularity for each access (load/store) evaluate registers content + memory (new) 11
12 Cache analysis Instruc>on & data set-associa>ve caches contextual analysis abstract interpreta>on (must, may, persistence) Mul>-level non inclusive cache hierarchies write-through, no-write allocate data caches LRU, PLRU, FIFO, MRU, Random Cache Hit Miss Classifica>on (CHMC) Always hit, Always miss, First miss, Not-classified 12
13 Pipeline analysis Compute the >ming of basic blocks simple in-order pipeline free of >ming anomalies fetch/memory stage depends on cache analysis 13
14 High-level analysis Determine cri>cal path Context sensi>ve (calling context) Implicit Path Enumera>on Technique (IPET) maximize # execu>ons execu>on >me constant computed low-level analysis by 14
15 Install GNU/Linux & MacOS Install, use and hack download sources from : hzps://team.inria.fr/pacap/so[ware/heptane/ modify install.sh to your configura>on dependencies: libxml2, ILP solver (lp-solve, cplex) Use create a config file (sample in config_files/ folder) launch HeptaneExtract launch HeptaneAnalysis collect results Hack architecture specifici>es in src/common/architecturedependent/ analysis in src/heptaneanalysis/src/specific/ 15
16 Research based on Heptane Cache analysis (cache hierarchies, mul>-cores) D. Hardy, I. Puaut. WCET analysis of instruc>on cache hierarchies. Journal of Systems Architecture, volume 57, issue 7, pages , August Branch predic>on (analysis, compiler-directed) A. Colin, I. Puaut. Worst Case Execu>on Time Analysis for a Processor with Branch Predic>on. Real-Time Systems, April Cache locking, par>>oning I. Puaut. Cache Analysis vs Sta>c Cache Locking for Schedulability Analysis in Mul>tasking Real-Time Systems. WCET Workshop, ECRTS Scratchpad management J-F. Deverge, I. Puaut. WCET-directed dynamic scratchpad memory alloca>on of data. ECRTS CRPD es>ma>on, Sta>c probabilis>c WCET, Traceability of flow informa>on,... hzps://team.inria.fr/pacap/members/isabelle-puaut/ 16 16
17 Conclusion Heptane WCET analysis tool open source es>mate WCET from binary advanced in sta>c cache analysis Side product : CFG management library Future work automa>c loop bound extrac>on further improve address analysis increase number of supported architecture Any help is welcome 17
18 Ques>ons? hzps://team.inria.fr/pacap/so[ware/heptane/ Specific ques>ons, skype: isabellepuaut 18
HEPTANE (Hades Embedded Processor Timing ANalyzEr) A Modular Tool for Sta>c WCET Analysis
HEPTANE (Hades Embedded Processor Timing ANalyzEr) A Modular Tool for Sta>c WCET Analysis Damien Hardy ALF research group, IRISA/INRIA Rennes TuTor 16, Vienna, April 2016 About HEPTANE Developed at IRISA/University
CS 465 Final Review. Fall 2017 Prof. Daniel Menasce
CS 465 Final Review Fall 2017 Prof. Daniel Menasce Ques@ons What are the types of hazards in a datapath and how each of them can be mi@gated? State and explain some of the methods used to deal with branch
Predictable paging in real-time systems: an ILP formulation
Predictable paging in real-time systems: an ILP formulation Damien Hardy Isabelle Puaut Université Européenne de Bretagne / IRISA, Rennes, France Abstract Conventionally, the use of virtual memory in real-time
Static WCET Analysis: Methods and Tools
Static WCET Analysis: Methods and Tools Timo Lilja April 28, 2011 Timo Lilja () Static WCET Analysis: Methods and Tools April 28, 2011 1 / 23 1 Methods 2 Tools 3 Summary 4 References Timo Lilja () Static
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection Daniel Grund 1 Jan Reineke 2 1 Saarland University, Saarbrücken, Germany 2 University of California, Berkeley, USA Euromicro
Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern
Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern Introduction WCET of program ILP Formulation Requirement SPM allocation for code SPM allocation for data Conclusion
FIFO Cache Analysis for WCET Estimation: A Quantitative Approach
FIFO Cache Analysis for WCET Estimation: A Quantitative Approach Abstract Although most previous work in cache analysis for WCET estimation assumes the LRU replacement policy, in practise more processors
History-based Schemes and Implicit Path Enumeration
History-based Schemes and Implicit Path Enumeration Claire Burguière and Christine Rochange Institut de Recherche en Informatique de Toulouse Université Paul Sabatier 6 Toulouse cedex 9, France {burguier,rochange}@irit.fr
Caching and Demand- Paged Virtual Memory
Caching and Demand- Paged Virtual Memory Defini8ons Cache Copy of data that is faster to access than the original Hit: if cache has copy Miss: if cache does not have copy Cache block Unit of cache storage
CSSE232 Computer Architecture I. Datapath
CSSE232 Computer Architecture I Datapath Class Status Reading Sec;ons 4.1-3 Project Project group milestone assigned Indicate who you want to work with Indicate who you don t want to work with Due next
Scope-based Method Cache Analysis
Scope-based Method Cache Analysis Benedikt Huber 1, Stefan Hepp 1, Martin Schoeberl 2 1 Vienna University of Technology 2 Technical University of Denmark 14th International Workshop on Worst-Case Execution
Main Points. Address Transla+on Concept. Flexible Address Transla+on. Efficient Address Transla+on
Address Transla+on Main Points Address Transla+on Concept How do we convert a virtual address to a physical address? Flexible Address Transla+on Segmenta+on Paging Mul+level transla+on Efficient Address
WCET-Aware C Compiler: WCC
12 WCET-Aware C Compiler: WCC Jian-Jia Chen (slides are based on Prof. Heiko Falk) TU Dortmund, Informatik 12 2015 年 05 月 05 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply.
Memory Hierarchy. 2/18/2016 CS 152 Sec6on 5 Colin Schmidt
Memory Hierarchy 2/18/2016 CS 152 Sec6on 5 Colin Schmidt Agenda Review Memory Hierarchy Lab 2 Ques6ons Return Quiz 1 Latencies Comparison Numbers L1 Cache 0.5 ns L2 Cache 7 ns 14x L1 cache Main Memory
Design and Analysis of Real-Time Systems Predictability and Predictable Microarchitectures
Design and Analysis of Real-Time Systems Predictability and Predictable Microarcectures Jan Reineke Advanced Lecture, Summer 2013 Notion of Predictability Oxford Dictionary: predictable = adjective, able
Static Analysis of Worst-Case Stack Cache Behavior
Static Analysis of Worst-Case Stack Cache Behavior Alexander Jordan 1 Florian Brandner 2 Martin Schoeberl 2 Institute of Computer Languages 1 Embedded Systems Engineering Section 2 Compiler and Languages
Asaf Cidon, Assaf Eisenman, Mohammad Alizadeh and Sachin KaH
Cli$anger: Scaling Performance Cliffs in Memory Caches [NSDI 2016] Cache OS: Data Center Dynamic Cache Management Asaf Cidon, Assaf Eisenman, Mohammad Alizadeh and Sachin KaH 1 Key-Value Caches are Essen1al
Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System
Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System Daniel Sandell Master s thesis D-level, 20 credits Dept. of Computer Science Mälardalen University Supervisor:
Static Analysis of Worst-Case Stack Cache Behavior
Static Analysis of Worst-Case Stack Cache Behavior Florian Brandner Unité d Informatique et d Ing. des Systèmes ENSTA-ParisTech Alexander Jordan Embedded Systems Engineering Sect. Technical University
Instructor: Randy H. Katz hap://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #7. Warehouse Scale Computer
CS 61C: Great Ideas in Computer Architecture Everything is a Number Instructor: Randy H. Katz hap://inst.eecs.berkeley.edu/~cs61c/fa13 9/19/13 Fall 2013 - - Lecture #7 1 New- School Machine Structures
Architectural Requirements Phase. See Sommerville Chapters 11, 12, 13, 14, 18.2
Architectural Requirements Phase See Sommerville Chapters 11, 12, 13, 14, 18.2 1 Architectural Requirements Phase So7ware requirements concerned construc>on of a logical model Architectural requirements
: Advanced Compiler Design. 8.0 Instruc?on scheduling
6-80: Advanced Compiler Design 8.0 Instruc?on scheduling Thomas R. Gross Computer Science Department ETH Zurich, Switzerland Overview 8. Instruc?on scheduling basics 8. Scheduling for ILP processors 8.
Timing Anomalies Reloaded
Gernot Gebhard AbsInt Angewandte Informatik GmbH 1 of 20 WCET 2010 Brussels Belgium Timing Anomalies Reloaded Gernot Gebhard AbsInt Angewandte Informatik GmbH Brussels, 6 th July, 2010 Gernot Gebhard AbsInt
UNIT V: CENTRAL PROCESSING UNIT
UNIT V: CENTRAL PROCESSING UNIT Agenda Basic Instruc1on Cycle & Sets Addressing Instruc1on Format Processor Organiza1on Register Organiza1on Pipeline Processors Instruc1on Pipelining Co-Processors RISC
Lecture 4: Build Systems, Tar, Character Strings
CIS 330:! / / / / (_) / / / / _/_/ / / / / / \/ / /_/ / `/ \/ / / / _/_// / / / / /_ / /_/ / / / / /> < / /_/ / / / / /_/ / / / /_/ / / / / / \ /_/ /_/_/_/ _ \,_/_/ /_/\,_/ \ /_/ \ //_/ /_/ Lecture 4:
CS 61C: Great Ideas in Computer Architecture (Machine Structures) More Cache: Set Associa0vity. Smart Phone. Today s Lecture. Core.
CS 6C: Great Ideas in Computer Architecture (Machine Structures) More Cache: Set Associavity Instructors: Randy H Katz David A PaGerson Guest Lecture: Krste Asanovic hgp://insteecsberkeleyedu/~cs6c/fa
Caches in Real-Time Systems. Instruction Cache vs. Data Cache
Caches in Real-Time Systems [Xavier Vera, Bjorn Lisper, Jingling Xue, Data Caches in Multitasking Hard Real- Time Systems, RTSS 2003.] Schedulability Analysis WCET Simple Platforms WCMP (memory performance)
Architecture of so-ware systems
Architecture of so-ware systems Lecture 13: Class/object ini
Modeling Hardware Timing 1 Caches and Pipelines
Modeling Hardware Timing 1 Caches and Pipelines Peter Puschner slides: P. Puschner, R. Kirner, B. Huber VU 2.0 182.101 SS 2016 Generic WCET Analysis Framework source code Extraction of Flow Facts Compilation
Lecture 1 Introduc-on
Lecture 1 Introduc-on What would you get out of this course? Structure of a Compiler Op9miza9on Example 15-745: Introduc9on 1 What Do Compilers Do? 1. Translate one language into another e.g., convert
Chapter 2 MRU Cache Analysis for WCET Estimation
Chapter 2 MRU Cache Analysis for WCET Estimation Most previous work on cache analysis for WCET estimation assumes a particular replacement policy LRU. In contrast, much less work has been done for non-lru
CS 61C: Great Ideas in Computer Architecture Func%ons and Numbers
CS 61C: Great Ideas in Computer Architecture Func%ons and Numbers 9/11/12 Instructor: Krste Asanovic, Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs61c/sp12 Fall 2012 - - Lecture #8 1 New- School Machine
A Distributed Data- Parallel Execu3on Framework in the Kepler Scien3fic Workflow System
A Distributed Data- Parallel Execu3on Framework in the Kepler Scien3fic Workflow System Ilkay Al(ntas and Daniel Crawl San Diego Supercomputer Center UC San Diego Jianwu Wang UMBC WorDS.sdsc.edu Computa3onal
Research opportuni/es with me
Research opportuni/es with me Independent study for credit - Build PL tools (parsers, editors) e.g., JDial - Build educa/on tools (e.g., Automata Tutor) - Automata theory problems e.g., AutomatArk - Research
EE382V: System-on-a-Chip (SoC) Design
EE382V: System-on-a-Chip (SoC) Design Lecture 5 Performance Analysis Sources: Prof. Jacob Abraham, UT Austin Prof. Lothar Thiele, ETH Zurich Prof. Reinhard Wilhelm, Saarland Univ. Andreas Gerstlauer Electrical
TerraSwarm. A Machine Learning and Op0miza0on Toolkit for the Swarm. Ilge Akkaya, Shuhei Emoto, Edward A. Lee. University of California, Berkeley
TerraSwarm A Machine Learning and Op0miza0on Toolkit for the Swarm Ilge Akkaya, Shuhei Emoto, Edward A. Lee University of California, Berkeley TerraSwarm Tools Telecon 17 November 2014 Sponsored by the
CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES
CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES PITFALLS AND SOLUTIONS 1 Claire Burguière, Jan Reineke, Sebastian Altmeyer 2 Abstract In preemptive real-time systems, scheduling analyses
CS 61C: Great Ideas in Computer Architecture Strings and Func.ons. Anything can be represented as a number, i.e., data or instruc\ons
CS 61C: Great Ideas in Computer Architecture Strings and Func.ons Instructor: Krste Asanovic, Randy H. Katz hdp://inst.eecs.berkeley.edu/~cs61c/sp12 Fall 2012 - - Lecture #7 1 New- School Machine Structures
History Table. Latest
Lecture 15 Prefetching Latest History Table A0 Correlating Prediction Table A0,A1 A3 11 Winter 2019 Prof. Ronald Dreslinski A1 Prefetch A3 h8p://www.eecs.umich.edu/courses/eecs470 Slides developed in part
Best Practice for Caching of Single-Path Code
Best Practice for Caching of Single-Path Code Martin Schoeberl, Bekim Cilku, Daniel Prokesch, and Peter Puschner Technical University of Denmark Vienna University of Technology 1 Context n Real-time systems
Performance Measurement
ECPE 170 Jeff Shafer University of the Pacific Performance Measurement 2 Lab Schedule Ac?vi?es Today Background discussion Lab 5 Performance Measurement Wednesday Lab 5 Performance Measurement Friday Lab
Data Flow Analysis. Suman Jana. Adopted From U Penn CIS 570: Modern Programming Language Implementa=on (Autumn 2006)
Data Flow Analysis Suman Jana Adopted From U Penn CIS 570: Modern Programming Language Implementa=on (Autumn 2006) Data flow analysis Derives informa=on about the dynamic behavior of a program by only
Profiling & Tuning Applica1ons. CUDA Course July István Reguly
Profiling & Tuning Applica1ons CUDA Course July 21-25 István Reguly Introduc1on Why is my applica1on running slow? Work it out on paper Instrument code Profile it NVIDIA Visual Profiler Works with CUDA,
Pa#ern Recogni-on for Neuroimaging Toolbox
Pa#ern Recogni-on for Neuroimaging Toolbox Pa#ern Recogni-on Methods: Basics João M. Monteiro Based on slides from Jessica Schrouff and Janaina Mourão-Miranda PRoNTo course UCL, London, UK 2017 Outline
Estimation of Cache Related Migration Delays for Multi-Core Processors with Shared Instruction Caches
Estimation of Cache Related Migration Delays for Multi-Core Processors with Shared Instruction Caches Damien Hardy, Isabelle Puaut To cite this version: Damien Hardy, Isabelle Puaut. Estimation of Cache
Predictable code and data paging for real time systems
Predictable code and data paging for real time systems Damien Hardy Isabelle Puaut Université Européenne de Bretagne / IRISA, Rennes, France Abstract There is a need for using virtual memory in real-time
CSE Opera+ng System Principles
CSE 30341 Opera+ng System Principles Lecture 2 Introduc5on Con5nued Recap Last Lecture What is an opera+ng system & kernel? What is an interrupt? CSE 30341 Opera+ng System Principles 2 1 OS - Kernel CSE
Hardware-Software Codesign. 9. Worst Case Execution Time Analysis
Hardware-Software Codesign 9. Worst Case Execution Time Analysis Lothar Thiele 9-1 System Design Specification System Synthesis Estimation SW-Compilation Intellectual Prop. Code Instruction Set HW-Synthesis
History of Java. Java was originally developed by Sun Microsystems star:ng in This language was ini:ally called Oak Renamed Java in 1995
Java Introduc)on History of Java Java was originally developed by Sun Microsystems star:ng in 1991 James Gosling Patrick Naughton Chris Warth Ed Frank Mike Sheridan This language was ini:ally called Oak
Program Op*miza*on and Analysis. Chenyang Lu CSE 467S
Program Op*miza*on and Analysis Chenyang Lu CSE 467S 1 Program Transforma*on op#mize Analyze HLL compile assembly assemble Physical Address Rela5ve Address assembly object load executable link Absolute
PhD in Computer And Control Engineering XXVII cycle. Torino February 27th, 2015.
PhD in Computer And Control Engineering XXVII cycle Torino February 27th, 2015. Parallel and reconfigurable systems are more and more used in a wide number of applica7ons and environments, ranging from
HW/SW Codesign. WCET Analysis
HW/SW Codesign WCET Analysis 29 November 2017 Andres Gomez gomeza@tik.ee.ethz.ch 1 Outline Today s exercise is one long question with several parts: Basic blocks of a program Static value analysis WCET
Memory Management. CS449 Fall 2017
Memory Management CS449 Fall 2017 Life9mes Life9me: 9me from which a par9cular memory loca9on is allocated un9l it is deallocated Three types of life9mes Automa9c (within a scope) Sta9c (dura9on of program)
hashfs Applying Hashing to Op2mize File Systems for Small File Reads
hashfs Applying Hashing to Op2mize File Systems for Small File Reads Paul Lensing, Dirk Meister, André Brinkmann Paderborn Center for Parallel Compu2ng University of Paderborn Mo2va2on and Problem Design
Efficient Memory and Bandwidth Management for Industrial Strength Kirchhoff Migra<on
Efficient Memory and Bandwidth Management for Industrial Strength Kirchhoff Migra
Improving Cache Performance by Exploi7ng Read- Write Disparity. Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, and Daniel A.
Improving Cache Performance by Exploi7ng Read- Write Disparity Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, and Daniel A. Jiménez Summary Read misses are more cri?cal than write misses
Stash Directory: A Scalable Directory for Many- Core Coherence! Socrates Demetriades and Sangyeun Cho
Stash Directory: A Scalable Directory for Many- Core Coherence! Socrates Demetriades and Sangyeun Cho 20 th Interna+onal Symposium On High Performance Computer Architecture (HPCA). Orlando, FL, February
Shared Cache Aware Task Mapping for WCRT Minimization
Shared Cache Aware Task Mapping for WCRT Minimization Huping Ding & Tulika Mitra School of Computing, National University of Singapore Yun Liang Center for Energy-efficient Computing and Applications,
Virtualization. Introduction. Why we interested? 11/28/15. Virtualiza5on provide an abstract environment to run applica5ons.
Virtualization Yifu Rong Introduction Virtualiza5on provide an abstract environment to run applica5ons. Virtualiza5on technologies have a long trail in the history of computer science. Why we interested?
Predictable paging in real-time systems: a compiler approach
Predictable paging in real-time systems: a compiler approach Isabelle Puaut Damien Hardy Université Européenne de Bretagne / IRISA, Rennes, France Abstract Conventionally, the use of virtual memory in
Hybrid SPM-Cache Architectures to Achieve High Time Predictability and Performance
Hybrid SPM-Cache Architectures to Achieve High Time Predictability and Performance Wei Zhang and Yiqiang Ding Department of Electrical and Computer Engineering Virginia Commonwealth University {wzhang4,ding4}@vcu.edu
Computer Systems Architecture
Computer Systems Architecture Lecture 12 Mahadevan Gomathisankaran March 4, 2010 03/04/2010 Lecture 12 CSCE 4610/5610 1 Discussion: Assignment 2 03/04/2010 Lecture 12 CSCE 4610/5610 2 Increasing Fetch
Chapter 3: Instruc0on Level Parallelism and Its Exploita0on
Chapter 3: Instruc0on Level Parallelism and Its Exploita0on - Abdullah Muzahid Hardware- Based Specula0on (Sec0on 3.6) In mul0ple issue processors, stalls due to branches would be frequent: You may need
Chronos: a Timing Analyzer for Embedded Software
Chronos: a Timing Analyzer for Embedded Software Xianfeng Li Department of Computer Science and Technology, Peking University, China Yun Liang Department of Computer Science, National University of Singapore,
Caches in Real-Time Systems. Instruction Cache vs. Data Cache
Caches in Real-Time Systems [Xavier Vera, Bjorn Lisper, Jingling Xue, Data Caches in Multitasking Hard Real- Time Systems, RTSS 2003.] Schedulability Analysis WCET Simple Platforms WCMP (memory performance)
A Fast and Precise Worst Case Interference Placement for Shared Cache Analysis
A Fast and Precise Worst Case Interference Placement for Shared Cache Analysis KARTIK NAGAR and Y N SRIKANT, Indian Institute of Science Real-time systems require a safe and precise estimate of the Worst
CS 61C: Great Ideas in Computer Architecture (Machine Structures)
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Instructors: Randy H. Katz David A. PaGerson hgp://inst.eecs.berkeley.edu/~cs61c/fa10 1 2 Cache Field Sizes Number of bits in a cache includes
Design and Analysis of Real-Time Systems Microarchitectural Analysis
Design and Analysis of Real-Time Systems Microarchitectural Analysis Jan Reineke Advanced Lecture, Summer 2013 Structure of WCET Analyzers Reconstructs a control-flow graph from the binary. Determines
Programming Environments
Programming Environments There are several ways of crea/ng a computer program Using an Integrated Development Environment (IDE) Using a text editor You should use the method you are most comfortable with.
Main Memory. CS 4410, Opera3ng Systems. Lorenzo Alvisi Anne Bracy. Spring 2017 Cornell University. See: Ch 8 & 9 in OSPP textbook
Main Memory Lorenzo Alvisi Anne Bracy CS 4410, Opera3ng Systems See: Ch 8 & 9 in OSPP textbook Spring 2017 Cornell University The slides are the product of many rounds of teaching CS 4410 by Professors
Memory Management Prof. James L. Frankel Harvard University
Memory Management Prof. James L. Frankel Harvard University Version of 5:42 PM 25-Feb-2017 Copyright 2017, 2015 James L. Frankel. All rights reserved. Memory Management Ideal memory Large Fast Non-volatile
Instructors: Randy H. Katz David A. PaGerson hgp://inst.eecs.berkeley.edu/~cs61c/fa10. 10/4/10 Fall Lecture #16. Agenda
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Instructors: Randy H. Katz David A. PaGerson hgp://inst.eecs.berkeley.edu/~cs61c/fa10 1 Agenda Cache Sizing/Hits and Misses Administrivia
LRU. Pseudo LRU A B C D E F G H A B C D E F G H H H C. Copyright 2012, Elsevier Inc. All rights reserved.
LRU A list to keep track of the order of access to every block in the set. The least recently used block is replaced (if needed). How many bits we need for that? 27 Pseudo LRU A B C D E F G H A B C D E
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 32: Pipeline Parallelism 3
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 32: Pipeline Parallelism 3 Instructor: Dan Garcia inst.eecs.berkeley.edu/~cs61c! Compu@ng in the News At a laboratory in São Paulo,
Sta$c Analysis Dataflow Analysis
Sta$c Analysis Dataflow Analysis Roadmap Overview. Four Analysis Examples. Analysis Framework Soot. Theore>cal Abstrac>on of Dataflow Analysis. Inter- procedure Analysis. Taint Analysis. Overview Sta>c
CS 61C: Great Ideas in Computer Architecture Direct- Mapped Caches. Increasing distance from processor, decreasing speed.
CS 6C: Great Ideas in Computer Architecture Direct- Mapped s 9/27/2 Instructors: Krste Asanovic, Randy H Katz hdp://insteecsberkeleyedu/~cs6c/fa2 Fall 2 - - Lecture #4 New- School Machine Structures (It
Computer Systems A Programmer s Perspective 1 (Beta Draft)
Computer Systems A Programmer s Perspective 1 (Beta Draft) Randal E. Bryant David R. O Hallaron August 1, 2001 1 Copyright c 2001, R. E. Bryant, D. R. O Hallaron. All rights reserved. 2 Contents Preface
Virtual Memory: Concepts
Virtual Memory: Concepts Instructor: Dr. Hyunyoung Lee Based on slides provided by Randy Bryant and Dave O Hallaron Today Address spaces VM as a tool for caching VM as a tool for memory management VM as
Handling Write Backs in Multi-Level Cache Analysis for WCET Estimation
Handling Write Backs in Multi-Level Cache Analysis for WCET Estimation Zhenkai Zhang Institute for Software Integrated Systems Vanderbilt University Nashville, TN, USA zhenkai.zhang@vanderbilt.edu Zhishan
Baggy bounds checking. Periklis Akri5dis, Manuel Costa, Miguel Castro, Steven Hand
Baggy bounds checking Periklis Akri5dis, Manuel Costa, Miguel Castro, Steven Hand C/C++ programs are vulnerable Lots of exis5ng code in C and C++ More being wrieen every day C/C++ programs are prone to
WP7: Patents Case Study
MOLTO WP7: Patents Case Study Meritxell Gonzàlez Bermúdez 2nd Year Review Barcelona, March 20th, 2012 Objectives To create a prototype of MT and NL retrieval of patents in the bio- medical & pharmaceu;cal
Computer Architecture: Mul1ple Issue. Berk Sunar and Thomas Eisenbarth ECE 505
Computer Architecture: Mul1ple Issue Berk Sunar and Thomas Eisenbarth ECE 505 Outline 5 stages of RISC Type of hazards Sta@c and Dynamic Branch Predic@on Pipelining with Excep@ons Pipelining with Floa@ng-
Worst-Case Execution Time (WCET)
Introduction to Cache Analysis for Real-Time Systems [C. Ferdinand and R. Wilhelm, Efficient and Precise Cache Behavior Prediction for Real-Time Systems, Real-Time Systems, 17, 131-181, (1999)] Schedulability
Com S 321 Problem Set 3
Com S 321 Problem Set 3 1. A computer has a main memory of size 8M words and a cache size of 64K words. (a) Give the address format for a direct mapped cache with a block size of 32 words. (b) Give the
Timing Analysis Enhancement for Synchronous Program
Timing Analysis Enhancement for Synchronous Program Extended Abstract Pascal Raymond, Claire Maiza, Catherine Parent-Vigouroux, Fabienne Carrier, and Mihail Asavoae Grenoble-Alpes University Verimag, Centre
ECSE 425 Lecture 25: Mul1- threading
ECSE 425 Lecture 25: Mul1- threading H&P Chapter 3 Last Time Theore1cal and prac1cal limits of ILP Instruc1on window Branch predic1on Register renaming 2 Today Mul1- threading Chapter 3.5 Summary of ILP:
ECE7995 Caching and Prefetching Techniques in Computer Systems. Lecture 8: Buffer Cache in Main Memory (I)
ECE7995 Caching and Prefetching Techniques in Computer Systems Lecture 8: Buffer Cache in Main Memory (I) 1 Review: The Memory Hierarchy Take advantage of the principle of locality to present the user
Objec0ves. Gain understanding of what IDA Pro is and what it can do. Expose students to the tool GUI
Intro to IDA Pro 31/15 Objec0ves Gain understanding of what IDA Pro is and what it can do Expose students to the tool GUI Discuss some of the important func
Timing Analysis. Dr. Florian Martin AbsInt
Timing Analysis Dr. Florian Martin AbsInt AIT OVERVIEW 2 3 The Timing Problem Probability Exact Worst Case Execution Time ait WCET Analyzer results: safe precise (close to exact WCET) computed automatically
Computer Systems: A Programmer s Perspec4ve. Have a tour of computer system at first... Chapter 1
Computer Systems: A Programmer s Perspec4ve Have a tour of computer system at first... Chapter 1 1 Computer System Runs the sojware and manages the hardware RISC vs CISC ADDRESS BUS DATA BUS SOFTWARE HARDWARE
Virtual Memory: Concepts
Virtual Memory: Concepts 5-23 / 8-23: Introduc=on to Computer Systems 6 th Lecture, Mar. 8, 24 Instructors: Anthony Rowe, Seth Goldstein, and Gregory Kesden Today VM Movaon and Address spaces ) VM as a
MAKING DYNAMIC MEMORY ALLOCATION STATIC TO SUPPORT WCET ANALYSES 1 Jörg Herter 2 and Jan Reineke 2
MAKING DYNAMIC MEMORY ALLOCATION STATIC TO SUPPORT WCET ANALYSES 1 Jörg Herter 2 and Jan Reineke 2 Abstract Current worst-case execution time (WCET) analyses do not support programs using dynamic memory
Verifica(on of Concurrent Programs
Verifica(on of Concurrent Programs Parker Aldric Mar With special thanks to: Azadeh Farzan and Zachary Kincaid Research Field: Program Verifica(on Goal is to program code that is safe, i.e. code that produces
ML4Bio Lecture #1: Introduc3on. February 24 th, 2016 Quaid Morris
ML4Bio Lecture #1: Introduc3on February 24 th, 216 Quaid Morris Course goals Prac3cal introduc3on to ML Having a basic grounding in the terminology and important concepts in ML; to permit self- study,
Locality. Cache. Direct Mapped Cache. Direct Mapped Cache
Locality A principle that makes having a memory hierarchy a good idea If an item is referenced, temporal locality: it will tend to be referenced again soon spatial locality: nearby items will tend to be
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches Damien Hardy Thomas Piquet Isabelle Puaut
CS101: Fundamentals of Computer Programming. Dr. Tejada www-bcf.usc.edu/~stejada Week 1 Basic Elements of C++
CS101: Fundamentals of Computer Programming Dr. Tejada stejada@usc.edu www-bcf.usc.edu/~stejada Week 1 Basic Elements of C++ 10 Stacks of Coins You have 10 stacks with 10 coins each that look and feel
Shared Data Cache Conflicts Reduction for WCET Computation in Multi-Core Architectures.
Shared Data Cache Conflicts Reduction for WCET Computation in Multi-Core Architectures. Benjamin Lesage Damien Hardy Isabelle Puaut University of Rennes 1, UEB, IRISA Rennes, France {Benjamin.Lesage, Damien.Hardy,
Using Graph- Based Characteriza4on for Predic4ve Modeling of Vectorizable Loop Nests
Using Graph- Based Characteriza4on for Predic4ve Modeling of Vectorizable Loop Nests William Killian PhD Prelimary Exam Presenta4on Department of Computer and Informa4on Science CommiIee John Cavazos and
Worst-Case Execution Time (WCET)
Introduction to Cache Analysis for Real-Time Systems [C. Ferdinand and R. Wilhelm, Efficient and Precise Cache Behavior Prediction for Real-Time Systems, Real-Time Systems, 17, 131-181, (1999)] Schedulability