Modeling Hardware Timing 1 Caches and Pipelines

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1 Modeling Hardware Timing 1 Caches and Pipelines Peter Puschner slides: P. Puschner, R. Kirner, B. Huber VU SS 2016

2 Generic WCET Analysis Framework source code Extraction of Flow Facts Compilation object code Transformation of Flow Facts Exec-Time Modeling Calculation of Execution Scenarios WCET 2

3 Exec-Time Modeling Exec-time modeling typically done before WCET calculation in separate phases: 1. cache analysis 2. pipeline analysis 3. path analysis + WCET calculation Above phases may be also combined to improve accuracy: Example: (1) cache analysis (2) pipeline analysis + path-based WCET calculation. 3

4 Modeling Pipelines Instruction timing represented by reservation tables: IF ID EX M F WB IF ID EX M F WB 4

5 Modeling Pipelines Basic operations on reservation tables: Sequential combination of two reservation tables IF ID EX M F WB IF ID EX M F WB IF ID EX M F WB 5

6 Modeling Pipelines Basic operations on reservation tables: Parallel combination of two reservation tables IF ID EX M F WB IF ID EX M F WB IF ID EX M F WB 6

7 Modeling Caches Types of caches: Instruction cache; Data cache; Unified cache (instruction + data); Cache layout: direct mapped; n-way set-associative cache; Replacement strategies: LRU (SPARC), pseudo-round robin (ColdFire MFC 5307, PPC 750/755) 7

8 Modeling Caches (2) Two approaches are presented: 1. Cache analysis integrated into IPET-based path analysis, resulting in the following phases: 1. pipeline analysis 2. cache analysis + path analysis + WCET calculation 2. Cache analysis as a separate phase using abstract interpretation (data-flow analysis), resulting in the following phases: 1. cache analysis 2. pipeline analysis 3. path analysis + WCET calculation 8

9 Direct Mapped Cache tag address word ld(m) bits ld(k) bits m lines Line: valid bit (v), tag and data (k bytes) Line 1 Line 2 Line is selected by ld(m) address bits v tag w 1 w 2... w k Line m 9

10 Modeling Caches with IPET here: Direct mapped instruction cache Each basic block B i is divided into {B i.1, B i.2,,b i.ni } l-blocks (cache line blocks). Two l-blocks can be conflicting: they map to the same cache line and overwrite the cache content of the other non-conflicting: they do not interfere in cache Execution counter x i of B i is divided into x i = x i.j hit + x i.j miss, 1 j n i ILP goal function: N n i i= 1 j= 1 hit hit miss miss ( xi. j ti. j + xi. j ti. j ) 10

11 Modeling Caches with IPET B 1 B 2 B 3 (i) CFG Ca che Line [Y.T.Steven Li,S.Malik,A.Wolfe,95] basic block Cac he line cache line block (l-block) B 1.1 B 1.2 Ba sic Bloc k B 1 B 3 B 1 B 1 B 2 B 2 B 3 B 1.3 B 2.1 (ii) Cache table B B 3.1 B 3.2

12 Modeling Caches with IPET Cache Constraints: only one l-block B k.l maps to the same cache line (first access is miss): miss x k. l 1 only two or more non-conflicting l-blocks map to the same cache line (first access is miss): x k x miss. + miss l m. n two or more conflicting l-blocks à use CCG 1 12

13 Modeling Caches with IPET A CCG (cache conflict graph) is constructed for each cache line containing two or more conflicting l-blocks. The sum of control flow going in the node must be the same as going out of the node: x i = u, v p( u. v, i. j) = u, v program exec. only once : p( i. j, u. v) u, v p( s, u. v) = 1 13

14 Modeling Caches with IPET CFG and its corresponding CCG: 1 c 1 B 1 s 11 c 2 B p (s,4.1) p (s,7.1) p (4.1,4.1) 0 p (7.1,7.1) 9 p (4.1,7.1) 10 c 3 B 3 1 c 5 B B 4.1 B p (7.1,4.1) 9 c 4 B 4 B c 6 B 6 0 p (4.1,e) 1 p (7.1,e) c 10 7 B B c 8 1 c 9 B 8 B 9 (i) CFG [Y.T.Steven Li,S.Malik,A.Wolfe,95] e (ii) CCG 0 p (s,e) these two lblocks are in conflict with each other (but with no other lblocks) à separate CCG for each conflict set 14

15 Modeling Caches with IPET bounding the cache hit frequency x i.j hit : p hit ( i. j, i. j) x. p( s, i. j) + p( i. j, i j) x hit i j. if an l-block B i,j has only a local lifetime ( ExistsEdge ( s, i. j) ExistsEdge( i. j, e ) above constraints can be simplified as: ( i. j, i j) i. j = p. Nested loops (B i.j in outer, B u,v in inner loop, B h is loop header of inner loop): p( i. j, u. v) x h 15

16 Modeling Caches with IPET Discussion Shown example: direct mapped instruction cache Elegant way to integrate exec-time modelling into WCET calculation. Approach can be extended to: n-way set-associative instruction caches; Interprocedural calls; data caches; Complexity: Set of IPET constraints becomes much bigger due to CCG. Time to solve IPET can take several hours!!! à Not feasible for real-size programs. 16

17 Summary Precise static WCET analysis requires an accurate exec-time model. Modeling of features like caches or pipelines. Precise and accurate exec-time modeling can result in complex models. 17

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Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. Yau-Tsun Steven Li Sharad Malik Andrew Wolfe

Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software Yau-Tsun Steven Li Sharad Malik Andrew Wolfe 1 Introduction Paper examines the problem of determining the bound on the worst