How to Achieve Deterministic Code Performance Using a Cortex -M Cache Controller

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1 How to Achieve Deterministic Code Performance Using a Cortex -M Cache Controller Introduction In microcontroller-based embedded applications, the software is stored and run from non-volatile memory, which is typically Flash memory. Although Flash memories provide an efficient medium to store and execute code, a number of factors limit the deterministic code performance when executed from Flash. One of the important factors impacting the deterministic code behavior is the intricacies of a system bus matrix. The issues of deterministic code performance are also seen when the code is run from SRAM due to the same reasons as that for the Flash memory. Non-deterministic code performance is primarily due to the varying propagation time of code from the memories to the CPU. The system bus matrix that interfaces the memories to CPU contributes to the varying propagation time. The non-deterministic code performance is more evident in systems with multiple entities accessing the system bus. In real-time applications, there are situations where small, critical pieces of code require time bound execution. It is not advised to run such code from Flash memory or SRAM, as it might not achieve the intended deterministic timing due to system bus arbitration, that is, a cache miss condition requires the code to be fetched from the Flash memory or SRAM. The code access time might vary depending on the availability to access system bus as it is arbitrated between multiple bus entities. The effective way to achieve deterministic code performance of critical code is to execute the code from the Tightly Coupled Memory (TCM) to the processor, and avoid cache miss conditions. The ARM Cortex -M Cache Controller (CMCC) peripheral on Microchip s Cortex-M4 based microcontrollers (MCUs) provides support to run the critical code from the cache memory and achieve deterministic performance Microchip Technology Inc. DS A-page 1

2 Table of Contents Introduction Concept Solution Deterministic Performance Analysis Relevant Resources The Microchip Web Site Customer Change Notification Service...13 Customer Support Microchip Devices Code Protection Feature Legal Notice...14 Trademarks Quality Management System Certified by DNV...15 Worldwide Sales and Service Microchip Technology Inc. DS A-page 2

3 Concept 1. Concept CMCC on Cortex-M4 based MCUs (i.e., SAME54) has a dedicated Four-way L1 set associative cache of 4 KB, as shown in the following figure. Figure 1-1. Four-way L1 Set Associative Cache Memory 16 bytes 1024 bytes WAY 0 WAY 1 WAY 2 WAY 3 Line 0 Line 1 Line 2... Line 61 Line 62 Line 63 With CMCC, a part of the cache can be used as TCM for deterministic code performance by loading the critical code in a WAY and locking it. When a particular WAY is locked, the CMCC does not use the locked WAY for routine cache transactions. The locked cache WAY with the loaded critical code acts as an always-getting cache hit condition Microchip Technology Inc. DS A-page 3

4 Solution 2. Solution The following flow sequence shows the code to implement deterministic code performance. Figure 2-1. Flow Sequence to Implement Deterministic Code Performance Disable Cache Invalidate cache lines on the desired WAY Disable Instruction Cache Enable Data Cache Enable Cache Load the critical code to the desired WAY Lock the WAY loaded with the critical code Enable back Instruction Cache The following code examples show the implementation of functions for achieving deterministic code performance and its usage on Cortex-M4 based MCUs (i.e., SAME54) Microchip Technology Inc. DS A-page 4

5 Solution Figure 2-2. Implementation of Macros and Variables Used in cmcc_loadnlock Function 2018 Microchip Technology Inc. DS A-page 5

6 Solution Figure 2-3. Implementation of cmcc_loadnlock Function 2018 Microchip Technology Inc. DS A-page 6

Solution The variable CMCC in the above implementation is defined as shown in the following example. The implementation provided is for the Cortex-M4 based device, SAME54P20A.

7 Solution The variable CMCC in the above implementation is defined as shown in the following example. The implementation provided is for the Cortex-M4 based device, SAME54P20A. The details of the structure implementation, and the definitions of macros CMCC_MAINT1_WAY, CMCC_MAINT1_INDEX, CMCC_CTRL_CEN and CMCC_SR_CSTS can be found in Microchip s Atmel START (ASF4) library. Figure 2-4. Declaration of CMCC Structure Implementation Refer to the following steps to implement the cmcc_loadnlock function: 1. When the cache is enabled, the CMCC uses the four WAYs of the set associative cache in round robin fashion starting with WAY0. This happens immediately after enabling the cache. 2. The cmcc_loadnlock function scans through the cache WAYs to locate the desired WAY (refer to the code example labeled A). 3. In a pass, if the desired WAY is not found, the cmcc_loadnlock function loads the entire WAY with values from an array so as to pass over the WAY under process and proceed to check whether the next WAY is the desired WAY (refer to the code example labeled B). 4. When the desired WAY is found, the cmcc_loadnlock function reads the critical code from Flash into a dummy variable to ensure that the critical code is stored in a cache WAY (refer to the code example labeled C). 5. In the labels marked B and C, the cmcc_loadnlock function loads only one word (4 bytes) out of the required four (16 bytes), this is because the WRAP4 feature of AHB fills in the gaps by loading the entire line of 16 bytes. 6. The cmcc_loadnlock function locks only the desired cached WAY to trap the critical code in the cache. When a particular WAY is locked, the CMCC discontinues using the locked WAY for the usual round robin cache transactions. The locking of a WAY and trapping the critical code in a cache, emulates a situation of calls made to the critical code getting 100% cache hit. 7. The implementation of the cmcc_loadnlock function shown above works for critical code size less than or equal to the size of a cache WAY (CMCC_WAYSIZE), that is, 1024 bytes. If the critical code size is larger than the size of a WAY, the critical code needs to be accommodated in a consecutive second WAY. To accommodate critical code of larger size the implementation of cmcc_loadnlock function needs to be enhanced. Consider the following guidelines for enhancing the implementation of the cmcc_loadnlock function The parameter,size, is to be evaluated to identify whether the critical code fits in the available cache of 4 KB. If it fits in the available cache, the implementation needs to identify how many cache WAYs are needed Microchip Technology Inc. DS A-page 7

8 Solution Usage 7.2. The implementation needs to identify if the required number of consecutive WAYs are available to be allocated for the critical code The implementation should invalidate the consecutive WAYs (refer to the code example labeled 1) The implementation should load the consecutive WAYs with the critical code (refer to the code example labeled C) The implementation should lock the consecutive WAYs so as to trap the code in cache (refer to the code example labeled 2) The following code example shows the usage of the cmcc_loadnlock function. Figure 2-5. Usage of the cmcc_loadnlock Function 1. The cmcc_loadnlock function accepts three parameters The first parameter way_bitfield is the number of the cache WAY, this would take one of the four WAY values (CMCC_WAY0, CMCC_WAY1, CMCC_WAY2, CMCC_WAY3) The second parameter,f, is the address of the critical code function that needs to run always from the cache The third parameter,size, is the size of the critical code function. The size should not be greater than the size of the cache WAY (CMCC_WAYSIZE). If the size is greater than the WAY size, enhance the implementation as mentioned in the above step seven. 2. The exact size of the critical code function (_critical_code_function) can be obtained from the project s listing file. Use the following steps to find the size of the critical code function In the previous example, the critical code function is declared with the section attribute _cc_function_section. This is an instruction to the GNU linker to place the function _critical_code_function in a code segment with the name _cc_function_section Place a dummy size in the cmcc_loadnlock function call Clean and build the project Microchip Technology Inc. DS A-page 8

Solution 2.4. Open the Project s listing file (.lss) and locate the linker symbol _cc_function_section. The line with linker symbol shows the size of the section.

9 Solution 2.4. Open the Project s listing file (.lss) and locate the linker symbol _cc_function_section. The line with linker symbol shows the size of the section. This is the size of the critical code function. Figure 2-6. Locating the _cc_function_section Attribute 2.5. Replace the size of the critical code function in the call cmcc_loadnlock with the size from the.lss file 2.6. Build and program. 3. The cmcc_loadnlock function can be used to dynamically store more than one critical code functions in the cache WAYs by calling it consecutively more than once. Note: 1. This document covers usage of the unified four WAY L1 associative cache for deterministic code performance optimization only. The CMCC also allows data caching, and to use a portion of the cache as data TCM. For additional information, refer the Cortex-M4 based MCU (SAME54) data sheet. 2. The deterministic code performance implementation discussed in this document comes with a trade-off by reducing the active cache size Microchip Technology Inc. DS A-page 9

10 Deterministic Performance Analysis 3. Deterministic Performance Analysis In a cache-enabled system, code performance is determined by the frequency of cache hit or cache miss conditions. The more the cache hit condition, the better the performance. In a simple application, for example, an application where there is only one function performing the key operation iteratively, there is a higher probability of cache hits. In contrast, in a complex real-time application, where multiple entities, such as System Bus Masters access the non-volatile memory, the code performance is limited by the higher probability of cache miss conditions due to the non-deterministic call sequence. In addition, there are delays due to the system bus matrix. The following is the performance analysis of a simple application when the code is run from TCM (using the loadnlock implementation discussed previously) against the regular cache-enabled transactions. The following functions of 1 KB size has the same code that are used for profiling. critical_code_function (); // [Referred as TCM] _function_1 (); // [Referred as C1] _function_2 (); // [Referred as C2] _function_3 (); // [Referred as C3] _function_4 (); // [Referred as C4] _function_5 (); // [Referred as C5] _function_6 (); // [Referred as C6] The critical code function [TCM] always runs from the cache (is locked in a cache WAY by calling loadnlock) while the other function runs from Flash and is cached by the CMCC-based on the round robin sequence. The functions above are called indefinitely in the same sequence. A 20-sample profile of the above function sequence running on a Cortex-M4 based processor (SAME54 MCU) at 120 MHz, 15 NVM wait states, and no code optimization is shown in the following figure. The vertical axis in the graph shows the time taken in microseconds (µs). Figure 3-1. Deterministic Code Performance Analysis Summary: The time taken by the code, running from TCM, is deterministic as it takes 6.47 or 6.48 µs. This is in contrast to the non-deterministic time taken by code running through routine cache 2018 Microchip Technology Inc. DS A-page 10

11 Deterministic Performance Analysis transactions. In a single pass, such as Pass 1, the time consumption for the code running through normal cache operations varies from 6.86 µs to 7.26 µs. The possible occurrences of cache miss conditions when the functions C3 and C6 are run. There is a sudden spike in the time consumed (C3 taking 7.19 µs and C6 taking 7.26 µs) for running these functions. In addition to the deterministic code performance, there is performance benefit for the code running from TCM against the code running from the cache-enabled transactions. For the simple application, in a single pass, such as Pass 1, the time consumed for the code running from TCM is 6.47 µs as against the code running through normal cache operations that varies from 6.86 µs to 7.26 µs. The code TCM implementation discussed above provides deterministic performance model for the critical code. It also provides performance benefits over code implementation with cache-enabled systems. The performance benefits are subject to the complexity of the application. As the complexity of the application increases, the performance benefits of the code executed from TCM appears evident Microchip Technology Inc. DS A-page 11

12 Relevant Resources 4. Relevant Resources For additional information, refer to these documents: SAM D5x/E5x Family Data Sheet: SMART SAM E70 TCM Memory: How to Optimize Usage of SAM S70/E70/V7x Architecture: Microchip Technology Inc. DS A-page 12

13 The Microchip Web Site Microchip provides online support via our web site at This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Product Support Data sheets and errata, application notes and sample programs, design resources, user s guides and hardware support documents, latest software releases and archived software General Technical Support Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip s customer notification service helps keep customers current on Microchip products. Subscribers will receive notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at Under Support, click on Customer Change Notification and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code Microchip Technology Inc. DS A-page 13

14 Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dspic, FlashFlex, flexpwr, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, maxstylus, maxtouch, MediaLB, megaavr, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picopower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyavr, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mtouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipkit, chipkit logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dspicdem, dspicdem.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorbench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies Microchip Technology Inc. DS A-page 14

15 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: Quality Management System Certified by DNV ISO/TS Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dspic DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9001:2000 certified Microchip Technology Inc. DS A-page 15

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