Interfacing 23X512/1024 SDI/SQI Serial SRAM Devices to NXP LPC18XX/43XX Microcontrollers Using the SPIFI Peripheral. Vcc B13

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Interfacing 23X512/1024 SDI/SQI Serial SRAM Devices to NXP LPC18XX/43XX Microcontrollers Using the SPIFI Peripheral Author: INTRODUCTION Dragos Ciofu Microchip Technology Inc.

1 Interfacing 23X512/1024 SDI/SQI Serial SRAM Devices to NXP LPC18XX/43XX Microcontrollers Using the SPIFI Peripheral Author: INTRODUCTION Dragos Ciofu Microchip Technology Inc. Microchip s serial SRAM product line represents a flexible way to add additional RAM to an application. Available in PDIP, TSSOP and SOIC packages, Microchip s serial SRAM gives designers added flexibility when it comes to compatibility and cost effectiveness. With added Quad-SPI (SQI) capabilities and high clock rates, the 23X512/1024 devices eliminate the throughput penalty of a serial bus, while keeping the PCB impact and BOM costs to a minimum. The 23X512/1024 devices are also capable of operating in SDI and SPI mode. With clock rates up to 20 MHz, the 23X512/1024 SRAM provides a theoretical throughput of 80 Mbit/sec in SQI mode. This application note is targeted at customers using MCUs that offer Quad mode SPI capabilities, and who want to take advantage of the higher throughput capabilities offered by Microchip s Serial SRAM, when operated in the SQI mode. The serial bus is controlled by the microcontroller (master) which accesses the 23X512/1024 device using the MCUs SPIFI peripheral, configured for manual operation (as opposed to Flash operation). Figure 1 describes the hardware schematic for the interface between a Microchip 23X512/1024 device and an NXP LPC4357 device in an LBGA256 package. The 23X512/1024 device pinout does not vary with package, as opposed to third party microcontrollers. Users are advised to consult their chosen master device s data sheet and manufacturer notes to ensure pin-to-pin compatibility between families of microcontrollers. The schematic shows the connections between the SRAM and microcontroller, and the software is provided assuming these connections. The HOLD pin is tied to SPI_SIO3, being used as the fourth lane in the SQI bus. FIGURE 1: SCHEMATIC LPC4357 FET256 SPI_MISO SPI_MOSI SPI_SIO2 SPI_SIO3 SPI_CLK SPI_CS Vcc B13 C11 C12 A15 B14 C10 CS VCC SO/SIO1 HOLD/SIO3 SIO2 23X512/1024 SCK VSS SO/SIO Microchip Technology Inc. DS A-page 1

2 FIRMWARE DESCRIPTION The scope of this application note is to highlight the capabilities of Microchip s SRAM range. Bus protocol implementations vary from manufacturer to manufacturer, but Microchip s SRAM devices boast excellent compatibility, provided the protocol standards are adhered to. The provided firmware targets an NXP LPC4357 microcontroller, but the firmware is compatible with all devices from NXP s 18xx and 43xx families. The code targets NXP s proprietary SPIFI peripheral (port) and controls it with a command API available for the user of the 23X512/1024 device. The firmware was tested using a 23A1024 SQI SRAM device, attached to a LPC4357-EVB produced by EMBEST. This particular EVB implements an LPC4357 part that has on-chip Flash. The on-chip Flash option is necessary in order to have the SPIFI port available for other slave devices (in this case the Microchip 23A1024 SRAM). The ports employed for connecting the SRAM to the LPC device are pictured in the schematic in Figure 1. The SPIFI peripheral has a configurable clock frequency, as set from the firmware, and the 23A1024 SRAM device can operate with a clock frequency of up to 20 MHz without any explicit clock configuration sequence. The IDE used for developing the firmware is Keil uvision V In order to build the target, the LPCOpen v2.09 chip support library is needed, available on the MCU vendor s web site ( files/lpcopen_2_09_keil_iar_keil_mcb_4357_1.zip). Both oscilloscope screen captures and logic analyzer screen shots are shown in this application note. The following functions are provided to access the Serial SRAM: SRAMWriteSeq SRAMReadSeq SRAMWriteByte SRAMReadByte SRAMWritePage SRAMReadPage SRAMSetIOMode SRAMResetIOMode SRAMReadModeReg SRAMWriteModeReg The above functions are defined in the driver files SRAM_Driver.c, with respective declarations in SRAM_Driver.h. This file pair can be directly imported into the user s application code. The functions are called from Main_Demo.c. The main demo file cycles through all possible bus modes (SPI/SDI/SQI) while performing IO operations in all different memory modes (BYTE, PAGE, SEQUENTIAL). INITIALIZATION The 23X512/1024 devices do not require any specific initialization. The internal state machine drives the outputs and coordinates the read/write operations based on the external clock issued by the master device. However, in this case, the LPC microcontroller needs initialization, which is done by calling the included functions: spifiperipheralconfig spifiperipheralinit The peripheral configuration function must be called with the desired frequency (in Hz) as a parameter, while the peripheral initialization function needs the reference to a variable mapped in the peripheral memory addressable range. This latter variable acts as a handle for all operations using the SPIFI peripheral, whose registers are addressable starting from the 0x or (LPC_SPIFI_BASE) address. DS A-page Microchip Technology Inc.

3 BUS MODES The 23X512/1024 part can be accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) and separate data in (SI) and data out (SO) pins. Access is controlled through a Chip Select (CS) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) are supported if the application needs faster data rates. In SDI mode, the SI and SO lines are half duplex and behave as SIO0 and SIO1 (from the microcontroller s point of view). In SQI mode, the SI, SO, SIO2 and SIO3 behave as a half-duplex four lane bus, and the HOLD/SIO3 pin loses its HOLD alternate function. INSTRUCTION SET TABLE 1: INSTRUCTION SET Instruction Name Instruction Format Hex Code Description READ x03 Read data from memory array beginning at selected address WRITE x02 Write data to memory array beginning at selected address EDIO x3B Enter Dual I/O access EQIO x38 Enter Quad I/O access RSTIO xFF Reset Dual and Quad I/O access RDMR x05 Read Mode Register WRMR x01 Write Mode Register 2014 Microchip Technology Inc. DS A-page 3

4 ENTER DUAL I/O ACCESS To set SDI as a bus mode the EDIO (0x3B) instruction must be clocked in. The master device must be aware if the bus mode has been changed before issuing any bus mode change instructions. EDIO can be transmitted if the bus is in SPI or SQI modes. If the bus is already in SDI mode, the EDIO instruction will not reset the bus mode and will have no effect. Figure 2 represents the transmission of an EDIO (0x3B) instruction using the SPI protocol. The corresponding function call in the provided firmware is: SRAMSetIOMode(SDI, SPI) FIGURE 2: ENTER DUAL I/O ACCESS (SPI MODE) Enter SDI Mode (EDIO) from SPI Mode CS SCK SI SO High-Impedance DS A-page Microchip Technology Inc.

5 Figure 3 represents the transmission of an EDIO (0x3B) instruction using the SQI protocol The corresponding function call in the provided firmware is: SRAMSetIOMode(SDI, SQI) FIGURE 3: ENTER DUAL I/O ACCESS (SQI MODE) B 2014 Microchip Technology Inc. DS A-page 5

6 ENTER QUAD I/O ACCESS To set SQI as a bus mode the EQIO (0x38) instruction must be clocked in. The master device must be aware if the bus mode has been changed before transmitting any bus mode change instructions. EQIO can be transmitted if the bus is in SPI or SDI modes. If the bus is already in SQI mode, the EQIO instruction will not reset the bus mode and will have no effect. Figure 4 represents the transmission of an EQIO (0x38) instruction using the SPI protocol. The corresponding function call in the provided firmware is: SRAMSetIOMode(SQI, SPI) FIGURE 4: ENTER QUAD I/O ACCESS (SPI MODE) Enter SQI Mode (EQIO) From SPI Mode CS SCK SI SO High-Impedance DS A-page Microchip Technology Inc.

7 Figure 5 represents the transmission of an EQIO (0x38) instruction using the SDI protocol The corresponding function call in the provided firmware is: SRAMSetIOMode(SQI, SDI) FIGURE 5: ENTER QUAD I/O ACCESS (SDI MODE) Microchip Technology Inc. DS A-page 7

8 RESET DUAL AND QUAD I/O ACCESS To reset the bus mode from SQI or SDI modes back to SPI mode, the RSTIO (0xFF) instruction must be clocked in. The master device must be aware of the current bus mode before issuing the RSTIO instruction. The corresponding function call in this case is one of the following: SRAMResetIOMode (SDI) Or SRAMResetIOMode (SQI) If the bus mode is not known, the master device can transmit two RSTIO instructions using both the SDI and SQI formats to ensure a proper reset to SPI mode. This double transmit has no side effects over the SRAM. This is highlighted in the provided firmware, and corresponding function call is: SRAMResetIOMode (TBD) Figure 6 represents the transmission of an RSTIO (0xFF) instruction using the SDI protocol. FIGURE 6: RESET DUAL AND QUAD I/O ACCESS (SDI MODE) DS A-page Microchip Technology Inc.

9 Figure 7 represents the transmission of an RSTIO (0xFF) instruction using the SQI protocol, followed by the same instruction on the SDI protocol, as mentioned above. FIGURE 7: RESET DUAL AND QUAD I/O ACCESS (SQI MODE, SDI MODES) FF FF 2014 Microchip Technology Inc. DS A-page 9

10 WRITE MODE REGISTER The default mode of operation for the 23X512/1024 devices is Sequential mode, and the user must select the appropriate mode before any IO operation. The Write Mode Register instruction (WRMR) allows the users to write the bits 7 and 6 in the Mode register 00 = Byte mode 10 = Page mode 01 = Sequential mode (default operation) 11 = Reserved Figure 8 represents the transmission of a WRMR (0x01) instruction with the Page bits (0x80) as the parameter, using the SPI protocol. The corresponding function call in the provided firmware is: SRAMWriteModeReg(PAGE,SPI) FIGURE 8: WRITE MODE REGISTER (SPI MODE) Write Mode Register Timing Sequence CS SCK Instruction Data to Mode Register SI SO High-Impedance DS A-page Microchip Technology Inc.

11 Figure 9 represents the transmission of a WRMR (0x01) instruction with the PAGE bits (0x80) as the parameter, using the SDI protocol. On each clock, two bits are transmitted and the is found on the SIO1 line. Only eight clock cycles are required to shift 2 bytes of data. The corresponding function call in the provided firmware is: SRAMWriteModeReg(PAGE,SDI) FIGURE 9: WRITE MODE REGISTER (SDI MODE) Microchip Technology Inc. DS A-page 11

12 Figure 10 represents the transmission of a WRMR (0x01) instruction with the PAGE bits (0x80) as the parameter, using the SQI protocol. On each clock, the is found on the SIO3 line and the LSB on the SIO0 line. A 4-bit nibble is transmitted on each clock pulse. Only four clocks are required to shift two bytes of data. The corresponding function call in the provided firmware is: SRAMWriteModeReg(PAGE,SQI) FIGURE 10: WRITE MODE REGISTER (SQI MODE) DS A-page Microchip Technology Inc.

13 READ MODE REGISTER The Read Mode Register instruction (RDMR) provides access to the 23X512/1024 SRAM s Mode register. Figure 11 represents the transmission of a RDMR (0x05) instruction using the SPI protocol. The PAGE bits (0x80) are expected on the MISO line. The corresponding function call in the provided firmware is: SRAMReadModeReg(SPI) FIGURE 11: READ MODE REGISTER (SPI MODE) Read Mode Register Timing Sequence (RDMR) CS SCK Instruction SI SO High-Impedance Data from Mode Register Microchip Technology Inc. DS A-page 13

14 Figure 12 represents the transmission of a RDMR (0x05) instruction using the SDI protocol. In this case, the SEQ bits (0x40) are expected on the SIO1 and SIO0 lines. The is found on the SIO1 line. The corresponding function call in the provided firmware is: SRAMReadModeReg(SDI) FIGURE 12: READ MODE REGISTER (SDI MODE) DS A-page Microchip Technology Inc.

Figure 13 represents the transmission of a RDMR (0x05) instruction using the SQI protocol. In this case the PAGE bits (0x80) are expected on the SIO3 through SIO0 lines. The is found on the SIO3 line.

15 Figure 13 represents the transmission of a RDMR (0x05) instruction using the SQI protocol. In this case the PAGE bits (0x80) are expected on the SIO3 through SIO0 lines. The is found on the SIO3 line. A 4-bit nibble is transmitted on each clock pulse. Only four clocks are required to shift two bytes of data, one in each direction. SRAMReadModeReg(SQI) FIGURE 13: READ MODE REGISTER (SQI MODE) Microchip Technology Inc. DS A-page 15

16 BYTE WRITE In order to write a byte in either mode, the WRITE instruction (0x02) must be transmitted by the master, followed by the 24-bit address and the 8-bit data to be written. This is depicted in Figure 14. FIGURE 14: BYTE WRITE (SPI MODE) The corresponding function call in the provided firmware is: SRAMWriteByte(0x0123AB, data, SPI) (where *data=0x7a) DS A-page Microchip Technology Inc.

17 Figure 15 represents a WRITE instruction in SDI mode. The corresponding function call is: SRAMWriteByte(0x0123AB, data, SDI) FIGURE 15: BYTE WRITE (SDI MODE) AB 7B 2014 Microchip Technology Inc. DS A-page 17

18 Figure 16 represents a WRITE instruction in SQI mode. The corresponding function call is: SRAMWriteByte(0x0123AB, data, SQI) (where *data=0x7a) FIGURE 16: BYTE WRITE (SQI MODE) AB 7B DS A-page Microchip Technology Inc.

19 BYTE READ In order to read a byte in either mode, the READ instruction (0x03) must be transmitted by the master, followed by the 24-bit address. In SDI and SQI modes, one more additional dummy byte must be clocked before any actual data is sent on the bus by the SRAM. Figure 17 represents a READ instruction in SPI mode. The corresponding function call is: SRAMReadByte(0x0123AB, data, SPI) FIGURE 17: BYTE WRITE (SPI MODE) Microchip Technology Inc. DS A-page 19

20 Figure 18 represents a READ instruction in SDI mode. Notice that clocks 16 through 19 are the dummy byte clocks. The corresponding function call is: SRAMReadByte(0x0123AB, data, SDI) FIGURE 18: BYTE READ (SDI MODE) AB FF 7B DS A-page Microchip Technology Inc.

21 Figure 19 represents a READ instruction in SQI mode. The corresponding function call is: SRAMReadByte(0x0123AB, data, SQI) The waveform is similar to the WRITE waveform, the differences lie in the command word and the extra dummy byte that is read. FIGURE 19: BYTE READ (SQI MODE) AB BB 7B 2014 Microchip Technology Inc. DS A-page 21

22 PAGE AND SEQUENTIAL MODES The 23X512/1024 parts have three modes of operation that are selected by setting bits 7 and 6 in the Mode register, as specified above in the Write Mode Register section. In Page mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x00000; Figure 20 represents a two-byte-wide sequential write. The number of clocks required is two for the instruction, six for the address and four for the two bytes of data. The corresponding function call is: SRAMWriteSeq (0x123AB, data, 2, SQI) FIGURE 20: SEQUENTIAL WRITE - 2 BYTES (SQI MODE) AB BB 7B 7B7C DS A-page Microchip Technology Inc.

23 CONCLUSION This application note offers designers a set of firmware routines to access Microchip SPI/SDI/SQI serial SRAMs from another target than the PIC device series of microcontrollers. This demonstrates Microchip s SRAM series excellent compatibility, translated into lower development costs and faster time to market Microchip Technology Inc. DS A-page 23

24 APPENDIX A: REVISION HISTORY Revision A (09/2014) Initial release of this document. DS A-page Microchip Technology Inc.

25 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS == Trademarks The Microchip name and logo, the Microchip logo, dspic, FlashFlex, flexpwr, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC 32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mtouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipkit, chipkit logo, CodeGuard, dspicdem, dspicdem.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dspic DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9001:2000 certified Microchip Technology Inc. DS A-page 25

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Section 40. Introduction (Part IV)

Section 40. Introduction (Part IV) HIGHLIGHTS This section of the manual contains the following major topics: 40.1 Introduction... 40-2 40.2 Revision History...40-3 40 Introduction (Part IV) 2007-2012