Preemption Delay Analysis for the Stack Cache

Size: px
Start display at page:

Download "Preemption Delay Analysis for the Stack Cache"

Transcription

1 Preemption Delay nalysis for the Stack ache mine Naji U2IS ENST ParisTech Florian randner LTI, NRS Telecom ParisTech This work is supported by the Digiteo project PM-TOP. 1/18

2 Real-Time Systems Strict timing guarantees ritical tasks have to be completed in time 2/18

3 Real-Time Systems Strict timing guarantees ritical tasks have to be completed in time ound Worst-ase Execution Time (WET) Worst-ase Execution Time ound # Executions Worst-ase Execution Time est-ase Execution Time verage Execution Time Overestimation Execution Time 2/18

4 ache Related Preemption Delay - On Standard aches ache Related Preemption Delay (RPD): Time penalty introduced by cache misses due to task preemption. τ1 Preemption τ2 ache state 0x100 0x103 0x102 0x104 τ1 modifies the cache 0x100 0x105 0x103 0x104 0x100 0x103 0x102 0x104 ache miss Penalty Time Some cache blocks of a preempting task may evict cache blocks of a preempted task. ache misses may occur when the preempted task is resumed. 3/18

5 What is a Stack ache? Dedicated cache for stack data Simple ring buer (FIFO replacement) ll stack accesses are guaranteed hits (no need to analyze them) Dedicated stack control instructions (need to be analyzed) sres x : reserve x blocks on the stack sfree x : free x blocks on the stack sens x : ensure that at least x blocks are cached Intuitively: a cache window following the stack top 4/18

6 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

7 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

8 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

9 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

10 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

11 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

12 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

13 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

14 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

15 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

16 Example: Stack ache (1) function () function () function () (2) sres 2 <0> sres 2 <0> sres 3 <3> (3) call () call () sfree 3 (4) sens 2 <2> sens 2 <1> (5) sfree 2 sfree 2 Logical stack Stack cache ache conguration: 4 blocks 5/18

17 ache Related Preemption Delay - On Stack ache The original design of the stack cache did not consider the multitasking aspects. The stack space cannot be shared with tasks. ontext of preempted task has to be saved/restored. Two analysis problems: ontext Saving ontext Restoring We seek to compute RPD relative to the stack cache. 6/18

18 Preemption ost Examples 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) sfree 3 7/18

19 Preemption ost Examples 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) sfree i 2 i 2 i 3 i 2 i 5 i 4 Simple approach. 7/18

20 Preemption ost Examples 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) sfree i 2 i 2 i 3 i 2 i 5 i 4 i 2 i 2 i 3 i 2 i 5 i 4 Simple approach. Improved approach. 7/18

21 Drawbacks of the Naïve pproach Naive approach: Simple analysis, only based on the cache occupancy (originally provided by S analysis) However, some inaccuracies may be introduced... Not all saved/restored data may be accessed afterwards. Unnecessary saving of coherent data to main memory. nalysis does not take advantage of placement of ensures 8/18

22 ontext Saving nalysis - Overview Split the stack cache into three regions by introducing two pointers: Dead Pointer (DP) keeps track of dead data. Lazy Pointer (LP) keeps track of coherent data. Two pointer denes two areas, Dead rea is located below DP, while oherent rea is located above LP. Regions size is computed using local data-ow analyses. MT LP DP ST oherent data Data to save Dead data 9/18

23 ontext Restoring nalysis - Overview Split the stack cache into three dierent regions introducing two pointers Dead data is not restored, and Restore Pointer (RP) keeps track of data that has to be restored explicitly. sens instruction will load the rest. Size of these regions is computed using function local data-ow analyses. Only the stack frame of the current function is restored Inter-procedural analysis accounts for additional overheads 10/18 MT RP DP ST Ensured data Data to restore Dead data

24 Global ost of Ensure Instruction Intuitively, sens instructions will partially restore stack frames for free. We need to account for the additional cost paid by sens instructions. 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) sfree 3 11/18

25 Global nalysis of Ensure ost osts can be derived from the longest path in a weighted G from the program's entry node to the current function. Weights represents the dierence between the corresponding ensure bounds and the calling function reserved size. Path length represent additional cost. 12/18

26 Global nalysis of Ensure ost - Example Global Ensure and Reserve nalyses - Example: 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) sfree 3 13/18

27 Global nalysis of Ensure ost - Example Global Ensure and Reserve nalyses - Example: 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) sfree /18

28 Global nalysis of Ensure ost - Example Global Ensure and Reserve nalyses - Example: 1 ) func () 2 ) sres ) () 4 ) sens ) sfree 2 1 ) func () 2 ) sres ) () 5 ) sens ) sfree 2 1 ) func () 2 ) sres ) nop 4 ) sfree Observation The length of the path is bounded by the stack cache size and the minimum amount of stack data remaining in the stack cache after returning from the function. 13/18

29 Experimental Setup Miench benchmark suite LLVM compiler 3.5 for the Patmos processor ompiled with optimizations enabled (-O2) Stack cache congurations: 256 ompile benchmarks and perform preemption delay analyses 14/18

30 Experiments: ontext Saving nalysis Full Optimized # asic locks > 250 Transfer osts (bytes) Shift from right to the left Improvement in around 16% of basic blocks 15/18

31 Experiments: ontext Restoring nalysis Full Optimized # asic locks > 250 Transfer osts (bytes) Drastic shift from right to the left Improvement in around 99% of basic blocks In some cases the program runs even faster (1.7%) 16/18

32 onclusion We proposed a static analysis to determine preemption delay associated with the stack cache. Several function-local data-ow analysis Inter-procedural eects are handled through variants of the longest path problem. 17/18

33 Thanks for your attention ny Question? Full Optimized # asic locks > 250 Transfer osts (bytes) 18/18

Static Analysis of Worst-Case Stack Cache Behavior

Static Analysis of Worst-Case Stack Cache Behavior Static Analysis of Worst-Case Stack Cache Behavior Florian Brandner Unité d Informatique et d Ing. des Systèmes ENSTA-ParisTech Alexander Jordan Embedded Systems Engineering Sect. Technical University

More information

Static Analysis of Worst-Case Stack Cache Behavior

Static Analysis of Worst-Case Stack Cache Behavior Static Analysis of Worst-Case Stack Cache Behavior Alexander Jordan 1 Florian Brandner 2 Martin Schoeberl 2 Institute of Computer Languages 1 Embedded Systems Engineering Section 2 Compiler and Languages

More information

Preemption-Aware Caching for Predictability and Performance

Preemption-Aware Caching for Predictability and Performance Selfish-LRU: Preemption-ware aching for Predictability and Performance Jan Reineke Sebastian ltmeyer aniel Grund Sebastian Hahn laire Maiza S a a r l a n d U n i v e r s i t y, G e r m a n y University

More information

Cooperative Memory Management in Embedded Systems

Cooperative Memory Management in Embedded Systems ooperative Memory Management in Embedded Systems, Philip Taffner, hristoph Erhardt, hris7an Dietrich, Michael S7lkerich Department of omputer Science 4 Distributed Systems and Opera7ng Systems 1 2 Motivation

More information

Caches in Real-Time Systems. Instruction Cache vs. Data Cache

Caches in Real-Time Systems. Instruction Cache vs. Data Cache Caches in Real-Time Systems [Xavier Vera, Bjorn Lisper, Jingling Xue, Data Caches in Multitasking Hard Real- Time Systems, RTSS 2003.] Schedulability Analysis WCET Simple Platforms WCMP (memory performance)

More information

Caches in Real-Time Systems. Instruction Cache vs. Data Cache

Caches in Real-Time Systems. Instruction Cache vs. Data Cache Caches in Real-Time Systems [Xavier Vera, Bjorn Lisper, Jingling Xue, Data Caches in Multitasking Hard Real- Time Systems, RTSS 2003.] Schedulability Analysis WCET Simple Platforms WCMP (memory performance)

More information

Operating Systems (2INC0) 2017/18

Operating Systems (2INC0) 2017/18 Operating Systems (2INC0) 2017/18 Virtual Memory (10) Dr Courtesy of Dr I Radovanovic, Dr R Mak System rchitecture and Networking Group genda Recap memory management in early systems Principles of virtual

More information

A Simple Example. The Synchronous Language Esterel. A First Try: An FSM. The Esterel Version. The Esterel Version. The Esterel Version

A Simple Example. The Synchronous Language Esterel. A First Try: An FSM. The Esterel Version. The Esterel Version. The Esterel Version The Synchronous Language Prof. Stephen. Edwards Simple Example The specification: The output O should occur when inputs and have both arrived. The R input should restart this behavior. First Try: n FSM

More information

Introduction. 1 Measuring time. How large is the TLB? 1.1 process or wall time. 1.2 the test rig. Johan Montelius. September 20, 2018

Introduction. 1 Measuring time. How large is the TLB? 1.1 process or wall time. 1.2 the test rig. Johan Montelius. September 20, 2018 How large is the TLB? Johan Montelius September 20, 2018 Introduction The Translation Lookaside Buer, TLB, is a cache of page table entries that are used in virtual to physical address translation. Since

More information

Concurrent activities in daily life. Real world exposed programs. Scheduling of programs. Tasks in engine system. Engine system

Concurrent activities in daily life. Real world exposed programs. Scheduling of programs. Tasks in engine system. Engine system Real world exposed programs Programs written to interact with the real world, outside the computer Programs handle input and output of data in pace matching the real world processes Necessitates ability

More information

AUTOBEST: A United AUTOSAR-OS And ARINC 653 Kernel. Alexander Züpke, Marc Bommert, Daniel Lohmann

AUTOBEST: A United AUTOSAR-OS And ARINC 653 Kernel. Alexander Züpke, Marc Bommert, Daniel Lohmann AUTOBEST: A United AUTOSAR-OS And ARINC 653 Kernel Alexander Züpke, Marc Bommert, Daniel Lohmann alexander.zuepke@hs-rm.de, marc.bommert@hs-rm.de, lohmann@cs.fau.de Motivation Automotive and Avionic industry

More information

WCET-Aware C Compiler: WCC

WCET-Aware C Compiler: WCC 12 WCET-Aware C Compiler: WCC Jian-Jia Chen (slides are based on Prof. Heiko Falk) TU Dortmund, Informatik 12 2015 年 05 月 05 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply.

More information

CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES

CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES PITFALLS AND SOLUTIONS 1 Claire Burguière, Jan Reineke, Sebastian Altmeyer 2 Abstract In preemptive real-time systems, scheduling analyses

More information

The Esterel Language. The Esterel Version. Basic Ideas of Esterel

The Esterel Language. The Esterel Version. Basic Ideas of Esterel The Synchronous Language Esterel OMS W4995-02 Prof. Stephen. Edwards Fall 2002 olumbia University epartment of omputer Science The Esterel Language eveloped by Gérard erry starting 1983 Originally for

More information

Figure 1: Organisation for 128KB Direct Mapped Cache with 16-word Block Size and Word Addressable

Figure 1: Organisation for 128KB Direct Mapped Cache with 16-word Block Size and Word Addressable Tutorial 12: Cache Problem 1: Direct Mapped Cache Consider a 128KB of data in a direct-mapped cache with 16 word blocks. Determine the size of the tag, index and offset fields if a 32-bit architecture

More information

What s An OS? Cyclic Executive. Interrupts. Advantages Simple implementation Low overhead Very predictable

What s An OS? Cyclic Executive. Interrupts. Advantages Simple implementation Low overhead Very predictable What s An OS? Provides environment for executing programs Process abstraction for multitasking/concurrency scheduling Hardware abstraction layer (device drivers) File systems Communication Do we need an

More information

Cache Memory COE 403. Computer Architecture Prof. Muhamed Mudawar. Computer Engineering Department King Fahd University of Petroleum and Minerals

Cache Memory COE 403. Computer Architecture Prof. Muhamed Mudawar. Computer Engineering Department King Fahd University of Petroleum and Minerals Cache Memory COE 403 Computer Architecture Prof. Muhamed Mudawar Computer Engineering Department King Fahd University of Petroleum and Minerals Presentation Outline The Need for Cache Memory The Basics

More information

Chapter 8: Virtual Memory. Operating System Concepts

Chapter 8: Virtual Memory. Operating System Concepts Chapter 8: Virtual Memory Silberschatz, Galvin and Gagne 2009 Chapter 8: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating

More information

CS6401- Operating System UNIT-III STORAGE MANAGEMENT

CS6401- Operating System UNIT-III STORAGE MANAGEMENT UNIT-III STORAGE MANAGEMENT Memory Management: Background In general, to rum a program, it must be brought into memory. Input queue collection of processes on the disk that are waiting to be brought into

More information

A Scalable SAS Machine

A Scalable SAS Machine arallel omputer Organization and Design : Lecture 8 er Stenström. 2008, Sally. ckee 2009 Scalable ache oherence Design principles of scalable cache protocols Overview of design space (8.1) Basic operation

More information

Week 2: Tiina Niklander

Week 2: Tiina Niklander Virtual memory Operations and policies Chapters 3.4. 3.6 Week 2: 17.9.2009 Tiina Niklander 1 Policies and methods Fetch policy (Noutopolitiikka) When to load page to memory? Placement policy (Sijoituspolitiikka

More information

Operating Systems, Fall

Operating Systems, Fall Policies and methods Virtual memory Operations and policies Chapters 3.4. 3.6 Week 2: 17.9.2009 Tiina Niklander 1 Fetch policy (Noutopolitiikka) When to load page to memory? Placement policy (Sijoituspolitiikka

More information

OPERATING SYSTEM. Chapter 9: Virtual Memory

OPERATING SYSTEM. Chapter 9: Virtual Memory OPERATING SYSTEM Chapter 9: Virtual Memory Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory

More information

CS307: Operating Systems

CS307: Operating Systems CS307: Operating Systems Chentao Wu 吴晨涛 Associate Professor Dept. of Computer Science and Engineering Shanghai Jiao Tong University SEIEE Building 3-513 wuct@cs.sjtu.edu.cn Download Lectures ftp://public.sjtu.edu.cn

More information

Start of Lecture: February 10, Chapter 6: Scheduling

Start of Lecture: February 10, Chapter 6: Scheduling Start of Lecture: February 10, 2014 1 Reminders Exercise 2 due this Wednesday before class Any questions or comments? 2 Scheduling so far First-Come-First Serve FIFO scheduling in queue without preempting

More information

ECE331: Hardware Organization and Design

ECE331: Hardware Organization and Design ECE331: Hardware Organization and Design Lecture 24: Cache Performance Analysis Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Last time: Associative caches How do we

More information

Threads and Concurrency

Threads and Concurrency Threads and Concurrency 1 Threads and Concurrency key concepts threads, concurrent execution, timesharing, context switch, interrupts, preemption reading Three Easy Pieces: Chapter 26 (Concurrency and

More information

Review question: Protection and Security *

Review question: Protection and Security * OpenStax-CNX module: m28010 1 Review question: Protection and Security * Duong Anh Duc This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 3.0 Review question

More information

Threads and Concurrency

Threads and Concurrency Threads and Concurrency 1 Threads and Concurrency key concepts threads, concurrent execution, timesharing, context switch, interrupts, preemption reading Three Easy Pieces: Chapter 26 (Concurrency and

More information

ECE Sample Final Examination

ECE Sample Final Examination ECE 3056 Sample Final Examination 1 Overview The following applies to all problems unless otherwise explicitly stated. Consider a 2 GHz MIPS processor with a canonical 5-stage pipeline and 32 general-purpose

More information

ECE7995 Caching and Prefetching Techniques in Computer Systems. Lecture 8: Buffer Cache in Main Memory (I)

ECE7995 Caching and Prefetching Techniques in Computer Systems. Lecture 8: Buffer Cache in Main Memory (I) ECE7995 Caching and Prefetching Techniques in Computer Systems Lecture 8: Buffer Cache in Main Memory (I) 1 Review: The Memory Hierarchy Take advantage of the principle of locality to present the user

More information

Course Outline. Processes CPU Scheduling Synchronization & Deadlock Memory Management File Systems & I/O Distributed Systems

Course Outline. Processes CPU Scheduling Synchronization & Deadlock Memory Management File Systems & I/O Distributed Systems Course Outline Processes CPU Scheduling Synchronization & Deadlock Memory Management File Systems & I/O Distributed Systems 1 Today: Memory Management Terminology Uniprogramming Multiprogramming Contiguous

More information

ITEC2620 Introduction to Data Structures

ITEC2620 Introduction to Data Structures T2620 ntroduction to ata Structures Lecture 4a inary Trees Review of Linked Lists Linked-Lists dynamic length arbitrary memory locations access by following links an only traverse link in forward direction

More information

Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System

Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System Center for Information ervices and High Performance Computing (ZIH) Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor ystem Parallel Architectures and Compiler Technologies

More information

CS 136: Advanced Architecture. Review of Caches

CS 136: Advanced Architecture. Review of Caches 1 / 30 CS 136: Advanced Architecture Review of Caches 2 / 30 Why Caches? Introduction Basic goal: Size of cheapest memory... At speed of most expensive Locality makes it work Temporal locality: If you

More information

Best Practice for Caching of Single-Path Code

Best Practice for Caching of Single-Path Code Best Practice for Caching of Single-Path Code Martin Schoeberl, Bekim Cilku, Daniel Prokesch, and Peter Puschner Technical University of Denmark Vienna University of Technology 1 Context n Real-time systems

More information

A program execution is memory safe so long as memory access errors never occur:

A program execution is memory safe so long as memory access errors never occur: A program execution is memory safe so long as memory access errors never occur: Buffer overflows, null pointer dereference, use after free, use of uninitialized memory, illegal free Memory safety categories

More information

Addresses in the source program are generally symbolic. A compiler will typically bind these symbolic addresses to re-locatable addresses.

Addresses in the source program are generally symbolic. A compiler will typically bind these symbolic addresses to re-locatable addresses. 1 Memory Management Address Binding The normal procedures is to select one of the processes in the input queue and to load that process into memory. As the process executed, it accesses instructions and

More information

Virtual Memory Outline

Virtual Memory Outline Virtual Memory Outline Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory Other Considerations Operating-System Examples

More information

Memory hierarchy. 1. Module structure. 2. Basic cache memory. J. Daniel García Sánchez (coordinator) David Expósito Singh Javier García Blas

Memory hierarchy. 1. Module structure. 2. Basic cache memory. J. Daniel García Sánchez (coordinator) David Expósito Singh Javier García Blas Memory hierarchy J. Daniel García Sánchez (coordinator) David Expósito Singh Javier García Blas Computer Architecture ARCOS Group Computer Science and Engineering Department University Carlos III of Madrid

More information

Artificial Intelligence

Artificial Intelligence rtificial Intelligence Robotics, a ase Study - overage Many applications: Floor cleaning, mowing, de-mining,. Many approaches: Off-line or On-line Heuristic or omplete Multi-robot, motivated by robustness

More information

Chapter 9: Virtual Memory

Chapter 9: Virtual Memory Chapter 9: Virtual Memory Background Demand Paging Chapter 9: Virtual Memory Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory Other Considerations

More information

Static WCET Analysis: Methods and Tools

Static WCET Analysis: Methods and Tools Static WCET Analysis: Methods and Tools Timo Lilja April 28, 2011 Timo Lilja () Static WCET Analysis: Methods and Tools April 28, 2011 1 / 23 1 Methods 2 Tools 3 Summary 4 References Timo Lilja () Static

More information

Introduction. CS3026 Operating Systems Lecture 01

Introduction. CS3026 Operating Systems Lecture 01 Introduction CS3026 Operating Systems Lecture 01 One or more CPUs Device controllers (I/O modules) Memory Bus Operating system? Computer System What is an Operating System An Operating System is a program

More information

1. Background. 2. Demand Paging

1. Background. 2. Demand Paging COSC4740-01 Operating Systems Design, Fall 2001, Byunggu Yu Chapter 10 Virtual Memory 1. Background PROBLEM: The entire process must be loaded into the memory to execute limits the size of a process (it

More information

director executor user program user program signal, breakpoint function call communication channel client library directing server

director executor user program user program signal, breakpoint function call communication channel client library directing server (appeared in Computing Systems, Vol. 8, 2, pp.107-134, MIT Press, Spring 1995.) The Dynascope Directing Server: Design and Implementation 1 Rok Sosic School of Computing and Information Technology Grith

More information

For The following Exercises, mark the answers True and False

For The following Exercises, mark the answers True and False 1 For The following Exercises, mark the answers True and False 1. An operating system is an example of application software. False 2. 3. 4. 6. 7. 9. 10. 12. 13. 14. 15. 16. 17. 18. An operating system

More information

Swapping. Operating Systems I. Swapping. Motivation. Paging Implementation. Demand Paging. Active processes use more physical memory than system has

Swapping. Operating Systems I. Swapping. Motivation. Paging Implementation. Demand Paging. Active processes use more physical memory than system has Swapping Active processes use more physical memory than system has Operating Systems I Address Binding can be fixed or relocatable at runtime Swap out P P Virtual Memory OS Backing Store (Swap Space) Main

More information

Last Class: Demand Paged Virtual Memory

Last Class: Demand Paged Virtual Memory Last Class: Demand Paged Virtual Memory Benefits of demand paging: Virtual address space can be larger than physical address space. Processes can run without being fully loaded into memory. Processes start

More information

CS533 Concepts of Operating Systems. Jonathan Walpole

CS533 Concepts of Operating Systems. Jonathan Walpole CS533 Concepts of Operating Systems Jonathan Walpole Improving IPC by Kernel Design & The Performance of Micro- Kernel Based Systems The IPC Dilemma IPC is very import in µ-kernel design - Increases modularity,

More information

Optimistic Shared Memory Dependence Tracing

Optimistic Shared Memory Dependence Tracing Optimistic Shared Memory Dependence Tracing Yanyan Jiang1, Du Li2, Chang Xu1, Xiaoxing Ma1 and Jian Lu1 Nanjing University 2 Carnegie Mellon University 1 powered by Understanding Non-determinism Concurrent

More information

Preemptive, Low Latency Datacenter Scheduling via Lightweight Virtualization

Preemptive, Low Latency Datacenter Scheduling via Lightweight Virtualization Preemptive, Low Latency Datacenter Scheduling via Lightweight Virtualization Wei Chen, Jia Rao*, and Xiaobo Zhou University of Colorado, Colorado Springs * University of Texas at Arlington Data Center

More information

Memory Management Outline. Operating Systems. Motivation. Paging Implementation. Accessing Invalid Pages. Performance of Demand Paging

Memory Management Outline. Operating Systems. Motivation. Paging Implementation. Accessing Invalid Pages. Performance of Demand Paging Memory Management Outline Operating Systems Processes (done) Memory Management Basic (done) Paging (done) Virtual memory Virtual Memory (Chapter.) Motivation Logical address space larger than physical

More information

Memory Management. Reading: Silberschatz chapter 9 Reading: Stallings. chapter 7 EEL 358

Memory Management. Reading: Silberschatz chapter 9 Reading: Stallings. chapter 7 EEL 358 Memory Management Reading: Silberschatz chapter 9 Reading: Stallings chapter 7 1 Outline Background Issues in Memory Management Logical Vs Physical address, MMU Dynamic Loading Memory Partitioning Placement

More information

Chapter 9: Virtual Memory

Chapter 9: Virtual Memory Chapter 9: Virtual Memory Silberschatz, Galvin and Gagne 2013 Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating

More information

Perform page replacement. (Fig 8.8 [Stal05])

Perform page replacement. (Fig 8.8 [Stal05]) Virtual memory Operations and policies Chapters 3.4. 3.7 1 Policies and methods Fetch policy (Noutopolitiikka) When to load page to memory? Placement policy (Sijoituspolitiikka ) Where to place the new

More information

Scope-based Method Cache Analysis

Scope-based Method Cache Analysis Scope-based Method Cache Analysis Benedikt Huber 1, Stefan Hepp 1, Martin Schoeberl 2 1 Vienna University of Technology 2 Technical University of Denmark 14th International Workshop on Worst-Case Execution

More information

Final Exam Preparation Questions

Final Exam Preparation Questions EECS 678 Spring 2013 Final Exam Preparation Questions 1 Chapter 6 1. What is a critical section? What are the three conditions to be ensured by any solution to the critical section problem? 2. The following

More information

CS 4410 Operating Systems. Review 1. Summer 2016 Cornell University

CS 4410 Operating Systems. Review 1. Summer 2016 Cornell University CS 4410 Operating Systems Review 1 Summer 2016 Cornell University 1 A modern computer system keyboard disks mouse printer monitor CPU Disk controller USB controller Graphics adapter memory OS device driver

More information

Chapter 9: Virtual Memory. Chapter 9: Virtual Memory. Objectives. Background. Virtual-address address Space

Chapter 9: Virtual Memory. Chapter 9: Virtual Memory. Objectives. Background. Virtual-address address Space Chapter 9: Virtual Memory Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory Other Considerations

More information

CIS Operating Systems Memory Management Address Translation for Paging. Professor Qiang Zeng Spring 2018

CIS Operating Systems Memory Management Address Translation for Paging. Professor Qiang Zeng Spring 2018 CIS 3207 - Operating Systems Memory Management Address Translation for Paging Professor Qiang Zeng Spring 2018 Previous class What is logical address? Who use it? Describes a location in the logical memory

More information

Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions

Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions *, Alessandro Biondi *, Geoffrey Nelissen, and Giorgio Buttazzo * * ReTiS Lab, Scuola Superiore Sant Anna, Pisa, Italy CISTER,

More information

Memory Management. Before We Begin. Process s Memory Address Space. Process Memory. CSE 120: Principles of Operating Systems.

Memory Management. Before We Begin. Process s Memory Address Space. Process Memory. CSE 120: Principles of Operating Systems. SE 12: Principles of Operating Systems Lecture 7 Memory Management February 1, 26 Prof. Joe Pasquale Department of omputer Science and Engineering University of alifornia, San Diego Before We Begin Read

More information

Operating Systems. Designed and Presented by Dr. Ayman Elshenawy Elsefy

Operating Systems. Designed and Presented by Dr. Ayman Elshenawy Elsefy Operating Systems Designed and Presented by Dr. Ayman Elshenawy Elsefy Dept. of Systems & Computer Eng.. AL-AZHAR University Website : eaymanelshenawy.wordpress.com Email : eaymanelshenawy@yahoo.com Reference

More information

Chapter 9: Virtual Memory

Chapter 9: Virtual Memory Chapter 9: Virtual Memory Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory Other Considerations

More information

Scheduling - Overview

Scheduling - Overview Scheduling - Overview Quick review of textbook scheduling Linux 2.4 scheduler implementation overview Linux 2.4 scheduler code Modified Linux 2.4 scheduler Linux 2.6 scheduler comments Possible Goals of

More information

D 5.3 Report on Compilation for Time-Predictability

D 5.3 Report on Compilation for Time-Predictability Project Number 288008 D 5.3 Report on Compilation for Time-Predictability Version 1.0 Final Public Distribution Vienna University of Technology, Technical University of Denmark, AbsInt Angewandte Informatik,

More information

Multiprocessor scheduling

Multiprocessor scheduling Chapter 10 Multiprocessor scheduling When a computer system contains multiple processors, a few new issues arise. Multiprocessor systems can be categorized into the following: Loosely coupled or distributed.

More information

Chapter 9: Virtual Memory

Chapter 9: Virtual Memory Chapter 9: Virtual Memory Chapter 9: Virtual Memory 9.1 Background 9.2 Demand Paging 9.3 Copy-on-Write 9.4 Page Replacement 9.5 Allocation of Frames 9.6 Thrashing 9.7 Memory-Mapped Files 9.8 Allocating

More information

Chapter 9: Virtual Memory. Operating System Concepts 9 th Edition

Chapter 9: Virtual Memory. Operating System Concepts 9 th Edition Chapter 9: Virtual Memory Silberschatz, Galvin and Gagne 2013 Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating

More information

Page 1. Multilevel Memories (Improving performance using a little cash )

Page 1. Multilevel Memories (Improving performance using a little cash ) Page 1 Multilevel Memories (Improving performance using a little cash ) 1 Page 2 CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency Latency

More information

Chapter 8 & Chapter 9 Main Memory & Virtual Memory

Chapter 8 & Chapter 9 Main Memory & Virtual Memory Chapter 8 & Chapter 9 Main Memory & Virtual Memory 1. Various ways of organizing memory hardware. 2. Memory-management techniques: 1. Paging 2. Segmentation. Introduction Memory consists of a large array

More information

Makuhari, Chiba 273, Japan Kista , Sweden. Penny system [2] can then exploit the parallelism implicitly

Makuhari, Chiba 273, Japan Kista , Sweden. Penny system [2] can then exploit the parallelism implicitly Dynamic Scheduling in an Implicit Parallel System Haruyasu Ueda Johan Montelius Institute of Social Information Science Fujitsu Laboratories Ltd. Swedish Institute of Computer Science Makuhari, Chiba 273,

More information

Agenda. EE 260: Introduction to Digital Design Memory. Naive Register File. Agenda. Memory Arrays: SRAM. Memory Arrays: Register File

Agenda. EE 260: Introduction to Digital Design Memory. Naive Register File. Agenda. Memory Arrays: SRAM. Memory Arrays: Register File EE 260: Introduction to Digital Design Technology Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa 2 Technology Naive Register File Write Read clk Decoder Read Write 3 4 Arrays:

More information

2 GHz = 500 picosec frequency. Vars declared outside of main() are in static. 2 # oset bits = block size Put starting arrow in FSM diagrams

2 GHz = 500 picosec frequency. Vars declared outside of main() are in static. 2 # oset bits = block size Put starting arrow in FSM diagrams CS 61C Fall 2011 Kenny Do Final cheat sheet Increment memory addresses by multiples of 4, since lw and sw are bytealigned When going from C to Mips, always use addu, addiu, and subu When saving stu into

More information

Processor. Processor. Processor L 1 L 1 L 2 L 2 L 1. Main Memory. Main Memory. Main Memory. Prefetch Buffer

Processor. Processor. Processor L 1 L 1 L 2 L 2 L 1. Main Memory. Main Memory. Main Memory. Prefetch Buffer I-sim: An Instruction Cache Simulator Donald O. Tanguay, Jr. Software and Systems Laboratory Hewlett-Packard Laboratories August 1991 Abstract As clock rates and instruction-level parallelism use increase,

More information

CSE 410 Final Exam 6/09/09. Suppose we have a memory and a direct-mapped cache with the following characteristics.

CSE 410 Final Exam 6/09/09. Suppose we have a memory and a direct-mapped cache with the following characteristics. Question 1. (10 points) (Caches) Suppose we have a memory and a direct-mapped cache with the following characteristics. Memory is byte addressable Memory addresses are 16 bits (i.e., the total memory size

More information

Main Memory and the CPU Cache

Main Memory and the CPU Cache Main Memory and the CPU Cache CPU cache Unrolled linked lists B Trees Our model of main memory and the cost of CPU operations has been intentionally simplistic The major focus has been on determining

More information

Operating System Concepts

Operating System Concepts Chapter 9: Virtual-Memory Management 9.1 Silberschatz, Galvin and Gagne 2005 Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped

More information

Your submitted proj3.c must compile and run on linprog as in the following example:

Your submitted proj3.c must compile and run on linprog as in the following example: CDA3101 Project 3: Cache Simulator Due 8/3 I. Purpose The purpose of this project is to exercise your understanding of caches of various sizes and configurations, as well as the write policies of write-through

More information

From Data to Effects Dependence Graphs: Source-to-Source Transformations for C

From Data to Effects Dependence Graphs: Source-to-Source Transformations for C From Data to Effects Dependence Graphs: Source-to-Source Transformations for C CPC 2015 Nelson Lossing 1 Pierre Guillou 1 Mehdi Amini 2 François Irigoin 1 1 firstname.lastname@mines-paristech.fr 2 mehdi@amini.fr

More information

ECE 3055: Final Exam

ECE 3055: Final Exam ECE 3055: Final Exam Instructions: You have 2 hours and 50 minutes to complete this quiz. The quiz is closed book and closed notes, except for one 8.5 x 11 sheet. No calculators are allowed. Multiple Choice

More information

A Statistical Model of Skewed-Associativity. Pierre Michaud March 2003

A Statistical Model of Skewed-Associativity. Pierre Michaud March 2003 A Statistical Model of Skewed-Associativity Pierre Michaud March 23 It s about microarchitected caches Type of cache Type of object Data/instructions cache Translation buffer Data/instructions block Page

More information

A Static Scheduling Heuristic for. Heterogeneous Processors. Hyunok Oh and Soonhoi Ha

A Static Scheduling Heuristic for. Heterogeneous Processors. Hyunok Oh and Soonhoi Ha 1 Static Scheduling Heuristic for Heterogeneous Processors Hyunok Oh and Soonhoi Ha The Department of omputer Engineering, Seoul National University, Seoul, 11-742, Korea: e-mail: foho,shag@comp.snu.ac.kr

More information

Optimizing Heap Data Management. on Software Managed Manycore Architectures. Jinn-Pean Lin

Optimizing Heap Data Management. on Software Managed Manycore Architectures. Jinn-Pean Lin Optimizing Heap Data Management on Software Managed Manycore Architectures by Jinn-Pean Lin A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science Approved June

More information

Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi

Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi Lecture - 13 Virtual memory and memory management unit In the last class, we had discussed

More information

Code Factoring in GCC

Code Factoring in GCC ode Factoring in ábor Lóki, Ákos Kiss, Judit Jász, and Árpád eszédes epartment of Software ngineering Institute of Informatics University of Szeged, ungary {loki,akiss,jasy,beszedes}@inf.u-szeged.hu bstract

More information

Scalable Cache Coherent Systems Scalable distributed shared memory machines Assumptions:

Scalable Cache Coherent Systems Scalable distributed shared memory machines Assumptions: Scalable ache oherent Systems Scalable distributed shared memory machines ssumptions: rocessor-ache-memory nodes connected by scalable network. Distributed shared physical address space. ommunication assist

More information

Levels in memory hierarchy

Levels in memory hierarchy CS1C Cache Memory Lecture 1 March 1, 1999 Dave Patterson (http.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs1c/schedule.html Review 1/: Memory Hierarchy Pyramid Upper Levels in memory hierarchy

More information

Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses

Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses Bekim Cilku, Roland Kammerer, and Peter Puschner Institute of Computer Engineering Vienna University of Technology A0 Wien, Austria

More information

Input and Output = Communication. What is computation? Hardware Thread (CPU core) Transforming state

Input and Output = Communication. What is computation? Hardware Thread (CPU core) Transforming state What is computation? Input and Output = Communication Input State Output i s F(s,i) (s,o) o s There are many different types of IO (Input/Output) What constitutes IO is context dependent Obvious forms

More information

Performance analysis of the static use of locking caches.

Performance analysis of the static use of locking caches. Performance analysis of the static use of locking caches. A. MARTÍ CAMPOY, A. PERLES, S. SÁEZ, J.V. BUSQUETS-MATAIX Departamento de Informática de Sistemas y Computadores Universidad Politécnica de Valencia

More information

Module 4: Index Structures Lecture 13: Index structure. The Lecture Contains: Index structure. Binary search tree (BST) B-tree. B+-tree.

Module 4: Index Structures Lecture 13: Index structure. The Lecture Contains: Index structure. Binary search tree (BST) B-tree. B+-tree. The Lecture Contains: Index structure Binary search tree (BST) B-tree B+-tree Order file:///c /Documents%20and%20Settings/iitkrana1/My%20Documents/Google%20Talk%20Received%20Files/ist_data/lecture13/13_1.htm[6/14/2012

More information

CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II

CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!

More information

To appear in the IEEE Transactions on Computers.

To appear in the IEEE Transactions on Computers. To appear in the IEEE Transactions on Computers. Analysis of Cache-related Preemption Delay in Fixed-priority Preemptive Scheduling Chang-Gun Lee y Joosun Hahn y Yang-Min Seo z Sang Lyul Min y Rhan Ha

More information

Page Replacement Chap 21, 22. Dongkun Shin, SKKU

Page Replacement Chap 21, 22. Dongkun Shin, SKKU Page Replacement Chap 21, 22 1 Virtual Memory Concept Virtual memory Concept A technique that allows the execution of processes that are not completely in memory Partition each user s program into multiple

More information

Page replacement algorithms OS

Page replacement algorithms OS Page replacement algorithms OS 2007-08 1 When a page fault occurs OS has to choose a page to evict from memory If the page has been modified, the OS has to schedule a disk write of the page The page just

More information

Heap Management. Heap Allocation

Heap Management. Heap Allocation Heap Management Heap Allocation A very flexible storage allocation mechanism is heap allocation. Any number of data objects can be allocated and freed in a memory pool, called a heap. Heap allocation is

More information

Memory Management. Memory Management. G53OPS: Operating Systems. Memory Management Monoprogramming 11/27/2008. Graham Kendall.

Memory Management. Memory Management. G53OPS: Operating Systems. Memory Management Monoprogramming 11/27/2008. Graham Kendall. Memory Management Memory Management Introduction Graham Kendall Memory Management consists of many tasks, including Being aware of what parts of the memory are in use and which parts are not Allocating

More information

Eliminating Stack Overflow by Abstract Interpretation

Eliminating Stack Overflow by Abstract Interpretation Eliminating Stack Overflow by Abstract Interpretation Paper by John Regehr, Alastair Reid, and Kirk Webb ACM Transactions on Embedded Computing Systems, Nov 005 Truong Nghiem nghiem@seas.upenn.edu Outline

More information