CodeWarrior Development Studio for StarCore 3900FP DSP v Release Notes

Transcription

1 Freescale Semiconductor Document Number: CW_SC_3900FP_v Release Notes Rev. 1.3, 3/2015 CodeWarrior Development Studio for StarCore 3900FP DSP v Release Notes Release Description Release of CodeWarrior Development Studio for StarCore sc3900fp DSP provides MAPLE firmware A28_1, SDOS support, L1 defense enhancements and workaround for errata A , and improvements in IDE, debugger and build tools. Contents Release Description... 1 Release Content MAPLE Firmware MAPLE3W A28_1 Firmware Release MAPLE3LW A28_1 Firmware Release SmartDSP OS Driver Features...4 Demos Performance Important Notes Known Issues and Limitations Compatibility Build Tools IDE Debugger Documentation License, copyright System requirements Getting Started Comprehensive User Guides Known Issues and Limitations Contact Information User Forum and FAQ Contacting Freescale Release Quality Freescale Semiconductor, Inc. All rights reserved.

2 Release Content 1.1 MAPLE Firmware This is the most up to date reference manual for external link for customers: Files available: MAPLE-B3RM_RevE_B4860Rev2_A28.pdf MAPLE-B3RM_RevE_B4420Rev2_A28.pdf MAPLE3W A28_1 Firmware Release The init parameter called timer_period, should not be of small values, thus overloading the MAPLE riscs with the parse ucode. This release includes the following PEs: eftpe2 (x2) F1 verified. CRCPE F1 verified. CGPE F1 verified. CRPE ULB2 is F1 verified CRPE DL2 is F1 verified. TCPE F1 verified. PUFFT2_EDF F1 Verified (See exceptions below). Code Size: 44KB PUFFT2_EDF Alternative BW support (ALT_UBW) MAPLE3LW A28_1 Firmware Release The init parameter called timer_period should not be of small values, thus overloading the MAPLE riscs with the parse ucode. This release includes the following PEs: eftpe2 (x3) F1 verified. DEPE F2 verified (exception below). CRCPE Fully verified. etvpe2 Fully verified. PDSCH2 EDF F1 verified (exception below). PUFFT2_EDF F1 verified (See exceptions below). PUSCH2_EDF F1 verified for a limited feature list (see below) Code Size: 156KB Freescale Semiconductor CW_SC_3900FP_V Release Notes, Rev

3 EQPE2 Non-Interpolation mode in standalone EQPE enabled EQPE2 features are according to PUSCH2-EDF feature list MMSE Repeat mode in standalone EQPE enabled PDSCH2 EDF epdcch Release 11 Supported features: o DNOSD DNOS disable option to mask the DNOS interrupt. o UE-RS Scrambling INIT upgrade to support Release 11 modifications. o Alternative bandwidth supported. o EFSEL indicates number of eftpes instead of eftpe ID o NNOSE/MMTID error handling in sync mode o Re-configuration o CSI per BD o Dynamic POS-RS o Late PCR o Multiple Sectors per MAPLE Instance. o RB mapping is compatible with the RM. o Pre-IFFT Multiplication Enable. o Post-IFFT Multiplication Enable. o External Padding Pattern. o Hybrid MBSFN (Normal CP with MBSFN_EN=1) o SSFC=9 for rel 11 o Update SSFC=7 for rel 11 o PDPE Input code words debug dump o PDPE Output debug dump o Trace. o Padding. o PH. o Number of control OFDM symbols indication (NC). o Number of data OFDM symbols indication (ND). o One general SYNC_FLOW bit. o One general IFFT_DIS bit. o Up to 100 users per sector can use UE Specific Reference Signals. o Beam Forming. o SYNC Mode using 2<=MNOS<=15 & NOS o PBFIX. Not supported features: o 7.5KHz o In case of multi sector configuration, PDSCH may not meet throughput with MNOS=2 and mixed NCP/ECP o In case of multi sector configuration, PDSCH may not meet throughput with external padding with MNOS<4 o Latency optimizations o Per user CSI o CSRS priorities for COMP o CFI=0 o R-PDCCH o CS-RS for Rel 11 DL-COMP o Cinit per UE specific RS o Maskable NOS decrement 3 CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

4 PUFFT_EDF F1 functionality. The Input buffer base address (parameter MPUFFT<s>AIBA<x> see section in RM) should be aligned to 16 Byte. Alternative BW support (ALT_UBW) Functional per RM 1.2 SmartDSP OS SmartDSP OS R libraries are compiled with option Wmwfe-error Treat warnings as errors Driver Features CPRI Ethernet errata A workaround SmartDSP OS R introduces support for B4860/B4420 CPRI errata (A ) workaround implementation. The solution is intended for users who need to send Ethernet packets with 7 PREAMBLE bytes as required in the Ethernet standard. The CPRI Ethernet hardware in B4 generates 3 PREAMBLE bytes. The CPRI Ethernet workaround support is a software implementation replacing the CPRI Ethernet hardware transmit data path. A flag was added to CPRI Ethernet initialization parameters structure to allow application to switch the CPRI Ethernet TX data path for enabling the solution. Note: the solution executes 4B5B and CRC encodings, which result in performance impact compared to the regular HW non-wa mode. Application: Using Ethernet workaround mode requires further application adjustments, all of which are demonstrated in the introduced demo. The most notable are (refer to user guide for more information): - The block size provided as 1st parameter in function osmempartcreate() must be enlarged by 25% + 20 bytes. This is to ensure space for drivers internal operation. - Since the WA solution based on employing the VSS transmit activity for Ethernet data, the driver allocates internally a VSS transmit buffer. The application must provide memory type (local, shared, etc ) and buffer attributes (cacheable, write back, guarded and more). - The user shall provide a value_m value. The meaning of value_m is detailed in the user guide. In general, the bigger value_m is, the bigger the latency of packets transmission, but also the smaller the interrupts frequency. VSS: The CPRI VSS TX mechanism is used by the driver for Ethernet packet transmission in the workaround mode (refer to errata description). The application can use VSS transmission in parallel with the Ethernet, even when the Ethernet TX is configured to work in the workaround mode. Only VSS transmit data path is impacted by the workaround implementation. There are limitations and modifications for VSS, main of which are (refer to user guide for more information): - The VSS TX threshold is not set by the application, but relates to value_m. - In VSS TX callback the VSS TX buffer to fill is not continuous but divided into equal sized segments. These segments shall be fetched and filled using the following SIO API functions ossiobufferget() and ossiobufferput(). - Pre-filling of the TX buffer, before the VSS TX enable is possible via a dedicated new SIO control command for VSS. It is also demonstrated in demo. Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

5 SIO: SIO mechanism was modified to allow usage of functions ossiobufferget() and ossiobufferput() in VSS TX callback when working in Ethernet workaround mode. Please refer to Known Issues and limitations MAPLE3 L1 Defense Support SmartDSP OS R introduces L1 Defense flow enhancement enabling reset of MAPLE before MAPLE initialization. New status bits were added by μcode to support this flow, enabling SmartDSP OS to determine if the driver should issue MAPLE reset during the L1 Defense initialization. This enables safely issuing L1 Defense warm reset not knowing the MAPLE state. MAPLE3 Firmware Update SmartDSP OS R is released with B4860/B4420 MAPLE3LW/MAPLE3W Firmware Release A28_1. The following new features were added to support the new μcode version: - EQPE standalone with repeat mode. - PDSCH2 EDF Supports epdcch (Release 11): o New flag added, PDSCH_BD_EXTND_EN, to allow for a BD extension. The extension should receive the number of imported types and a pointer to the data structure. For reference, see maple_pdsch_job_extension_t or the MAPLE PDSCH Demo. o API Change When the UE specific reference signal is targeting antenna port 5 The UE RS headers should contain the Cell ID see DMRSID for details. - eftpe now supports 32 jobs in one batch. 5 CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

6 Demos CPRI This single core demo shows the usage of the CPRI workaround mode. The demo executes multiple CPRI units, for each Ethernet is used in workaround mode as well as VSS. The demo verifies received data for both Ethernet and VSS and is located in: SmartDSP\demos\starcore\b4860\cpri_ethernet_workaround_vss_and_ethernet Performance SmartDSP OS R kernel performance figures are shown in Table 1. The mode of calculation was such that each measurement was taken 5 times; once with cold instruction caches and the other without. The WCS (worst case scenario) is the cold cache result. The BCS (best case scenario) is the best of the results. Table 1 SmartDSP B4860 and B4420 Performance Figures prolog/epilog from prolog/epilog from prolog/epilog from Task High priority from low priority Epilog Prolog Epilog Prolog Epilog Prolog Epilog Prolog B4860 B4420 WCS BCS AVG WCS BCS AVG High priority Task Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

7 Task from low priority Task Low priority from high priority from Task Epilog Task Prolog Epilog Prolog Epilog Prolog Important Notes Note on B4860/B4420 rev2 cacheable spinlocks SmartDSP OS R contains B4860/B4420 rev2.2 support for cacheable spinlocks with light barriers for cacheable memory. Therefore, os_shared_data_descriptor inside B4860/B4420 rev2 linker files must be with cacheable coherent attributes. Note on ISR Stack size: ISR stack size is defined in os_config.h and not in the linker file (as opposed to the CodeWarrior stationary configuration) #define OS_STACK_SIZE <size> Note on System Stack mapping: The user MUST take care to map the system stack to the virtual address 0xBB and to provide the actual physical mapping. Towards this, the default lcf has the symbol _ARCH_SYS_STACK_VIRT_BASE declared. The relevant portion of the core s private lcf is as follows: unit private (*) { MEMORY { os_system_stack_descriptor ("rw"): org = _ARCH_SYS_STACK_VIRT_BASE; os_background_stack_descriptor ("rw"): org = _ARCH_BCK_STACK_VIRT_BASE; } SECTIONS { descriptor_os_system_stack { 7 CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

8 } }.os_system_stack } > os_system_stack_descriptor; descriptor_os_background_stack {.os_background_stack } > os_background_stack_descriptor; address_translation (*) { os_system_stack_descriptor (0, ((STACK_DATA_MMU_DEF_HIGH << 32) STACK_DATA_MMU_DEF_LOW)) : LOCAL_DDR0, AFTER(local_data_ddr0_descriptor); os_background_stack_descriptor (0, ((STACK_DATA_MMU_DEF_HIGH << 32) STACK_DATA_MMU_DEF_LOW)) : LOCAL_DDR0, AFTER(os_system_stack_descriptor); } // Stack setting _StackStartPhys = physical_address("stackstart"); Note on projects All projects must add the relevant SoC (B4860/B4420) as well as the relevant core (SC3900) as compiler preprocessors Known Issues and Limitations CPRI Ethernet errata workaround Scenario in which VSS and Ethernet data types of the same CPRI unit are owned by different cores is not tested. Debug Print L1 Defense When warm reset is invoked, if a core has begun sending a debug print message to NEXUS, messages from the other cores are discarded in the C-NPC until this core has completed sending the message (which happens after returning from reset). B4420 Level 0 CPRI Reconfiguration B4420 level 0 reconfiguration is supported for CPRI IQ and VSS usage only (Ethernet and HDLC are not yet supported). DPAA L1 defense support L1 defense SmartDSP OS module currently supports using DPAA integration scenario only. This means that Linux is initializing QMAN and BMAN and is allocating portals for DSP usage. Standalone L1 defense support is planned to be added in future SmartDSP OS releases. CPRI HDLC CRC error A CRC error and packed discarded errors are sometimes received from CPRI hardware upon receive of first HDLC. Following frames are received correctly and without error. Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

9 While the issue needs to be checked, SmartDSP OS CPRI HDLC demo ignores this first RX callback in case it contains these errors. MBECC and BD UNDDERRUN errors are disabled in HDLC demo, since those errors are being invoked frequently, without impact on transmitted or received data. B4420 CPRI QDS Cross matrix configuration B4420 QDS Cross matrix configuration script (external to SmartDSP OS) seems to be not configuring the CPRI lanes connections properly. As a result, it is not possible to test B4420 CPRI tests using optical connection (SFP) on the board. For this reason, CPRI auxiliary demo and auto negotiation demo were not tested on B4420 (so does not contain B4420 targets). In following releases, after connectivity is corrected, B4420 targets will be tested and added to the demos. CPRI units connection with cross cable on single SoC When connecting 2 CPRI units on the same SoC using a cross cable (optical), only when the 2 CPRI units are configured as CPRI masters, the data is exchanged correctly. If configuring one unit as slave (theoretically the correct configuration), data is corrupted or NULL. This issue impacts CPRI full negotiation demo, which is using cross cable. This will be fixed in following SmartDSP OS releases Compatibility Silicon version and configuration SmartDSP OS R supports B4860/B4420 rev2.2 all tests were tested on B4860 rev2.2 silicon on QDS boards. B4860/B4420 tests were run using core frequency 1.2GHz, DDR frequency 1.86GHz, MAPLE frequency 600MHz, platform frequency 667MHz. The B4860 reset configuration word (RCW) used for testing is: 140E0018 0F A8D0000 A000A400 FC A B1F The B4420 reset configuration word (RCW) used for testing is: 140C0018 0F A9E FC A b CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

10 Memory map The DSP memory map used by R is as following (B4860/B4420): Memory region Virtual address Physical address Size DSP DDR (DDR controller 1) 0x > 0xFFFFFFFF CCSRBAR 0x7F > 0x7FFFFFFF MAPLE MBUS 0x > 0x79BFFFF M3 memory (if used) 0x7D > 0x7D07FFFF DSP cluster registers (Bank0) Shared control structure (used by PA and DSP) 0xFEC > 0xFEC3FFFF 0xFFF > 0xFFFFFFFF 0x > 0xFFFFFFFF 0xFFE > 0xFFEFFFFFF 0xFE > 0xFE0 BFFFF 0xC > 0xC4007FFFF 0x (2GB) 0x x xFFF > 0xFFFFFFFF PA DDR (DDR2 controller ) (PA access only) 0x > 0x7FFFFFFF PA shared DDR 0x x6EFFFFFF SC shared DDR 0x6F x6FFFFFFF CodeWarrior (PA configurable) (PA configurable) 0x * 3 = 0xc00000) Up to 0x80000 (512KB) 0x (max size) 0x (2GB) 0xF (240MB max size) 0x (16MB max size) SmartDSP OS R libraries and applications were compiled and tested with CodeWarrior for StarCore , Build 421. Linux BSP SmartDSP OS R is compatible with the B4860 QDS Linux BSP version QORIQ SDK Build Tools New version of build tools v adds the following features: Modulo addressing vectorization Predication improvements Enhance predicate usage in code reordering Support for rename linker directive when building self contained libraries Generate inline debug information for inline assembly functions Elf2xx tool generates MASK register information Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

11 1. Performance Report Table 2 Build Tools Performance Improvements vs. CW Benchmark Average Improvement Max. Improvement Max. Degradation DSP 1% 10% 1.5% Control Code 0% 0% 0% 2. Compile time report Table 3 Compile Time Report Benchmark Total Compile Time (s) Average Time (s) LTE Compile Files compiled in more than 20s MatrixInverse_B4860_QDS/ SBL1_ULSPK_MatrixInverse_8x8_BackSubst.c MatrixInverseCholesky_B4860_QDS/ SBL1_ULSPK_MatInvChol_8x8_2x.c PDSCH_AL_B4860_rev2_ifft_dis_lib/ SBL1_PDSCH_AL_Parser.c PDSCH_AL_B4860_rev2_lib/SBL1_PDSCH_AL_Parser.c, SBL1_PDSCH_MAL_Late.c pusch_config_0_rev2_lib/ SBL1_PUSCH_AL.c pusch_config_1_rev2_lib/ SBL1_PUSCH_AL.c MapleFWK_DL_B4860_QDS_SY/ SBL1_PDSCH_REF_Background_FWK_MAPLE_Padding.c PDSCH_RC_B4860_QDS_REV2_SYNC/SBL1_PDSCH_Tasks.c SDOS pusch_simple_b4860/data_buffers.c Compile time benchmarks were run on Intel Core i CPU@2.60 Ghz, RAM 4GB, OS win7 32bit, HDD 7200 RPM 1.4 IDE New version of the IDE adds the following features: - Option Preprocess All Source Files to generate preprocessed files for all source files in the project - Support to index inside the binary files. This can be enabled from Windows -> Preferences -> C/C++ -> Indexer -> check index sources from binary files - Executable file can be correctly expanded after Export/Import debug project. 11 CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

12 1.5 Debugger New version of the debugger adds the following feature: - Disable Searches again cache lines for a certain string icon if no previous search was made in the cache viewer. 1.6 Documentation The documentation roadmap is updated for the following cheat sheet short description: - Exporting Trace, Performance, Critical Code, and Call Tree Data - Importing Offline Trace Data - Multicore Tracing and Profiling on B4860 Target The Targeting manual has updates in the following sections: Processor Page Configuring Connections The SC3000 Linker Reference Manual has the following updates: - New section added How to use KEEP Directive - Update table 9-1 Command line options for warnings-as-errors option The Tracing and Analysis User Guide has the following changes: - Chapter 2 is updated with O0 optimization level impact - Miscellaneous tab page information is added on the Debug Configuration Dialog Box Trace and Profiling Tab in sections Simulation Profiling and Hardware Profiling The SDOS OS Concept User Guide has a new section CPRI Ethernet Errata A Workaround. License, copyright The license key was updated in CodeWarrior for StarCore 3900FP DSP v release. System requirements Recommended configurations: - 3GHz Intel Pentium P4 processor or better. Dual-core processor preferable. - Microsoft Windows Vista, Windows 7, Windows Server 2012 R2-2GB RAM (Experience on machines with 1GB RAM is significantly reduced) GB free disk space Note: 500MB of free space is required on the OS drive, regardless of the free space available on the destination drive. Getting Started The Getting Started Guide for StarCore DSPs.pdf provides instructions on how to install the product, configure B4 QDS boards, and how to work with projects. To install the CodeWarrior software, perform the following steps: 1. Run the installer - the install wizard appears. Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

13 2. Follow the wizard's on-screen instructions to install the CodeWarrior software. 3. When installation completes, the InstallShield Wizard Completed page appears. 4. Check the Display Documentation checkbox. 5. Click Finish. The SC folder contains several quick start guides for the product: Eclipse Quick Reference Card.pdf Ethernet TAP Quick Start.pdf Getting Started Guide for StarCore DSPs.pdf Quick Start for StarCore DSPs.pdf Service Pack Updater Quick Start.pdf Comprehensive User Guides The complete product documentation can be found in the folder SC\Help\PDF and contains the following documents: Build Tools Message Reference Manual.pdf CodeWarrior Common Features Guide.pdf CodeWarrior TAP Users Guide.pdf Ethernet TAP Users Guide.pdf EWL C Reference.pdf EWL C++ Reference.pdf Gigabit TAP Users Guide.pdf SmartDSP OS API Reference Manual.pdf SmartDSP OS User Guide.pdf StarCore ABI Reference Manual.pdf StarCore Assembler User Guide.pdf StarCore C-C++ Compiler User Guide.pdf StarCore FAQ Guide.pdf StarCore SC3000 Linker User Guide.pdf StarCore Simulator User Guide.pdf Targeting StarCore DSPs.pdf Tracing and Analysis Users Guide.pdf USB TAP Users Guide.pdf 13 CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

14 Known Issues and Limitations Known Issue Abstract Workaround Run Control ENGR Error running core after making trace configuration Set JTAG clock speed at 4000 khz ENGR ENGR ENGR ENGR ENGR Simulator Newly introduced "maple_eqpe" demo not running successfully on simulator on "Debug" configuration Updated "maple_pusch" demo not running successfully on simulator on some configurations [SC10.8.2][SDOS5.14] maple_reset demo fails [SC10.8.3][SDOS5.15] maple_pdsch fails with build config Debug & Release Software Analysis [10.8.1][Multicore trace] Continuous trace does not work multicore ENGR Trace collection does not work on B4420 when using Aurora link N/A ENGR ENGR [10.8.2][B4860][64bits][CWTAP/ETAP/GTAP] Error at resume after applying profiling trace configuration [10.8.2][B4860][Critical Code] Out of memory at generating code coverage use the configuration "EQPE_B Release" instead use the "b4860 pusch shared channel" configuration instead. use the B4420 ISS target, do not define SIMULATOR, change TEST_NUM_OF_ITERATIONS to 2 instead of 200 in file ap_config.h Please use either the "b4860 pdsch performance" or the "b4860 pdsch sync debug" configuration instead. Increase DDR trace buffer size and set trace collection mode to one buffer to workaround this issue. In this way there should be room for all trace messages generated by cores in trace buffer Set JTAG clock speed at 4000 khz 0. Use default heap setting as provided by CW. 1. Import raw trace into new workspace. 2. Close CW. Open CW. 3. Open Software Analysis view. Configure results -> Exclude Symbols and exclude symbols from some of used libraries(it minimizes memory usage in saving data step). Click on Critical Code. Please see the SDOS chapter on the list of additional limitations. Contact Information User Forum and FAQ After looking through these release notes, and the documentation that comes with the installation of CodeWarrior, the next best place to look for answers to your questions is the online user forums located at Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

15 Please check: - CodeWarrior for StarCore DSPs forum for issues related to CodeWarrior development tools. The Frequently Asked Questions about CodeWarrior for StarCore DSP are posted here. - StarCore DSPs forum for issues related to the silicon and hardware platforms. The forums provide a great way to learn by seeing the questions and answers posted by other users. Of course, you can post your own questions and responses as well. Contacting Freescale Finally, if you still have questions not addressed in the release notes, or wants to provide feedback, please use the Freescale online support web page. To use this page, follow these steps: 1. In a web browser, go to Freescale s Technical Support web page appears. 2. On this page, click the Create service request online link. The New Service Request Category/Topic page appears. 3. From the Category dropdown menu, select Technical Request. 4. From the Topic dropdown menu, select CodeWarrior (or other appropriate topic). 5. Click Next. The New Service Request SR Details page appears. 6. In this page, enter the requested information. At a minimum, enter information in each field marked by an *. 7. Click Submit. If you are already logged in, the Service Request Confirmation page appears. Go to the last step. If you are not already logged in, the Log-in page appears. 8. If you are a registered member, login with your user name and password. The Service Request Confirmation page appears. Go to the last step. 9. If you have not yet registered, a. If you want to become registered member, click Register Now and complete the registration process. The Service Request Confirmation page appears. b. If you do not want to register, supply your contact information in the I do not want to register - Provide contact information form and click Submit. 10. Click Done. The Service Request Confirmation page appears. Your service request is submitted. 15 CW_SC_3900FP_v Release Notes, Rev. 1.3 Freescale Semiconductor

16 Release Quality This list includes the issues reported by external customers that are now fixed: ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR ENGR SmartDSP OS CPRI BD filling macros CPRI_ETHERNET_BD_BUFFER_SET and CPRI_HDLC_BD_BUFFER_SET is not correctly defined or used CPRI driver, debug target, parameters assertion function is not multicore safe SDOS CPRI driver, debug target, parameters assertion function cprireconfigurationassertparameters(...) lacks VSS assertion CPRI_CONFIG[10] bit is no longer in Reference Manual Enable CPRI Ethernet errata w/a (A ) Build Tools Linker fails silently when multiple definitions exist in a self contained library CW StarCore compiler optimizes mod operation wrongly Linker options which should return failure on link do not attribute ( aligned (n)) doesn't work in CW Alignment not correctly calculated. fsscc.exe crash LLT error while parsing.appli file IDE Export/Import Debug project does not work Documentation [Cheat Sheets] "Multicore Tracing and Profiling on B4860 Target" need some description for Trace Configuration Cheat Sheets] Offline Trace Data file type for HW and SIM need to be updated in "Import offline Trace Data" Trace and Profile tab describe should be update for both SIM trace and HW trace Section " File Coverage Tab" of Critical Code data must be removed Some figures and NOTEs need to be updated in "Tracing and Analysis Users Guide.pdf" [SC ][Documentations Roadmap] Cheat Sheets' description in Documentations Roadmap need to be updated for some SA features Freescale Semiconductor CW_SC_3900FP_v Release Notes, Rev

17 How to Reach Us: Home Page: Web Support: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. Freescale, the Freescale logo, CodeWarrior, QorIQ, QorIQ Qonverge, and StarCore are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org Freescale Semiconductor, Inc. All rights reserved. Document Number: CW_SC_3900FP_v Rev /2015