Methode Electronics. DM7041-X 1000BASE-T Small Form Factor Pluggable BDT Bus Interface. ISO 9001 Certified

Transcription

1 DM7041-X 1000BASE-T Small Form Factor Pluggable BDT Bus Interface

2 BI-Directional Data Transfer Bus The DM7041 SFP x RJ45 transceiver supports a bi-directional data transfer bus (BDT) to access the PHY registers and Serial ID. The device address of the PHY is X (1,0,1,0,A2,A1,A0,R/W) and the device address of the Serial ID is X (1,0,1,0,0,0,0,R/W). The BDT operates with a serial data line (SDA) and a serial clock line (SCL). The MOD_DEF[2:1] pins of the SFP plug are utilized as the bus interface connections with MOD_DEF2 being the data and MOD_DEF1 being the clock. SFP /400 Description Device Pins Kbps Mode MOD_DEF2 SDA Serial data line MOD_DEF1 SCL Serial clock line Table 1 MOD_DEF2 is a bi-directional line, while MOD_DEF1 is not. Both of the bus interface lines are high when the bus is inactive. Table 1 indicates the pin mapping of the transceiver to the BDT. The DM7041 transceiver BDT features are: 7-bit device address/8-bit data transfers 100 Kbps mode 400 Kbps mode Bus Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a START or STOP condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a START condition which must precede any other command. STOP CONDITION: A low-to-high transition of SDA with SCL high is a STOP condition. After a read sequence, the stop command will place the addressed device in standby mode. NOWLEDGE: All addresses and data words are serially transmitted to and from the addressed device in 8-bit words. The addressed device sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. Device Addressing The PHY and the Serial ID require an 8-bit device address word following a START condition to enable either device for read or write operations. The device addresses for the PHY and Serial ID are listed in Table 2. DEVICE ADDRESS PHY X Serial ID X X = 1 for READ, 0 for Write Table 2

3 Write Operations RANDOM WRITE: A write operation requires a register address following the device address and acknowledgment. Upon receipt of this address, the PHY will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the PHY will output a zero and the addressing device must terminate the write sequence with a STOP condition. A complete byte write operation includes the upper and lower bytes. The upper byte is written first, followed by the lower byte. Note that the Serial ID is READ ONLY and will not respond to write operations SDA Line Start =W Register Address Upper Byte Stop TO PHY Start =W Register Address Lower Byte Stop FROM PHY SEQUENTIAL WRITE: A sequential write is started by a random address write. After the register address is received by the PHY, the PHY responds with an NOWLEDGE. The PHY generates an NOWLEDGE as long as the addressing device does not generate a STOP. In a sequential write, only even transfer of bytes is accepted by the PHY. If the last byte is odd, it is held internally by the PHY but is not written to the PHY register. SDA Line Start =W Register Address Upper Byte n Lower Byte n TO PHY Upper Byte n+1 Lower Byte n+1 Upper Byte n+x Lower Byte n+x Stop FROM PHY Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. You can read the PHY registers or the Serial ID simply by selecting their corresponding device address. CURRENT ADDRESS READ: The internal data word address counter, in each device, maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the power is maintained. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the addressed device, the current address data word is serially clocked out. The addressing device does not respond with an input zero but does generate a following STOP condition = PHY Start 1=R = ID Upper TO PHY or SERIAL ID SDA Line Stop Byte FROM PHY or SERIAL ID RANDOM READ: A random read requires a dummy byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the addressed device, the addressing device must generate another START condition. The addressing device now initiates a current address read by sending a device address with the read/write select bit high. The addressed device acknowledges the device address and serially clocks out the data word. The addressing device does not respond with a zero but does generate a following STOP condition. SDA Line = PHY Start 0=W = ID Register Address Start = PHY = ID 1=R Upper Byte Stop = PHY Start 0=W = ID Register Address Start = PHY = ID 1=R Lower Byte Stop TO PHY or SERIAL ID FROM PHY or SERIAL ID SEQUENTIAL READ: Sequential reads are initiated by either a current or a random address read. After the addressing device receives a data word, it responds with an NOWLEDGE. As long as the addressed device receives an NOWLEDGE, it will continue to increment the data word address and serially clock out sequential data words. The sequential read operation is terminated when the addressing device does not respond with a zero but does generate a following STOP condition = PHY SDA Line Start 0=W = ID Register Address = PHY Start 1=R = ID Upper Byte n Lower Byte n Upper Byte n+1 Lower Byte n+1 Upper Byte n+x Lower Byte n+x Stop TO PHY or SERIAL ID FROM PHY or SERIAL ID

4 Serial ID: Data Fields The table below lists the details of the information that is stored inside the Serial ID and can be read by accessing this device via the BDT. Data Address Field Size Field Name Field Description Field Value Value Description BASE ID FIELDS 0 1 Identifier Type of serial transceiver 03 SFP TRANSCEIVER 1 1 Ext. Identifier Extended identifier of type of serial transceiver 04 WITH SERIAL ID 2 1 Connector Code for connector type 00 UNSPECIFIED Transceiver Code for electronic or optical compatibility 00,00,00,08, 00,00,00, BASE-T 11 1 Encoding Code for serial encoding algorithm 01 8B10B ENCODING 12 1 BR, Nominal Nominal bit rate, units of 100Mbits/sec 0D 1.25 Gbps 13 1 Reserved 00 RESERVED 14 1 Length(9m) km Link length supported for 9/125 mm fiber, units of km 00 NA 15 1 Length (9m) Link length supported for 9/125 mm fiber, units of 100m 00 NA 16 1 Length (50m) Link length supported for 50/125 mm fiber, units of 10m 00 NA 17 1 Length (62.5m) Link length supported for 62.5/125 mm fiber,units of 10m 00 NA 18 1 Length (Copper) Link length supported for copper, units of meters METERS 19 1 Reserved 00 RESERVED Vendor name SFP transceiver vendor name (ASCII) 4D,65,74,68, 6F,64,65,20, 45,6C,65,63, 2E,20,20,20 METHODE ELEC (ASCII) 36 1 Reserved 01 PHY REG 2[15:8] Vendor OUI SFP transceiver vendor IEEE company ID 00,00,00 UNSPECIFIED 44,4D,37,30, Vendor PN 20,20,20,20 Part number provided by SFP transceiver vendor 34,31,20,20, DM7041 (ASCII) 20,20,20,20, (ASCII) Vendor rev Revision level for part number provided by vendor (ASCII) Reserved 41,0C,C CC_BASE Check code for Base ID Fields (addresses 0 to 62) VARIES EXTENDED ID FIELDS 42,20,20,20 Rev B PHY REG 2[7:0], PHY REG 3[15:8] PHY REG 3[7:0] Options Indicates which optional SFP signals are implemented 00,10 Tx DISABLE IMPLIMENTED 66 1 BR, max Upper bit rate margin, units of % BR, min Lower bit rate margin, units of % Vendor SN Serial number provided by vendor (ASCII) VARIES (ASCII) Date code Vendor s manufacturing date code VARIES YY-MM-DD-LOT# Reserved 00,00, CC_EXT Check code for the Extended ID Fields (addr. 64 to 94) VARIES VENDOR SPECIFIC ID FIELDS Read-only Vendor specific data Table 3

5 PHY Registers The BDT bus interface can be used to access the PHY registers for read and write operations. This allows the user to configure the device for modes of operation other than the default mode. In addition, it allows the user to configure the transceiver for special modes that facilitate system testing and diagnostics. The following is a partial list of the various possible modes of the transceiver. Table 4 is an exhaustive description of the applicable Phy registers. The following defaults are set on power up by a hardware reset. ANEG[3:0] = 1010 = Auto-Neg, advertise only 1000BASE-T full-duplex, preferred Master. HWCFG MODE[3:0] = 1000 = 1000BASE-X without Clock with 1000BASE-X Auto-Neg to copper (GBIC or SERDES mode). SERDES and SGMII Mode The Gigabit Ethernet Transceiver normally operates in SERDES mode. The SERDES interface supports 1000 Mbps operation only. In this mode, the copper side Auto-Negotiation results are sent to the MAC using 1000BASE-X Auto- Negotiation. For example, the link partner's abilities such as flow control and duplex are indicated to the MAC. The MAC, based on this information, will determine the mode of operation. Similarly, the 1000BASE-X Auto-Negotiation information received from the MAC is used by the Transceiver to control what abilities the Transceiver advertises. For example, if the MAC advertises only full-duplex, but the Transceiver is configured to advertise both full-duplex and half-duplex, the Transceiver only advertises full-duplex. The advertise register settings are not modified, although what is advertised on the line is now different. There is also a legacy SERDES mode that does not support 1000BASE-X Auto-Negotiation. The legacy mode is 1000BASE-X without 1000BASE-X Auto-Negotiation, and can be set by setting Register 27.3:0 HWCFG_MODE[3:0] bits to '1100'. Changing to this mode does not disable serial interface Auto-Negotiation. A register write to Register 20.3 is necessary when switching from SERDES mode to legacy SERDES mode. The Transceiver also supports the SGMII Rev. 1.5 interface to copper. This interface supports 10, 100, and 1000 Mbps modes of operation. The Transceiver does not need a TXCLK input as it recovers this clock from input data. The serial interface without clock is selected by setting Register 27.3:0 HWCFG_MODE[3:0] bits to '0100'. For SGMII mode, if the bypass logic brings up the fiber link, copper auto-negotiation will restart and advertise only gigabit speed. When the copper interface is running in 1000BASE-T mode, the serial 1.25 GHz SGMII encoding is identical to that found in 1000BASE-X. In 100BASE-TX and 10BASE-T modes, the SGMII interface still runs at 1.25 GHz using 1000BASE-X encoding. However, each byte of data in the packet is repeated 10 or 100 times, respectively. The synchronizing FIFOs are automatically enabled in these modes for both the transmit and receive paths. The SGMII interface implements a modified 1000BASE-X Auto-Negotiation to indicate link, duplex, and speed to the MAC. The result of the Auto-Negotiation exchange on the copper side is encoded onto the serial interface via the modified Auto- Negotiation so that the device can adjust to the correct operating speed. When switching to SGMII mode, Register 20.3 = 1. A register write must be done to enable the serial interface Auto- Negotiation. When switching to SGMII mode, Register must be set according to the desired setting. 1 = Feature is enabled 0 = Feature is disabled Loopback Modes Internal Loopback The Gigabit Ethernet Transceiver is capable of performing 2 types of loopback tests, Internal loopback and Line loopback. Internal loopback testing is a quick way to check the integrity of the MAC to SFP connections. This requires register writes to the PHY to put it in loopback mode. For the internal loopback operation Fiber Auto-Negotiation should be disabled both on the PHY and on the MAC. This is because the SFP requires a handshake between the Fiber AN on the MAC side and the copper Auto-Negotiation on the RJ45 side. Since the loop back mode automatically disables receive functionality on the copper side, it will be impossible to carryout this handshake that is required by the SFP.

6 To perform internal loopback you must first disable Fiber Auto-Negotiation by writing to register 20.3=0. (You will need to disable Auto-Negotiation of the MAC as well.) After disabling Auto-Negotiation, loopback can then be performed by writing to register The register write sequence is outlined below: Register 20.3 = 0 Disable Fiber Auto-Negotiation. Need software reset to update the value. (Separately from the PHY, you also need to disable Auto-Negotiation in the MAC.) Register 0.15 = 1 Software reset. Need to update register 20.3 setting. Register 0.14 = 1 Enable loopback. After loopback test is completed, you can now re-enable Fiber Auto-Neg by setting register 20.3=1 and soft resetting the PHY. Line Loopback Line loopback mode allows a link partner to send frames into the Gigabit Ethernet Transceiver to test the transmit and receive data path. Frames that are sent from a link partner into the PHY, before reaching the MAC interface pins are looped back and sent out on the line side. This allows the link partner to receive its own frames. Before enabling the line loopback feature, the Gigabit Ethernet Transceiver must first establish link to another PHY link partner. If Auto negotiation is enabled, both link partners should advertise the same speed and full-duplex. If Autonegotiation is disabled, both link partners need to be forced to the same speed and full-duplex. Once link is established, enable the line loopback mode by writing to register bit = 1 (Enable line loopback) = 0 (Disables line loopback) Virtual Cable Tester The Gigabit Ethernet Transceiver PHY has a Virtual Cable Tester TM (VCT) feature that uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, and termination mismatch. The TDR results are stored in register 28 pages 0-3 (one page for each wire pair). Register 22 is used to select which MDI pair has its results shown in Register 28. The PHY transmits a signal of known amplitude (+1 V) down each of the four pairs of an attached cable. It will conduct the cable diagnostic test on each pair sequentially. The transmitted signal will continue down the cable until it reflects off of a cable imperfection. The magnitude of the reflection and the time it takes for the reflection to come back are stored in register 28.12:8 and 28.7:0 respectively. Using the information from register 28, the distance to the problem location and the type of problem can be determined. For example, the time it takes for the reflection to come back can be converted to distance using the chart in Figure 1. The polarity and magnitude of the reflection together with the distance will indicate the type of discontinuity. For example, a +1V reflection will indicate an open close to the PHY and a -1V reflection will indicate a short close to the PHY. If the cable is properly terminated and there are no discontinuities, then there will be no reflections. When the cable diagnostic feature is activated by setting Register = 1, a pre-determined amount of time elapses before a test pulse is transmitted. This is to ensure that the link partner loses link, so that it stops sending 1000BASE-T or 100BASE-TX idles or 10 Mbit data packets. This wait time can be eliminated and TDR testing can begin immediately if VCT page 1 register is set to 1. This bit should be set only if it is known that there is no active link partner connected to the PHY. The TDR test can be performed either when there is no link partner or when the link partner is Auto-Negotiating or sending 10 Mbit idle link pulses. The definition for shorts and opens is arbitrary and the user can define it in anyway they desire using the information in register 28. The impedance mismatch at the location of the discontinuity could also be calculated knowing the magnitude of the reflection.

7 Executing the VCT TDR Step 0: Make sure the auto media select is not enabled before proceeding with the steps below. All discussion will refer to the pages 0-3 of register 28. Store the contents of register bits 22.7:0. Step 1: Write to register 22.7:0 = 0x00 and bit = 1 to enable the VCT. This bit self clears (28.15 = 0) to indicate that the VCT has completed. Step 2: To read the TDR results, set register 22.7:0 to select the MDI pair for the results to be read in register 28.14:0. Step 3: Once the enable VCT has completed, register bits 28.14: 13 will tell you if you have a successful test. If 28.14:13 = 11 indicates that the VCT test has failed; it means there was not enough quiet time to test this pair. (This scenario may occur if a link partner is forced 100Mb sending non-stop 100Mb idles so the VCT test cannot complete, though there may be a cable fault on the other pairs) Step 4: If a valid test is reported from step 3, register bits 28.14:13 each will have indicated one of three results: 10 = valid test, open in cable (> 330 ohms) 01 = valid test, short in cable (< 33 ohms) 00 = valid test, no open or short (However, need to check if properly terminated or have impedance mismatch.) If the distance to fault is 0xFF (infinite distance since no reflection), then the cable is properly terminated. Else, the cable has an impedance mismatch. Step 5: To determine the distance to fault, simply read the distance of reflection from register bits 28.7:0. These register bits correspond to a cable length based on figure 1. Step 6: Return to step 2 and proceed to read the next MDI pair. Step 7: Restore the original contents of register bits 22.7:0 Gigabit Ethernet Transceiver Cable Diagnostic Features When gigabit link is already established, the Gigabit Ethernet Transceiver PHY reports pair skew, pair swap, polarity swap, and approximate cable length. Such statuses are stored in the various pages of register 28. Register bits 22.7:0 selects register 28 pages. Register 28 allows reading and writing to the page selected. (Example: 22.7:0 = 0x0004 points to page 4 of register 28). Further more, register 29 selects extended register pages and register 31 allows reading these extended register pages. Pair Skew The PHY can detect skew among the four pairs of the cable that connects it with the link partner. Three of the four pairs will report its own delay skew with respect to the fastest pair, in 8ns increments. The results are summarized on page 4 of Register 28. Pair Swap The PHY's auto crossover can adjust the role of its MDl pairs when linking with a link partner. To determine the channel associated with the MDl pair, read the results that are summarized on page 5, bits 5 and 4 of register 28. Polarity Swap The PHY can detect if any of the RJ45 pairs connected to the PHY was inverted. Polarity status is stored on page 5, bits 3:0 of register 28. Cable Length From Gigabit Link After gigabit link, the PHY can determine the approximate cable length (non-tdr method). The decimal value in register 31 corresponds to a cable length. Register 29 is used to access the cable length registers of each pair.

8 The following tables define what changes can be made to the PHY registers, and what information can be read. Table 4.1: Register Map Address Description 00 Control Register 01 Status Register 02 NA 03 NA 04 Auto-Negotiation Advertisement Register 05 Link Partner Ability Register (Base Page) 06 Auto-Negotiation Expansion Register 07 Next Page Transmit Register 08 Link Partner Next Page Register BASE-T Control Register BASE-T Status Register NA 15 Extended Status Register 16 PHY Specific Control Register 17 PHY Specific Status Register 18 Interrupt Enable 19 Interrupt Status 20 Extended PHY Specific Control 21 Receive Error Counter 22 Extended Address for Cable Diagnostic Registers 23 NA 24 NA 25 NA 26 Extended PHY Specific Control 2 27 Extended PHY Specific Status and Mode Select 28 Cable Diagnostic Registers 29 Cable Length Register Access 30 NA 31 Cable Length Look Up Table Table 4.2 defines the register modes used in the following register map. Table 4.2: Register Mode Definitions Register Types Type Description LH Register field with latching high function. If status is high, then the register bit is set to one and remains set until a read operation is performed through the management interface or a reset occurs. LL Register field with latching low function. If status is low, then the register bit is cleared to zero and remains zero until a read operation is performed through the management interface or a reset occurs. R/W Read and write RES Reserved for future use. All reserved bits are read as zero unless otherwise noted. RO Read only. RO Read only ROC Read only clear. After read, register field is cleared. RWC Read/write clear on read. All bits are readable and writable. After reset or after the register field is read, register field is cleared to zero. RWR Read/write reset. All field bits are readable and writable. After reset, register field is cleared to zero. RWS Read/write set. All field bits are readable and writable. After reset, register field is set to a non-zero value specified in the text. SC Self-Clear. Writing a one to this register causes the desired function to be immediately executed, then the register field is automatically cleared to zero when the function is complete. Update Value written to the register field doesn't take effect until soft reset is executed. WO Write only. Reads to this type of register field return undefined data. For all binary equations appearing in the register map, the symbol is equal to a binary OR operation. A * in the settings column denotes default setting

9 Table 4.3: Control Register 0.15 Soft 1 = PHY reset R/W, 0 Self Clear Reset 0 = Normal operation SC 0.14 Loopback 1 = Enable loopback R/W = Disable loopback 0.13 Speed Selection (LSB) Bit 6, = Reserved 10 = 1000 Mbps 01 = 100 Mbps R/W 0 Update note 0.a 0.12 Auto-Negotiation Enable 00 = 10 Mbps 1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process 0.11 Power Down 1 = Power down 0 = Normal operation 0.10 Isolate 1 = Isolate 0 = Normal operation 0.9 Restart Auto- Negotiation 1 = Restart Auto-Negotiation Process 0 = Normal operation R/W 0 Update note 0.a,b,c,f R/W 0 0 note 0.c,e R/W 0 0 R/W, SC 0 Self Clear note 0.d 0.8 Duplex Mode 1 = Full-duplex 0 = Half-Duplex R/W 1 Update note 0.a 0.7 NA 0 R/W Speed Selection (MSB) See bit 13 R/W 1 Update note 0.a 0.5:0 Reserved RO Always note 0.a Speed, duplex, and auto-negotiation enable take on the values set by external pins ANEG[3:0] on hardware reset only. A write to these registers does not take effect until any one of the following also occurs: Software reset is asserted (register 0.15), Restart Auto-Negotiation is asserted (register 0.9), and Power down (register 0.11) transitions from power down to normal operation. note 0.b note 0.c note 0.d note 0.e note 0.f When the port is switched from power down to normal operation, software reset and restart Auto-Negotiation are performed even if bits Reset (0.15) and Restart Auto-Negotiation (0.9) are not set by the user. If register 0.12 is set to 0 and speed is manually forced to 1000 Mbps in registers 0.13 and 0.6, then Auto-Negotiation will still be enabled and only 1000BASE-T full-duplex is advertised if register 0.8 is set to 1, and 1000BASE-T halfduplex is advertised if 0.8 set to 0. Registers 4.8:5 and 9.9:8 are ignored. Auto-Negotiation is mandatory per IEEE for proper operation in 1000BASE-T. Auto-Negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (0.9) is set. Power down shuts down the chip except for the MAC interface if 16.3 is set to 1. If 16.3 is set to 0, then the MAC interface also shuts down. Power down also has no effect on the 125CLK output if 16.4 is set to 0. Bit 0.12 determines whether 10/100/1000BASE-T Auto-Negotiation is on or off. See 20.3 for SGMII and GBIC Auto- Negotiation Enable..

10 Table 4.4: Status Register BASE-T4 0 = PHY not able to perform RO Always 0 100BASE-T BASE-X Full-Duplex 1 = PHY able to perform fullduplex 100BASE-X 0 = PHY not able to perform RO BASE-X Half-Duplex Mbps Full- Duplex MbpsHalf- Duplex full-duplex 100BASE-X 1=PHYable to perform halfduplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X 1 = PHY able to perform fullduplex 10BASE-T 0 = PHY not able to perform full-duplex 10BASE- T 1 =PHY able to perform halfduplex 10BASE-T 0 = PHY not able to perform half-duplex 10BASE-T RO 0 RO 0 RO BASE-T2 0 = PHY not able to perform RO Always 0 Full-Duplex full-duplex 100BASE- T BASE-T2 0 = PHY not able to perform RO Always 0 Half-Duplex half-duplex 100BASE-T2 1.8 Extended Status 1 = Extended status information in RO Always 1 register Reserved 0 RO Always MF Preamble Suppression 1 = PHY accepts management frames with preamble suppressed RO Always Auto-Negotiation Complete 1 = Auto-Negotiation process complete 0 = Auto-Negotiation process not complete 1.4 Remote Fault 1 = Remote fault condition detected 0 = Remote fault condition not detected RO, LH 0 0 note 1.a 1.3 Auto-Negotiation 1 = PHY able to perform RO Always 1 Ability Auto-Negotiation 1.2 Link Status 1 = Link is up RO, 0 0 note 1.b 0 = Link is down LL 1.1 Jabber Detect 1 = Jabber condition detected RO, = Jabber condition not detected LH 1.0 Extended Capability 1 = Extended register capabilities RO Always 1 note 1.a Remote Fault bit is only supported in 1000BASE-T mode note 1.b This register indicates if link was lost since the last read. For the current link status either read this register back-toback or read register bit Link Real Time.

11 Table 4.5: Auto-Negotiation Advertisement Register 4.15 Next Page 1 = Advertise 0 = Not advertised note 4.a,b 4.14 Reserved 0 RO Always Remote Fault 1 = Set Remote Fault bit 0 = Do not set Remote Fault bit note 4.a 4.12 Reserved 0 note 4.a,c 4.11 Asymmetric Pause 1 = Asymmetric Pause 0 = No asymmetric Pause R/W 1 Retain note 4.a 4.10 PAUSE 1 = MAC PAUSE implemented 0 = MAC PAUSE not implemented R/W 1 Retain note 4.a BASE-T4 0 = Not capable of 100BASE-T4 RO Always BASE-TX Full-Duplex 1 = Advertise 0 = Not advertised note 4.a,d BASE-TX Half-Duplex 1 = Advertise 0 = Not advertised note 4.a,d BASE-TX Full-Duplex 1 = Advertise 0 = Not advertised note 4.a,d BASE-TX Half-Duplex 1 = Advertise 0 = Not advertised note 4.a,d 4.4:0 Selector Field = RO Always note 4.a Values programmed in register 4 have no effect unless Auto-Negotiation is restarted (Reg 0.9) or link goes down. note 4.b If 1000BASE-T is advertised then the required next pages are automatically transmitted. Register 4.15 should be set to 0 if no additional next pages are needed. note 4.c Reserved bit is R/W to allow for forward compatibility with future IEEE standards. note 4.d See note 0.c Table 4.6: Link Partner Ability Register (Base Page) 5.15 Next Page Received Code Word Bit Acknowledge Received Code Word Bit Remote Fault Received Code Word Bit :5 Technology Received Code Word Bit RO 0x00 0x00 Ability Field 12:5 5.4:0 Selector Field Received Code Word Bit 4:0 RO

12 Table 4.7: Auto-Negotiation Expansion Register 6.15:5 Reserved RO Always 0x000 note 6.a 6.4 Parallel Detection Fault 1 = A fault has been detected via the Parallel Detection function note 6.a,c 0 = A fault has not been detected via the Parallel Detection function 6.3 Link Partner 1 = Link Partner is Next Page able note 6.a Next Page Able 0 = Link Partner is not Next Page able 6.2 Local Next Page Able 1 = Local Device is Next Page able RO 1 note 6.a,b 6.1 Page Received 1 = A New Page has been received R0/ 0 0 note 6.0 Link Partner Auto-Negotiation Able 0 = A New Page has not been received 1 = Link Partner is Auto-Negotiation able 0 = Link Partner is not Auto- Negotiation able LH 6.a,d note 6.a note 6.a Register 6 is not valid until the Auto-Negotiation complete bit (Reg 1.5) indicates completed. note 6.b 6.2 = 1 if HWCFG_MODE[3:0] is not any of 0011, 0111 note 6.c 6.4 only applies to copper modes. note 6.d When using Auto Fiber/Copper Selection set = 1 for the fiber version of 6.1 and = 0 for the copper version. Table 4.8: Next Page Transmit Register 7.15 Next Page Transmit Code Word Bit 15 R/W 0 0 note 7.a 7.14 Reserved Transmit Code Word Bit Message Page Transmit Code Word Bit 13 R/W Acknowledge 2 Transmit Code Word Bit 12 R/W Toggle Transmit Code Word Bit :0 Message/ Unformatted Field Transmit Code Word Bit 10:0 R/W 0x001 0x001 note 7.a A write into register 7 will implicitly set a variable in the Auto-Negotiation state machine. Table 4.9: Link Partner Next Page Register 8.15 Next Page Received Code Word Bit Acknowledge Received Code Word Bit Message Page Received Code Word Bit Acknowledge 2 Received Code Word Bit Toggle Received Code Word Bit :0 Message/ Unformatted Field Received Code Word Bit 10:0 RO 0x000 0x000

13 Table 4.10: 1000BASE-T Control Register Test mode 000 =Normal Mode R/W note 9.a 001 = Test Mode 1 Transmit Waveform Test 010 = Test Mode 2- Transmit Jitter Test (MASTER mode) 011 = Test Mode 3- Transmit Jitter Test (SLAVE mode) 100 = Test Mode 4- Transmit Distortion Test 101, 110, 111 = Reserved 9.12 MASTER/ SLAVE Manual Configuration Enable 1 = Manual MASTER/SLAVE configuration 0 = Automatic MASTER/ SLAVE configuration note 9.b,c 9.11 MASTER/ SLAVE Configuration Value 1 = Manual configure as MASTER 0 = Manual configure as SLAVE R/W 1 Retain note 9.b,c,d 9.10 Port Type 1 = Prefer multi-port device (MASTER) 0 = Prefer single port device (SLAVE) R/W 1 Retain note 9.b,c,e BASE-T Full- Duplex 1 = Advertise 0 = Not advertised R/W 1 Retain note 9.b,c BASE-T Half-Duplex 1 = Advertise 0 = Not advertised note 9.b,c 9.7:0 Reserved R/W 0 0 note 9.a TX_TCLK comes from RX_CLK pin for jitter testing in test modes 2 and 3. note 9.b Values programmed in register 9.12:8 have no effect unless Auto-Negotiation is restarted (Reg 0.9) or link goes down. note 9.c See note 0.c note 9.d Bit 9.11 is ignored if bit 9.12 is equal to zero. note 9.e Bit 9.10 is ignored if bit 9.12 is equal to one MASTER/ SLAVE Configuration Resolution Local Receiver Status Remote Receiver Status Link Partner 1000BASE-T Full- Duplex Capability Link Partner 1000BASE-T Half- Duplex Capability Table 4.11: 1000BASE-T Status Register MASTER/ SLAVE Configuration Fault 1 = MASTER/SLAVE configuration fault detected 0 = No MASTER/SLAVE con- RO, LH, SC 0 0 figuration fault detected 1 = Local PHY configuration resolved to MASTER 0 = Local PHY configuration resolved to SLAVE 1 = Local Receiver OK 0 = Local Receiver Not OK 1 = Remote Receiver OK 0 = Remote Receiver Not OK 1 = Link Partner is capable of 1000BASE-T full-duplex 0 = Link Partner is not capable of 1000BASE-T full- duplex 1 = Link Partner is capable of 1000BASE-T half-duplex 0 = Link Partner is not capable of 1000BASE-T half- duplex note 10.a note 10.a 10.9:8 Reserved 00 RO :0 Idle Error Count MSB of Idle Error Counter RO, SC note 10.b note 10.a Values in register 10.11:10 are not valid until register 6.1 is 1. note 10.b Counter will peg at and will not roll over.

14 Table 4.12: Extended Status Register BASE-X Full- 1 =1000BASE-X full-duplex capable RO 1 1 note 15.a Duplex 0 = not 1000BASE-X full- duplex BASE-X Half- Duplex BASE-T Full- Duplex BASE-T Half- Duplex capable 1 =1000BASE-X half-duplex capable 0 = not 1000BASE-X half- duplex capable 1 = 1000BASE-T full duplex capable 0 = not 1000BASE-T full-duplex capable 1 = 1000BASE-T half-duplex capable 0 = not 1000BASE-T half-duplex capable RO 1 1 note 15.a RO 1 1 note 15.a RO 1 1 note 15.a 15.11:0 Reserved RO 0x000 0x000 note 15.a Bit 13 = bit 12 = 1 Table 4.13: PHY Specific Control Register 16.15:14 Transmit 1000BASE-T 10/100BASE-T R/W 00 Retain note 16.a FIFO depth 16.13:12 Receive FIFO depth 00 = +/- 16 Bits 01 = +/- 24 Bits 10 = +/- 32 Bits 11 = +/- 40 Bits 1000BASE-T 00 = +/- 16 Bits 01 = +/- 24 Bits 10 = +/- 32 Bits 11 = +/- 40 Bits 00 = +/- 8 Bits 01 = +/-12 Bits 10 = +/- 16 Bits 11 = +/- 20 Bits 10/100BASE-T 00 = +/- 8 Bits 01 = +/-12 Bits 10 = +/- 16 Bits 11 = +/- 20 Bits Assert CRS on Transmit 1 = Assert on transmit 0 = Never assert on transmit Force Link 1 = Force link good Good 0 = Normal operation 16.9:8 Energy Detect 0x = Off 10 = Sense only on Receive (Energy Detect) 11 = Sense and periodically transmit NLP (Energy Detect+ TM ) 16.7 Enable Extended Distance 16.6:5 MDI Crossover Mode 1 = Lower 10BASE-T receive threshold 0 = Normal 10BASE-T receive threshold 00 = Manual MDI configuration 01 = Manual MDIX configuration 10 = Reserved 11 = Enable automatic crossover for all modes 1 = 125CLK Low 0 = 125CLK Toggling 1 = Always power up 0 = Can power down 16.4 Disable 125CLK 16.3 MAC Interface Power Down 16.2 SQE Test 1 = SQE test enabled 0 = SQE test disabled 16.1 Polarity 1 = Polarity Reversal Disabled Reversal 0 = Polarity Reversal Enabled 16.0 Disable 1 = Disable jabber function Jabber 0 = Enable jabber function R/W 00 Retain note 16.b note 16.c note 16.d R/W 0x Update note 16.e note 16.f R/W 11 Update note 16.e,f,j R/W 1 Update note 16.e R/W 1 Update note 16.e,k note 16.i note 16.h note 16.i

15 note 16.a note 16.b note 16.c note 16.d note 16.e note 16.f note 16.g note 16.h note 16.i note 16.j note 16.k Transmit FIFO is enabled in 1000BASE-T mode or serial interface mode. Receive FIFO is enabled in TBI mode or serial interface mode. This bit has no effect in full-duplex. If link is forced to be good, the link state machine is bypassed and the link is always up. In 1000BASE-T mode this has no effect. Changes in bits16.9:8, 16.6:5, 16.4, and 16.3 are disruptive to the normal operation; hence, any changes to these registers must be followed by software reset to take effect. When using cable exceeding 100m, the 10BASE-T receive threshold must be lowered in order to detect incoming signals. SQE Test is automatically disabled in full-duplex mode regardless of the state of bit 16.2 SQE test is default to disable for multi-port devices and enable for single port devices. If polarity is disabled, then the polarity is forced to be normal in 10BASE-T. Jabber has effect only in 10BASE-T half-duplex mode. Bit 6:5- {ENA_XC, ENA_XC} if copper Auto-Negotiation is enabled. (HW Rst Default) Bit 6:5- {0, 0} if copper Auto-Negotiation is not enabled. (HW Rst Default) This bit determines whether MAC interface powers down when register 0.11 is used to power down the device or when the PHY enters the energy detect state. Table 14: PHY Specific Status Register 17.15:14 Speed 11 = Reserved RO 10 Retain note 17.a 10 = 1000 Mbps 01 = 100 Mbps 00 = 10 Mbps Duplex 1 = Full-duplex RO 1 Retain note 17.a 0 = Half-duplex Page Received 1 = Page received RO, = Page not received LH Speed and 1 = Resolved note 17.a Duplex Resolved 0 = Not resolved Link (real time) 1 = Link up 17.9:7 Cable Length (100/1000 modes only) 0 = Link down 000 = < 50m 001 =50-80m 010 = m 011 = m 100 = >140m RO note 17.b 17.6 MDI Crossover 1 = MDIX note 17.a Status 0 = MDI 17.5 Downshift Status 1 = Downshift 0 = No Downshift 17.4 Energy Detect 1 = Sleep Status 0 = Active 17.3 Transmit Pause Enabled 1 = Transmit pause enabled 0 = Transmit pause disabled Note 17.a, c 17.2 Receive Pause Enabled 1 = Receive pause enabled 0 = Receive pause disabled Note 17.a, c 17.1 Polarity (real time) 1 = Reversed 0 = Normal 17.0 Jabber (real time) 1 = Jabber 0 = No jabber RO 0 Retain note 17.a Speed, duplex, MDI, TX pause, and RX pause status bits are valid only after resolved bit = 1. The resolved bit is set when Auto-Negotiation is completed or Auto-Negotiation is disabled. note 17.b Cable length measurement is only a rough estimate. Actual value depends on the attenuation of the cable, output levels of the remote transceiver, connector impedance, etc. note 17.c This is a reflection of the MAC pause resolution. This bit is for information purposes and is not used by the device.

16 Table 4.15: Interrupt Enable Auto-Neg. Error 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable Speed Changed 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable Duplex Changed 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable Page Received 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable Auto-Neg Complete 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable Link Status Changed 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable 18.9 Symbol Error Interrupt 1 = Interrupt enable Enable 0 = Interrupt disable 18.8 False Carrier Interrupt 1 = Interrupt enable Enable 0 = Interrupt disable 18.7 FIFO Over/Underflow 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable 18.6 MDI X-over Changed 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable 18.5 Downshift Interrupt 1 = Interrupt enable Enable 0 = Interrupt disable 18.4 Energy Detect 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable 18.3:2 Reserved Always write Polarity Changed 1 = Interrupt enable Interrupt Enable 0 = Interrupt disable 18.0 Jabber Interrupt Enable 1 = Interrupt enable 0 = Interrupt disable Table 4.16: Interrupt Status Auto-Negotiation 1 = Auto-Negotialion Error note 19.a Error 0 = No Auto-Negotialion Error Speed Changed 1 = Speed changed 0 = Speed not changed Duplex Changed 1 = Duplex changed 0 = Duplex not changed Page Received 1 = Page received 0 = Page not received Auto-Negotiation 1 = Auto-Negotiation completed Completed 0 = Auto-Negotiation not completed Link Status 1 = Link status changed Changed 0 = Link status not changed 19.9 Symbol Error 1 = Symbol error 0 = No symbol error 19.8 False Carrier 1 = False carrier 0 = No false carrier 19.7 FIFO Over/ 1 = Over/Underflow Error Underflow 0 = No FIFO Error 19.6 MDI Crossover 1 = Crossover changed Changed 0 = Crossover not changed 19.5 Downshift Interrupt 1 = Downshift detected 0 = No down shift 19.4 Energy Detect 1 = Energy Detect state changed Changed 0 = No Energy Detect state change detected 19.3:2 Reserved 00 RO Always Polarity Changed 1 = Polarity Changed 0 = Polarity not changed 19.0 Jabber 1 = Jabber 0 = No jabber note 19.a An error is said to occur if MASTER/SLAVE does not resolve, parallel detect fault, no common HCD, or link does not come up after negotiation is completed.

17 Table 4.17: Extended PHY Specific Control Link down on no 1 = Lost lock detect R/W 0 0 note 20.a Idles 0 = No lost lock detect Reserved 0 R/W Reserved 0 R/W TBI RCLK[1 :0] 1 = Disable RCLK[1 :0] R/W 0 0 disable 0 = Enable RCLK[1:0] 20.11:10 Master downshift counter 00 = 1x, 01 = 2x, 10 = 3x, 11 = 4x R/W 11 Update note 20.b,c,f 20.9:8 Slave downshift counter 00 = disable, 01 = 1x 10 = 2x,11 = 3x R/W 00 Update note20.b, c, e, f 20.7 RGMII Receive Clock Timing 1 = Add delay to RX_CLK for RXD Outputs R/W 0 Update note 20.c,i Control 0 = Does not add delay to RX_CLK 20.6:4 Default MAC 110 R/W 110 Update note interface speed See note 20.e 20.3 Fiber Auto- 1 = Enable Negotiation Enable 0 = Disable 20.2 Reserved 0 R/W 0 Update 20.1 NA 0 R/W 0 Update 20.0 Reserved 0 20.b,d R/W 1 Update Note 20.b note 20.a Asserts lost lock and brings link down if Idle not seen within 1 ms in 1000BASE-T mode. note 20.b Changes in bits 20.7 are disruptive to the normal operation; hence, any change to these registers must be followed by software reset to take effect note 20.c Register 20.11:10 has no effect unless 20.9:8 is not set to default (00). note 20.d note 20.e note 20.f MAC Interface Speed during Link down 000 = 10 Mbps 001 = 100 Mbps 01X = 1000 Mbps 100 = 10 Mbps 101 = 100 Mbps 110 = 1000 Mbps 111 = 1000 Mbps TX_CLK speed during link down 000 = 2.5 MHz 001 = 25 MHz 01X = 0 MHz 100 = 2.5 MHz 101 = 25 MHz 110 = 2.5 MHz 111 = 25 MHz TX_CLK speed during 1000BASE-T link 000 = 0 MHz 001 = 0 MHz 01X = 0 MHz 100 = 2.5 MHz 101 = 25 MHz 110 = 2.5 MHz 111 = 25 MHz 00 disables the four-pair/two-pair downshift feature (default). 01, 10, and 11 enable this feature. 1x, 2x, 3x, and 4x is the number of times the PHY attempts to establish Gigabit link before the PHY downshifts to the next highest speed. Table 4.18: Receive Error Counter 21.15:0 Receive Error Count Error Count RO,SC 0x0000 0x0000 note 21.a note 21.a Counter will peg at OxFFFF and will not roll over. Table 4.19: VCT Page Selection for VCT Register :8 Reserved 22.7:0 VCT register page selection 0x00 = VCT page 0: MDl[0] TDR results 0x01 = VCT page 1: MDl[1] TDR results 0x02 = VCT page 2: MDl[2] TDR results 0x03 = VCT page 3: MDl[3] TDR results 0x04 = VCT page 4: Pair Skew 0x05 = VCT page 5: Pair Swap and Polarity RW 0x00 Retain

18 Table 4.20: Extended PHY Specific Control :8 Reserved R/W 0x00 Retain 26.7 Fiber Signal Detect Input 1 = Use external hardware pin for signal detect 0 = Force signal detect to be good 26.6 Fiber Input Impedance 1 = 75 Ohms 0 = 50 Ohms 26.5 Fiber Output 1 = 75 Ohms Impedance 0 = 50 Ohms 26.4 Fiber Mode Clock 1 = Enable Enable 0 = Disable 26.3 Fiber Output Boost 1 = (1000BASE-X) 0 = low (SGMII) 26.2:0 Fiber Output Amplitude note 26.a note 26.b 000 = 0.5V 100 = 0.70V 001 = 0.55V 101 = 0.75V 010 = 0.60V 110 = 0.80V 011 = 0.65V 111 = 0.85V R/W 0 Update R/W 0 Update note 26.a R/W 0 Update note 26.a R/W 0 Update note 26.a R/W 1 Update note 26.a R/W 010 Retain note 26.b Changes in bits 26.5:3 are disruptive to the normal operation hence any change to these registers must be followed by software reset to take effect. Differential voltage peak-to-peak measured with differential load Table 4.21: Extended PHY Specific Status Fiber/Copper Auto Selection Disable 1 = Disable fiber/copper auto selection 0 = Enable fiber/copper auto R/W 1 Update note 27.a,b Select Fiber/ Copper Auto- Negotiation register access Fiber/Copper resolution Serial Interface Auto-Negotiation Bypass Enable Serial Interface Auto-Negotiation Bypass Status selection 1 = Select fiber Auto-Negotiation registers 0 = Select copper Auto- Negotiation registers 1 = Fiber link 0 = Copper link 1 = Feature is enabled 0 = Feature is disabled 1 = Serial interface link came up because bypass mode timer timed out and fiber Auto-Negotiation was bypassed. 0 = Serial interface link came up because regular fiber Auto-Negotiation completed Interrupt Polarity 1 = INT active low 0 = INT active high 27.9:4 Reserved 27.3:0 MODE[3:0] 0100 = SGMII 1000 = SERDES 1100 = SERDES note 27.b,c RO 0 Retain note 27.c R/W 1 Update note 27.d RO 0 Retain note 27.e R/W 0 Update R/W 1000 Update note 27.a,f note 27.a Changes in bits and 3:0 are disruptive to the normal operation hence any change to these registers must be followed by software reset to take effect. note 27.b Register selects whether registers 1, 4, 5, 6, or 15 should be fiber or copper Auto-Negotiation registers note 27.c note 27.d note 27.e note 27.f has effect only if register is set to enable Fiber/Copper Auto Detection. Register indicates the resolution of the Fiber/Copper Auto Detection. This bit is valid only when link is up. The default value for Register = 1 for the following modes: 0111 = GMII to fiber 0011 = RGMII to fiber 1000 = GBIC For SGMII mode, if the bypass logic brings up the serial interface link, copper Auto-Negotiation will restart and advertise only gigabit speed = SGMII without Clock with SGMII Auto-Neg to copper 1000 = 1000BASE-X without Clock with 1000BASE-X Auto-Neg to copper 1100 = 1000BASE-X without Clock without 1000BASE-X Auto-Neg to copper

19 Table 4.22: VCT TDR Pages Enable VCT 0 = VCT completed R/W, 0 0 note 28.a 1 = Run VCT SC Enable 1.5sec wait 0 = Enable 1.5sec wait R/W, 0 0 note 28.b,c 1 = Disable 1.5sec wait SC 28.14:13 VCT Test Status 00 = valid test, normal cable (no RO 00 Retain note 28.d short or open in cable) 10 = valid test, open in cable 01 = valid test, short in cable 11 = Test fail 28.12:8 Magnitude 0x1F = +1V reflection RO 0x00 Retain note 28.d,e 0x10 = No reflection 0x00 = -1V reflection 28.7:0 Distance Refer to Figure 1 RO 0x00 Retain Note28.d,e note 28.a Enable VCT is available on VCT page 0 only note 28.b Enable 1.5sec wait is available on VCT page 1 only note 28.c Enables or disables the 1.5sec wait before running the TDR test note 28.d These bits are valid after completion of VCT = 0 note 28.e These bits are not valid if VCT Test Status 28.14:13 indicate test failed Figure 1: Cable Fault Distance Trend Line

20 Table 4.23: VCT Page 4: Pair Skew 28.15:12 MDI[3] skew Skew = value x 8ns RO :8 MDI[2] skew Skew = value x 8ns RO :4 MDI[1] skew Skew = value x 8ns RO :0 MDI[0] skew Skew = value x 8ns RO Table 4.24: VCT Page 5: Pair Swap and Polarity 28.15:7 Reserved RO 0x00 0x Page 4 & 5 Valid 0 = not valid for reading Status 1 = valid for reading 28.5 Channel C, D 0 = Channel D on MDI[2], Channel C on MDI[3] 1= Channel Con MDI[2], Channel D on MDI[3] 28.4 Channel A, B 0 = Channel B on MDI[0], Channel A on MDI[1] 1= Channel A on MDI[0], Channel B on MDI[1] 28.3 MDI[3] Polarity 0 = Positive 28.2 MDI[2] Polarity 1 = Negative 28.1 MDI[1] Polarity 28.0 MDI[0] Polarity Table 4.25: Cable Length Register Access 29.15:0 Select Pair To Access In Register 31 0x8754 = Access to MDI[0] 0x9754 = Access to MDI[1] 0xa754 = Access to MDI[2] 0xb754 = Access to MDI[3] RW 0x0000 0x0000 Table 4.26: Register 31 Cable Length Look Up Table Reg 31 decimal Length meters Reg 31 decimal Length meters Reg 31 decimal Length meters Reg 31 decimal Length meters Reg 31 decimal Length meters