UNH-IOL MIPI Alliance Test Program

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1 DSI Receiver Protocol Conformance Test Report UNH-IOL 121 Technology Drive, Suite 2 Durham, NH mipilab@iol.unh.edu Engineer Name engineer@company.com Panel Company 1010 Glass Way San Jose, CA USA 09/27/10 Enclosed are the results from the MIPI DSI Receiver Protocol Conformance testing performed on: Panel Company 3 Lane MIPI DSI Receiver This testing was performed by UNH-IOL from September 20, 2010 September 25, The test suite referenced in this report is available on the MIPI Alliance website: Issues Observed While Testing The DSI Receiver under test was observed to meet all requirements tests for DSI Receivers. For specific details regarding issues please see the corresponding test result. Test Report Completed 9/27/2010 iol Digitally signed by UNH-IOL Date: :24:38 04'00' Kevin Maffei kmaffei@iol.unh.edu

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3 Section 1: DUT and Test Setup Information Test Setup Details Manufacturer Model Firmware Revision Hardware Revision UNH-IOL ID: DSI/DCS Traffic Generator DSI/DCS Montior Additional Comments/Notes Panel Company 3 Lane MIPI DSI Receiver Not Available Not Available Moving Pixel Company P331 Agilent GHz Infiniium DSO with UNH-IOL DPHYGUI Software The below diagram shows the test setup used in performing this testing. The following table contains possible results and their meanings: with Comments FAIL Warning Informative Refer to Comments Not Applicable Borderline Not Tested Interpretation The Device Under Test (DUT) was observed to exhibit conformant behavior. The DUT was observed to exhibit conformant behavior however an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed. The DUT was observed to exhibit non-conformant behavior. The DUT was observed to exhibit behavior that is not recommended. s are for informative purposes only and are not judged on a pass or fail basis. From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included. The DUT does not support the technology required to perform these tests. The observed values of the specified parameters are valid at one extreme, and invalid at the other. Not tested due to the time constraints of the test period. 3

4 Section 2: Protocol Conformance Test s Chapter 5: DSI Physical Layer, Group 1: Data Flow Control Test Packets Sent in Entirety To determine that the DSI device transmits Packets in their entirety. Test Packets Received in Entirety To determine that the DSI device receives Packets in their entirety. The peripheral properly transmitted all packets in entirety. Refer to figure 1. The peripheral received packets in entirety because the image was displayed properly on the LCD panel. Refer to Figure 5. Chapter 5: DSI Physical Layer, Group 2: Bidirectionality and Low Power Signaling Policy Test Proper Lane Use in Command Mode To determine that the DSI device properly implements bidirectionality on Lane 0 and unidirectionality on Lane 1,2,3 if operating in Command Mode. Test Proper Lane Use in Video Mode To determine that the DSI device properly implements bidirectionality or unidirectionality on Lane 0 and unidirectionality on Lane 1,2,3 if operating in Video Mode. Test Clock Lane Only Driven by Host To determine that the DSI host always drives the Clock lane and that a peripheral device never drives the Clock Lane. Test Low Power Transmission To determine that the DSI host sends LP transmissions on data lane 0 only and that the DSI Peripheral sends transmissions on data lane 0 only use LP. Test Bidirectional Transmission To determine that the DSI host sends LP transmissions on data lane 0 only and that the DSI Peripheral sends transmissions on data lane 0 only use LP. Test Peripheral Receives Bus Turnaround Request To determine that Hosts and Peripherals properly accept and issue Bus Turn-Around commands. Not Applicable The peripheral properly receivied HS data on all data lanes (4). This was verified by an image being displayed properly on the LCD panel. See Figure 2 to see the bi-directionality on lane 0 after sending HS packet. The clock lane is never driven by the peripheral. The peripheral responds to both HS and LP transmissions. The response only occurs on data lane 0. Refer to Figure 3. The peripheral responds to both HS and LP transmissions. The response only occurs on data lane 0. Refer to Figure 3. The peripheral properly issues and receives bus turnaround commands whether the data is sent in HS or LP. Refer to figure 3. Chapter 5: DSI Physical Layer, Group 3: Command Mode Interfaces 4

5 Test Peripheral Command Mode Data Lane Module Requirements To determine that a Peripheral Data Lane Module operating in Command Mode supports CIL-SFAA (HS-RX, LP-RX, LP-TX, LP-CD). Test Peripheral Command Mode Clock Lane Module Requirements To determine that a Peripheral Clock Lane Module operating in Command Mode supports CIL-SCNN (HS-RX, LP-RX). Test Command Mode Bidirectional Link Reverse Direction Escape Mode Support To determine that a peripheral supporting bidirectionality on Lane 0 while operating in Command Mode supports Escape mode. Test Command Mode Bi-directional Link Forward Direction Escape Mode Support To determine that a host supporting bidirectionality on Lane 0 while operating in Command Mode supports Escape mode. Test ULPS Support Offered To determine that a host or peripheral supporting bidirectionality on Lane 0 while operating in Command Mode supports offering Escape mode entry to ULPS. Test ULPS Support Received To determine that a host or peripheral supporting bidirectionality on Lane 0 while operating in Command Mode supports receiving Escape mode entry to ULPS. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Chapter 5: DSI Physical Layer, Group 4: Video Mode Interfaces Test Peripheral Video Mode Data Lane Module Requirements To determine that a DSI receiver data lane module operating in Video Mode supports CIL-SFAN (HS-RX, LP-RX). Test Peripheral Video Mode Clock Lane Module Requirements To determine that a DSI receiver clock lane module operating in Video Mode supports CIL-SCNN (HS-RX, LP-RX). Test Video Mode RESET Trigger Message Support To determine that a device operating in Video Mode supports Escape Mode properly. Test Video Mode ULPS Support To determine that a device operating in Video Mode supports Escape Mode properly. 5 The peripheral properly receives HS video data. Refer to Figure 5. Refer to Figure 3 to see the panel respond to both HS and LP Transmissions. The peripheral properly receives HS video data. Refer to Figure 5. Refer to Figure 3 to see the panel respond to both HS and LP Transmissions. Not Applicable Can not implement with current software running on the test station. Not Applicable Can not implement with current software

6 running on the test station. Chapter 5: DSI Physical Layer, Group 5: Bidirectional Control Mechanism Test Peripheral Transmits Bus Turn-Around Request To determine that a peripheral performs a Bus Turn-Around properly when it is finished transmitting a response to a host processor. The peripheral properly turns the bus back to the testing station. Refer to Figure 3. Chapter 5: DSI Physical Layer, Group 6: Clock Management Test Continuous Clock Behavior To determine that a host claiming continuous clock behavior keeps the DSI Clock Lane active between HS data transmissions. Test Non-Continuous Clock Behavior To determine that a host claiming non-continuous clock behavior drives the Clock Lane to LP-11 between HS data transmissions. Test Escape Mode Non-Continuous Clock Frequency Matching To determine that a host claiming non-continuous clock behavior drives the Clock Lane to LP-11 during Escape Mode between HS data transmissions. The peripheral properly enters and exits HS while the clock lane is continuously active. Refer to Figure 6. The peripheral properly enters and exits HS while the clock lane is non-continuous. Refer to Figure 19. Not Applicable Not a peripheral test. Chapter 5: DSI Physical Layer, Group 7: System Power-Up and Initialization Test TX-Stop Detection by Peripheral To determine that the Peripheral s D-PHY detects a TX-Stop state after power on. Informative The peripheral did not accept bus transaction after any of the cases were sent. This is verified because the testing station was waiting on a BTA that occurs at the end of the INIT. Chapter 6: Multi-Lane Distribution and Merging, Group 1: Multi-Lane Interoperability and Lane-number Mismatch Test Proper Byte Distribution and Merging Over Multiple Lanes To determine that the Host Processor properly distributes and a Peripheral properly merges a transmitted or received stream of bytes. 6 The peripheral properly merges all of the bytes regardless of how many lanes are operating. This was verified by viewing an image on the screen for 1 lane, 2 lane, 3 lane, and 4 lane setups.

7 Test Proper Byte Distribution and Merging for Odd Byte Counts To determine that the Host Processor properly distributes and a Peripheral properly merges a transmitted or received stream of bytes when the length of that stream of bytes is not an integer multiple of the number of lanes. Test Proper Merging when Byte Stream Ends Early Verify proper behavior by a device when a received stream of bytes ends 2 cycles earlier on one lane than on all other lanes. The peripheral properly merges all of the bytes regardless of how many lanes are operating. This was verified by viewing an image on the screen for 1 lane, 2 lane, 3 lane, and 4 lane setups. This is a four lane device and it can be configured to run as either 1, 2, 3, or 4 lane system. All configurations function correctly. The same number of lanes are used by both the testing station and the peripheral. Refer to figure 1 to see the data be returned from the peripheral. The data did come back on lane 0 only. Test Number of Lanes To verify that a host or peripheral in a system does not dynamically change the number of Lanes used. Test Matching Number of Lanes To verify that a host and peripheral in a system support the same number of lanes. Test LP Mode To determine that a peripheral operating in LP mode only uses Lane 0 to send data back to the host. The peripheral properly merges all of the bytes regardless of how many lanes are operating. This was verified by viewing an image on the screen for 1 lane, 2 lane, 3 lane, and 4 lane setups. Chapter 7: Low Level Protocol Errors and Contention, Group 1: Low-Level Protocol Errors Test SoT Error Received by Peripheral To determine that the Peripheral properly handles a received SoT Error. Test SoT Sync Error Received by Peripheral To determine that the Peripheral properly handles a received SoT Sync Error. Test EoT Sync Error Received by Peripheral To determine that the Peripheral properly handles a received EoT Sync Error. Test Escape Mode Entry Command Error Detected by Host or Peripheral 7 The peripheral properly received the SoT error. Refer to Figure 7 to see the SoT error flag set. The peripheral properly received the SoT sync error flag due to a multibit SoT error sent by the testing station. Refer to Figure 8. The peripheral properly detected the EoT error.

8 To determine that the Peripheral or Host properly handles a received Escape Mode Entry Command Error. Test LP Transmission Sync Error Detected by Host or Peripheral To determine that the Peripheral or Host properly handles a received Escape Mode Entry Command Error. Test No Valid Escape False Control Error Detected by Host or Peripheral To determine that the Peripheral or Host properly handles a received False Control Error. Test No Turnaround Sequence False Control Error Detected by Host or Peripheral To determine that the Peripheral or Host properly handles a received False Control Error. The peripheral properly detects the escape mode entry command error. Refer to Figure 10. The peripheral properly detects the invalid LP transmission and sets the LP Transmission sync error flag. Refer the Figure 11. The peripheral properly detects the LP request followed by no command. This did set the False control error flag, refer to Figure 12. The peripheral properly detects the HS request followed by no command. Chapter 7: Low Level Protocol Errors and Contention, Group 2: Contention Detection and Recovery Test LP High Fault Detected by Both Sides To verify that a device properly detects and responds to an LP high fault. Test LP Low Fault Detected by Both Sides To verify that a device properly detects and responds to an LP low fault. Test False LP Low Fault Not Detected To verify that a device does not incorrectly detect an LP low fault. Test LP High Fault Detected by Host To verify that a host correctly detects an LP High fault. Test LP Low Fault Detected by Host To verify that a host correctly detects an LP Low fault. Test LP High Fault Detected by Peripheral To verify that a peripheral correctly detects an LP High fault. Test LP Low Fault Detected by Peripheral To verify that a peripheral correctly detects an LP Low fault. 8 Refer to Figure 14. Refer to Figure 15. The peripheral does not transition to LP-RX upon reception of the false LP low fault. Refer to figure 15. Not Applicable Not a peripheral test. Not Applicable Not a peripheral test. Not Applicable Testing station is not properly driving contention as defined in spec. Not Applicable Testing station is not properly driving

9 Test HS RX Timer To verify that a DSI peripheral properly implements the HS RX Timer. Test LP TX Timer - Peripheral To verify that a bi-directional peripheral properly implements the LP TX Timer. contention as defined in spec. Not Applicable Timer value is unknown. Not Applicable Timer value is unknown. Chapter 7: Low Level Protocol Errors and Contention, Group 3: Additional Timers Test Turnaround Acknowledge Timeout To verify that a Peripheral properly implements the TA_TO Timer. Test Peripheral Reset Timeout To verify that a Peripheral properly implements the PR_TO Timer. Not Applicable Timer value is unknown. Not Applicable Timer value is unknown. Chapter 7: Low Level Protocol Errors and Contention, Group 4: Acknowledge and Error Reporting Mechanism Test Acknowledge To verify that a Peripheral properly acknowledges packets received error-free. Test Error Reported To verify that a Peripheral properly acknowledges packets received with errors. Test Acknowledge READ Request To verify that a Peripheral properly acknowledges READ packets received error-free. Test Error Reported on READ Request To verify that a Peripheral properly acknowledges READ packets received with errors. Test Single Bit Error on READ Request To verify that a Peripheral properly acknowledges READ packets received with a correctable single bit error. Test Error Register Cleared To verify that a Peripheral properly clears its error register after 9 The peripheral returned an ACK-TRIG response after the LP packet shown in Figure 1 was sent. The peripheral received an error after an HS packet shown in Figure 2. The peripheral properly received and returned the data which was sent to it. Refer to Figure 16. The peripheral detected errors and it did not transmit any read data only an error report packet. Refer to Figure 17. The peripheral properly transmitted the read data followed by an error report, reporting a one bit correctable ECC error. Refer to Figure 18.

10 reporting errors via an Acknowledge and Error Report packet. The error register is cleared properly refer to Figure 3. Section 3: Plots and Decode Data. Figure 1 Packets sent in entirety: Decode: Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 ( ) (4 8-bit words) ECC: 0x3F ( ) CRC: 0xF26E F E F2 BTA Request: LP-10/00/10/00 10

11 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 2 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x37 (110111): Set Maximum Return Packet Size WC : 0x0001 ( ) (0d1) ECC: 0x1D ( ) D BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 3 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x3400 ( ) (0d13312) ECC: 0x1C ( ) C BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 4 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 11

12 DT : 0x12 (010010): Generic Short READ Response, 2 bytes returned WC : 0x0000 ( ) (0d0) ECC: 0x18 ( ) BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul :27:06) ================= (dphygui.m): ================================================================== Figure 2 Proper lane use in command mode: Decode: HS decode ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 ( ) (4 8-bit words) ECC: 0x3F ( ) CRC: 0xF26E F E F2 LP DECODE: 12

13 13

14 Figure 3 Low Power Transmission: Decode: LP DECODE: Recovered State Sequence: (216 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L0L1L1L1L0L0L0L0L1L1L0L0L1L0L1L0L0L0L0L1L0L0L0L0L 0L0L0L0L0L0L0L0L0L1L1L1L1L1L1L0L0L0L0L0L0L0L0L0L0L 0L0L1L0L1L1L0L0L0L0L0L0L0L1L0L0L0L1L1L0L1L0L1L0L0L 1L1L1L0L1L1L0L0L1L0L0L1L1L1L1L1H1L1L1H1L0L0L0L1L0L 0L0L0L1L1H1L1L1H Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 ( ) (4 8-bit words) ECC: 0x3F ( ) CRC: 0xF26E F E F2 BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 14

15 Esc Entry : LP-10/00/01/00 Esc Command: (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul :19:00) ================= (dphygui.m): ================================================================== HS decode: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x37 (110111): Set Maximum Return Packet Size WC : 0x0001 ( ) (0d1) ECC: 0x1D ( ) D ******************* No more bursts left. Decode complete. ******************** (dphygui.m): ================================================================== (dphygui.m): ===== HS DECODER Complete (29-Jul :20:00) ================= (dphygui.m): ================================================================== LP DECODE: Recovered State Sequence: (98 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L1L1H1L0L1L1L1L0L0L0L0L1L0L1L0L0L0L0L0L0L1L0L0L0L 0L0L0L0L0L1L0L0L0L0L0L1L0L0L0L1L1L0L0L0L1H1L1L1H BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x8201 ( ) (0d33281) ECC: 0x18 ( ) ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 15

16 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 1 = DSI Protocol Violation BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul :20:57) ================= (dphygui.m): ================================================================== LP DECODE: Recovered State Sequence: (314 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L1L1H1L0L0L0L1L0L0L0L0L1L1H1L1L1H1L0L1L1L1L0L0L0L 0L1L0L0L1L0L0L1L0L0L0L0L0L0L0L0L0L0L0L0L1L0L1L1L0L 0L0L0L1L1L1L0L0L0L1H1L1L1H1L0L1L1L1L0L0L0L0L1L0L1L 0L1L1L0L0L0L0L0L1L0L0L0L0L0L0L0L0L0L0L0L0L0L1L0L1L 0L1L1L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L 0L0L0L0L0L0L0L0L0L0L0L0L1L0L0L0L0L1L0L0L1L1L0L0L0L 0L0L0L1H1L1L1H BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x3400 ( ) (0d13312) ECC: 0x1C ( ) 16

17 C BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 2 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Display->Host) VC : 00 DT : 0x1A (011010): Generic Long READ Response WC : 0x0004 ( ) (4 8-bit words) ECC: 0x35 ( ) CRC: 0x0321 1A BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul :21:48) ================= (dphygui.m): ================================================================== Figure 4 Command Mode Bidirectional Link Reverse Direction Escape Mode Support: Decode: 17

18 ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 ( ) (4 8-bit words) ECC: 0x3F ( ) CRC: 0xF26E F E F2 ******************* No more bursts left. Decode complete. ******************** LP DECODE: Recovered State Sequence: (98 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L1L1H1L0L1L1L1L0L0L0L0L1L0L1L0L0L0L0L0L0L1L0L0L0L 0L0L1L0L0L1L0L0L0L0L0L0L1L0L0L1L0L0L0L0L1H1L1L1H BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0241 ( ) (0d577) ECC: 0x09 ( ) ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 1 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 18

19 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) Figure 5 Peripheral Video Mode Data Lane Module Requirements: Decode: ******* BURST 98 CONTENTS (4 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x21 (100001): Sync Event, H Sync Start WC : 0x0000 ( ) (0d0) ECC: 0x12 ( ) ******* BURST 99 CONTENTS (2406 bytes extracted from burst, after Sync) ******* DSI PACKET DECODE (Long, 2406 bytes, Host->Display) VC : 00 DT : 0x3E (111110): Packed Pixel Stream, 24-bit RGB, Format WC : 0x0960 ( ) ( bit words) ECC: 0x04 ( ) CRC: 0x6485 3E A5 84 4F 9E 7A 48 B AB 84 5D 62 3A D

20 5E 39 0C D C4 A1 69 DB B7 7B D4 B0 76 D8 B3 7E D6 B0 7F AE 8A 5A 93 6E E EA C9 94 E7 C8 8F E8 CA 8C F4 D6 96 E7 CB 8A A A BF 9F C 83 5D B 65 3C 1E 6C 47 2D D 0A 45 2C F 8B A E D E B4 8E 69 C B 51 2B A6 7C 56 B E 64 3C BA 90 6A D4 AA 84 DB B1 8B D9 AE 8B B9 91 6E CB A2 82 BD E 1F 2F 0A 00 5A 36 1E A3 80 6A E E 88 6B C 5C 57 3A 2C 47 2B A 49 2A 27 BA 9B 99 DB BB BC A E 15 1B 04 0C 20 0B 14 1E 0A F 1B 0C A 0C 16 0A 0A 1B 10 0A E 5F B 2F 23 CA B9 B1 FF F1 EB FF F1 ED E 0E 11 2D B 0F 13 0A F 09 0B C E 08 0A 0B C C A D A 0C 0B C 70 B4 A9 B C 4D 7E C 44 3B 4E 41 3A 4A 34 2E 3C 0D 0A E C E 24 1E 22 2A E E D6 CD C6 FF FA F1 FF EE E3 C9 AD A2 A1 7F 75 EE CF BD E4 CF B4 D9 C9 A8 FF F2 D1 FF F5 D3 F2 DF BE DF CC AB E0 CE AA CD BB 97 CC B8 95 EA D6 B3 D6 BF 9D E2 CB AB F6 DD BE EF D6 B7 FF E7 C9 FF EA C9 FE E1 B9 FF E0 B7 F8 DC B5 E8 CE AB FC E1 C3 FF E6 C CD A9 8F DF B7 9E BD 93 7B 78 4E 38 5E E 02 3D 17 0C 4E 2D 1C EB CC B0 CD B0 90 9E FA E3 C4 DC C7 AC ED D7 BF F3 DD C6 EB D2 BE 8C 6F 5D 3E 21 0F B 20 3D D 35 2B 4D D 4A 46 3D 2B 29 2D 1B 19 1C 0D 0A 0C E 1D 4B 2F 2E E F 50 4A E 3F 42 4B 3C 41 3C 2D E 5B 4C E 5E 4E E 2E F A 1C B A A 1C 2B F A 8C 9B D 4B 5B BA A8 B6 9D F 8B F DA C3 C9 D0 BA BD C8 AF B2 A7 8D 8E AB 8F 8E BE A2 A1 E2 C4 C2 FF E6 E4 CF B1 AF D0 B2 B0 FF E3 DF FF E6 E2 F8 DD D6 F9 E0 D9 E9 D3 C8 C3 AF A4 E2 D0 C4 EC DC CF F3 E6 D6 EB DE CD F5 E6 CF FE EE D5 F0 DF C5 FB E7 CC FF F6 D7 EB D4 B2 D6 BD 95 EB CF A7 F8 DB AF EF CF A6 FF E6 C1 E1 BE A0 9F 7A 67 6F 49 3E 73 4A F 7D C 6E AB 8E 92 A5 88 8C 9E B D 73 7E 8B E D E 7C 8C E 90 A1 B2 A4 B5 CB BD CE E4 D3 E3 FB EB F6 FE F1 F8 F2 E6 EA E7 DE E1 E8 E2 E4 ED EB EE F3 F4 F8 ED EE F3 F5 F4 FA FA F5 FC FC F1 F7 EB DA E0 FF F1 F3 D9 C2 C8 E9 D3 E0 F6 DF F1 F0 DA F1 CB B4 D0 BD A5 C5 A0 86 AB D 88 6E 91 6E F B 5E 51 3C 4B 33 1F 2B 22 0E 1A E 1C F B 2A E 7A AF 9D AB BC AA BA C7 B5 C3 BC AA B B C 1C 1F 8D 7D 80 E2 D2 D5 F8 E7 EF D3 C2 CC C0 AE BC C5 B3 BF EC D9 DD F9 E5 E6 EB D5 D7 DC C3 C6 D7 BA BC CF B2 B4 FF E4 E6 FF F6 F6 DC BE BE BF A3 A0 B6 9A 97 B D3 BA B3 F4 DB D4 F7 DE D7 FF F8 ED FF F7 E4 FF E6 CC A E 3D 1E E2 C9 B3 FF FB ED F9 EB E8 F4 EA E9 FF FE F8 F6 F7 F1 F2 FF F8 E9 FC F6 F6 FF FF FF FF FB FF EC E F CF A5 8D FF F8 E4 FF F3 E5 C6 AB A B A1 70 6B A8 6F 66 A1 65 5A 7D F 1A 0A 20

21 E 43 3A 3B D 10 0A 16 0B 05 1D 0E C 72 5C A5 76 5C 82 4F E 78 3F E 23 7F 45 2D 8E 54 3E 94 5C B 76 4B 42 5E 38 2F 5C 3A 31 5F E 35 2E 3E 2A F 2D 1E 1B B 1B 1B 0D 0D F E 0C 1C 13 0E F B 60 A5 84 8D 8C F 8B E 48 8C 48 3B 8B B 4A 2D BF 6C 40 D DD 8F 44 EB A4 56 DB 9C 4C E6 AF 5F EE C0 73 F3 CE 87 F1 D3 93 F1 DA A4 F2 E0 B2 F3 E3 BF F2 E3 C6 F2 E3 CC F5 E6 D1 F7 E8 D5 F7 E7 D8 F0 E3 DA F3 E8 E2 F4 E9 E5 EE E4 E2 EB E1 E2 EC E3 E6 EB E2 E7 E7 DD E5 EA E0 E9 E9 DF E8 E9 DD E7 E8 DC E6 E8 DB E4 E9 D9 E3 E8 D9 E0 E9 D8 E0 EB D8 DE EB D6 DD EE D4 DD EE D4 DD ED D3 DC E8 D1 D7 E5 D2 D8 E2 D3 D6 E3 D8 DC DC D6 D6 E3 DF E0 DC D8 D7 DC D3 D4 EB E1 E2 E7 D8 DB F6 E0 E3 F3 CF D3 FF EC EE F7 D0 D D 0B B 00 3F 13 0A 43 0E D D 89 1E 2E F FF C2 BF D A2 3D 33 7F 18 0F 8B 23 1A 7B A B 2E 1D 9C C 3A F 3A B A 8F D 0B C 93 0F 0B 90 0C 08 B2 31 2C A F 0E D 8D 1B B 1A AD 43 2B EA FF A5 83 E5 93 6B FF B5 8B FF C5 9D FF AB 88 E C B6 49 2C CA 58 3D C F0 7F 61 D5 6A 4A ED FD 9D 75 E FF AC 7D FF B4 82 F7 A8 70 FF BB 83 FF BB 87 E C 4D 26 9E 4E 2D 83 2D B B 6F 0E 07 7C 1E 16 7F 25 1C 8B 34 2A B A C EE AF 9D DC A4 8D DA A8 8D EB BE 9D FF D7 B6 FF E0 BF FF E9 C9 D C6 7A 62 BA 6A 53 C C0 73 5F CF B5 71 5E 8C BE D3 8E 7F BF 8A 78 E1 B2 9E FF E8 D1 FF DE C6 FA D8 BD FF DF C3 F0 C7 A9 FF DA BC FF CC AE FF C4 A4 F6 B C F2 A9 7E FF BB 8A F0 AE 7C EC B2 82 FF D3 A4 E4 B9 8F E8 C1 9A F0 C4 A1 CD 9B 78 FF C3 9E D FB AA 7F F4 A5 7C C F3 B4 93 FF D0 AC F9 BB 94 DA 9F 73 9B D5 A2 77 DC AF 86 C5 9D 7A FF F7 DA FF EF D5 FA D6 C0 FF EB D D B 13 0B 5E C 13 0D 4E 23 1D 6B 3E A 25 1F 55 1A A 6A 25 1E 74 2B 24 7D E 8A 3A 33 8E 3B C B 2C A A C 3B 2A 9B 3A 29 9E 3B 28 A1 3E 2B AE AB B2 4D 39 A2 3D 29 AD BA 56 3F AF 4B 33 B0 4C 32 B B2 4E 34 BD C1 5D 45 B7 53 3B BE 5A 42 CD 69 4F DB 77 5D D E DC CB D D4 72 4D D3 71 4A D0 6F 45 C CE 6D 42 CB 6A 3F C9 68 3D CF 6F 45 BC 5C 34 E2 84 5E DF D8 7F 5F E5 8E 72 BF B4 5F 4A DE 8C 77 DA 84 6D BD 5F 43 D DA 7B 5B CC 6F 4D CA 6D 4B BC 62 3F C6 6C 49 FF B0 8E E0 82 5E CE 6D 4A B D D7 6E 4E D D DF D8 6A 49 CD D0 6C 4A E C4 6B 4D 92 3E 22 6E 1E B 2F C 22 6B E 5B 24 1F C 4D 22 1B D 1A 4A 1E 1B 4C 20 1D A 46 1F E D F 1B 36 0A 0B 5D 2C 2F AE 77 7A C8 8D 8F AA 6A 68 AB 6A 64 B2 6E 63 B C0 7E 6E C0 81 6F C CF 8D 77 CD BA 76 5F B2 6B 55 BC 75 5F CA C3 7E 6E C DB 98 8F D4 93 8D C0 80 7E BD 7F 80 B9 7D 7F B AC 6E 79 AB 6D 7A A B C1 7F 8B B4 6F 74 CF C7 7E 6D C4 76 5F C0 6D 4F C0 69 4B C5 65 4C A9 45 2E AC AB AB 3C 28 A4 3A 22 AC 4A 31 BC 66 4D C6 7E 66 D8 9B

22 ******* BURST 100 CONTENTS (4 bytes extracted from burst, after Sync) ********* DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x21 (100001): Sync Event, H Sync Start WC : 0x0000 ( ) (0d0) ECC: 0x12 ( ) Figure 6 Continuous Clock behavior: Decode: N/A 22

23 Figure 7 SoT Error received by peripheral: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0201 ( ) (0d513) ECC: 0x23 ( ) ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 23

24 Figure 8 SoT Sync error: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0002 ( ) (0d2) ECC: 0x17 ( ) ERROR REPORT DECODE: 0 = SoT Error 1 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 24

25 Figure 9 Eot Sync Error: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0201 ( ) (0d513) ECC: 0x23 ( ) ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 25

26 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation Figure 10 Escape Mode Entry Command Error: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0008 ( ) (0d8) ECC: 0x2E ( ) E ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 1 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 26

27 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 0 bytes remaining... (Done, no complete packets left Figure 11 LP Transmission Sync Error Flag: ******* BURST 1 CONTENTS (3.125 bytes extracted from burst, after Sync) ******* *** ERROR *** :(decodedsipacket.m): Invalid packet, contains < 32 bits. Aborting packet decode. BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 2 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0010 ( ) (0d16) ECC: 0x2D ( ) D ERROR REPORT DECODE: 27

28 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 1 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation BTA Request: LP-10/00/10/00 Figure 12 False control error due to LP request: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report 28

29 WC : 0x0040 ( ) (0d64) ECC: 0x21 ( ) ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 1 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 29

30 Figure 13 False control error due to HS request: Decode: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0040 ( ) (0d64) ECC: 0x21 ( ) ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 1 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 30

31 BTA Request: LP-10/00/10/00 Figure 14 LP High Fault: Decode: N/A Figure 15 LP Low Fault: Decode: N/A 31

32 Figure 16 Writing generic data and seeing it be returned: ******* BURST 1 CONTENTS (16 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 12 bytes, Host->Display) VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0006 ( ) (6 8-bit words) ECC: 0x23 ( ) CRC: 0x84DE DE 84 4 bytes remaining... DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x0454 ( ) (0d1108) ECC: 0x03 ( ) FULL HEX PACKET DUMP: (Each byte be appears LSB first on the wire) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 2 CONTENTS (10 bytes extracted from burst, after Sync) ********** 32

33 DSI PACKET DECODE (Long, 10 bytes, Display->Host) VC : 00 DT : 0x1A (011010): Generic Long READ Response WC : 0x0004 ( ) (4 8-bit words) ECC: 0x35 ( ) CRC: 0x40F1 1A F1 40 BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) Figure 17 No read data returned only error report: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0201 ( ) (0d513) ECC: 0x23 ( ) ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 33

34 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) Figure 18 Read data and error report returned: Decode: LP DECODE: Recovered State Sequence: (558 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L0L1L1L1L0L0L0L0L1L1L0L0L1L0L1L0L0L0L1L1L0L0L0L0L 0L0L0L0L0L0L0L0L0L1L1L0L0L0L1L0L0L0L0L1L0L1L0L1L0L 34

35 0L0L1L0L0L0L0L0L1L0L0L0L1L0L0L0L0L1L0L0L0L1L0L0L1L 1L0L0L1L1L0L0L0L0L1L0L0L0L1L0L0L1L1L1L1L0L1L1L0L0L 1L0L0L0L0L1L0L0L1L0L0L1L0L0L0L0L1L0L1L0L1L0L0L0L1L 0L0L0L0L0L0L1L0L0L0L0L0L0L1H1L1L1H1L0L1L1L1L0L0L0L 0L1L0L1L0L1L1L0L0L0L0L0L1L0L0L0L0L0L0L0L0L0L0L0L0L 0L1L0L1L0L1L1L0L0L1L0L0L0L1L0L0L0L0L0L0L0L0L0L0L0L 1L1L0L0L1L1L0L0L0L0L0L0L0L0L0L0L1L0L0L0L1L1L1L1L0L 0L0L0L0L0L1L0L1H1L0L1L1L1L0L0L0L0L1L0L1L0L0L0L0L0L 0L0L0L0L0L0L0L0L0L1L0L0L0L0L0L0L0L0L1L0L1L1L1L0L0L 1H1L1L1H Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 1 CONTENTS (16 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 12 bytes, Host->Display) VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0006 ( ) (6 8-bit words) ECC: 0x23 ( ) CRC: 0x84DE DE 84 4 bytes remaining... DSI PACKET DECODE (Short, 4 bytes, Host->Display) VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x0454 ( ) (0d1108) ECC: 0x02 ( ) (*** INVALID ECC ***, Calculated: ) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 2 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Display->Host) VC : 00 DT : 0x1A (011010): Generic Long READ Response WC : 0x0004 ( ) (4 8-bit words) ECC: 0x35 ( ) CRC: 0x40F1 1A F

36 Esc Entry : LP-10/00/01/00 Esc Command: (LPDT) ******* BURST 3 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0100 ( ) (0d256) ECC: 0x3A ( ) A ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 1 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation Figure 19 Non-Continuous Clocking: 36

37 Decode: N/A 37