NovTech System On Chip NOVSOM CV

Transcription

1 NovTech System On Chip NOVSOM CV User s Guide Document Number: NOVSOM_CV_002 Rev /2014 Property of NovTech, Inc, under NDA Page 1 of 31

2 Contact Information: Home Page: Company: Modules: E mail: sales@novtech.com USA/Europe or Locations Not Listed: 7401 Wiles Road, Suite 229 Coral Springs, FL United States +1 (888) or +1 (954) sales@novtech.com Europe, Middle East, and Africa: 30 HaShahar St. Ra'anana, Israel +972 (0) gguy@novtech.com Information in this document is provided solely to enable system and software implementers to use NovTech products. There are no express or implied copyright licenses granted hereunder to design or fabricate any circuits or circuits based on the information in this document. NovTech reserves the right to make changes without further notice to any products herein. NovTech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NovTech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in NovTech data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. NovTech does not convey any license under its patent rights nor the rights of others. NovTech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NovTech product could create a situation where personal injury or death may occur. Should Buyer purchase or use NovTech products for any such unintended or unauthorized application, Buyer shall indemnify and hold NovTech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NovTech was negligent regarding the design or manufacture of the part. Learn More: For more information about NovTech products, please visit NovTech and the NovTech logo are trademarks of NovTech, Inc. All other product or service names are the property of their respective owners. NovTech, Inc All rights reserved. Property of NovTech, Inc, under NDA Page 2 of 31

3 Table of Contents About This Document... 5 Audience... 5 Revision History... 5 Related Documents... 5 Acronyms and Abbreviations General Information SoM Details SoC Boot Configuration Clocking Board to Board Connectors Unexposed Pins Power Scheme DDR On SoM Booting Options Additional Booting Options Minimal Requirement to Boot the NOVSOM Mechanical B2B Part Numbers: Ordering Information Pin Out Tables Property of NovTech, Inc, under NDA Page 3 of 31

4 List of Figures Figure 1 Top view of the NOVSOM CV... 7 Figure 2 Top view of the NOVSOM CV (note that the B2B connectors are mounted on the bottom side of the module) List of Tables Table 1 Specifications... 8 Table 2 J2 A side, 1 to Table 3 J2 A side, 41 to Table 4 J2 A side, 81 to Table 5 J2 B side, 1 to Table 6 J2 B side, 41 to Table 7 J2 B side, 81 to Table 8 J3 A side, 1 to Table 9 J3 A side, 41 to Table 10 J3 A side, 81 to Table 11 J3 B side, 1 to Table 12 J3 B side, 41 to Table 13 J3 B side, 81 to Table 14 J4 A side, 1 to Table 15 J4 A side, 41 to Table 16 J4 A side, 81 to Table 17 J4 B side, 1 to Table 18 J4 B side, 41 to Table 19 J4 B side, 81 to Property of NovTech, Inc, under NDA Page 4 of 31

5 About This Document This manual describes the features and functionality of the NOVSOM CV. Audience This manual is intended for software, hardware, and system engineers who are planning to use the NOVSOM CV. Revision History Ver 0.1 Related Documents Altera Cyclone V SoC documentation at: cyclone v.jsp NOVSOM CV Design Guide NOVSOM CV Ordering Guide NOVPEK CV User Manual Acronyms and Abbreviations The following acronyms and abbreviations are used in this manual. This list does not include signal, register, and software mnemonics. B2B CPU CSPI DDR EEPROM GPIO I2C I/O JTAG Board to Board Central Processing Unit Serial Peripheral Interface Double Data Rate Electrically Erasable Programmable Read Only Memory General Purpose Input/Output Inter integrated Circuit Input/Output Joint Test Access Group Property of NovTech, Inc, under NDA Page 5 of 31

6 MB MCU MMC OTG PCB PHY POR RAM SD UART USB Megabyte Microcontroller Unit Multi media Card On the go Printed Circuit Board Physical interface Power on reset Random access memory Secure digital (smart media) Universal asynchronous receiver/transmitter Universal serial bus Property of NovTech, Inc, under NDA Page 6 of 31

7 1. General Information The NOVSOM resolves some of the biggest challenges faced by designers when working with the SoC, such as: DDR Routing Boot Configuration Dense Routing of BGA Packages, High Board Layer Count All while maintaining the full flexibility available on the SoC. A key element of the SoC is the multiplexing of interfaces, FPGA IO pins (Single ended and differential) and the voltage options for different IO groups/banks. All of these are available on the NOVSOM CV. Optional HPS NAND FLASH Optional HPS EEPROM Optional HPS SD Slot Optional 1Gb HPS SPI NOR Altera Cyclone V SoC Up to 2Gbyte DDR3 with optional ECC Optional 1Gb SPI NOR FPGA Configurator Figure 1 - Top view of the NOVSOM CV Property of NovTech, Inc, under NDA Page 7 of 31

8 Table 1 Specifications Characteristic Clock Temperature: Operating Storage Relative Humidity Power Requirements Dimension Specifications Up to 925MHz C: 0 C to +70 C I: 40 C to +85 C A: 40 C to +105 C 40 C to +85 C 0 to 90% (non condensing) Requires Power Management 2.83 inch x 2.33 inch 2. SoM Details The heart of the NOVSOM is the Altera Cyclone V SoC, in addition, the NOVSOM includes the DDR, clocks and Solid State solutions: 2.1 SoC The NOVSOM can support all Cyclone V SoC series SE, SX and ST in F31 and U23 packages, please refer to Altera documentation to find the supported densities and speed for the above. 2.2 Boot Configuration FPGA Boot Select Pins There are five pines, MSEL0 to MSEL4 that define the FPGA boot configuration, they are routed to the B2B and need to be set on the carrier board for the preferred boot option. Please follow Altera FPGA boot configuration documents for the proper setting HPS Boot Select Pins There are three pines, BOOTSEL0 to BOOTSEL2 (multiplex on other interfaces signals) that define the HPS boot configuration, they are routed to the B2B and need to be set on the carrier board for the preferred boot option. Please follow Altera HPS boot configuration documents for the proper setting HPS Clock Select Pins There are two pines, CLKSEL0 and CLOCKSEL1 (multiplex on other interfaces signals) that define the HPS clocks boot configuration, they are routed to the B2B and need to be set on the carrier board for the preferred boot option. Please follow Altera HPS boot configuration documents for the proper setting HPS POR Select Pin The HPS PORSEL pin is routed to the B2B and need to be set on the carrier board for the preferred boot option. Please follow Altera HPS boot configuration documents for the proper setting. Property of NovTech, Inc, under NDA Page 8 of 31

9 2.3 Clocking HPS CLK1 A 25MHz crystal oscillator is connected to this clock interface on the NOVSOM HPS CLK2 This pin is routed to the B2B and can to be set on the carrier board for the preferred input FPGA Single/Differential Ended Clocks All FPGA Single/Differential Ended Clocks are routed to the B2B and can to be set on the carrier board for the preferred input or serves at any other functions assigned to these pins (please review Altera documentation for all pin definitions). 2.4 Board to Board Connectors There are three B2B connectors that connect the NOVSOM to the carrier board, they carry all HPS peripheral signals, all FPGA BNKS signals, all HPS/FPGA system and configuration singles and all Power signals, see section 4.0 for mechanical information and section 5.0 for the pinout assignment. 2.5 Unexposed Pins The following signals that reside on the Cyclone V SoC are not exposed on the NOVSOM B2B connectors: HPS Bank 6 DDR Signals. HPS CLK1 Pin, SoC Balls D25 (F31 package). RREF_TL Pin, on board 2.0K Resistor to Ground, SoC Ball G1 (F31 package). 2.6 Power Scheme All Power Rails of the SoC are routed to the B2B Connectors, additional Power Rail DDR_VTT_VCNTL (2.5V to 3.3V) need to be driven into the board powering the DDR3 VTT termination supplier. 2.7 DDR The NOVSOM has four DDR3 memory chips, 16 bit width each, to provide a maximum of 2Gbyte, and two DDR3 memory chips for ECC. The DDR3 can be run up to a maximum specified clock speed of 400MHZ. 2.8 On SoM HPS Booting Options SD Card The NOVSOM SD supports board booting via the Cyclone V SoC SDMMC interface on BANK7C. The carrier board pin strapping needs to be set for this boot option (BOOTSELs). Please note that the SDMMC interface pins are routed to the B2B connector and can be used in the PINMUXING Property of NovTech, Inc, under NDA Page 9 of 31

10 scheme if this boot option is not selected. The SD is powered by the HPS VCCIO7C power rail and it needs to be set to 3.3V or 1.8V if this option to be used (Please refer to Altera HPS boot configuration documents for the proper setting) NAND FLASH The NOVSOM NAND FLASH supports board booting via the Cyclone V SoC NAND interface on BANK7B. The carrier board pin strapping needs to be set for this boot option (BOOTSELs). Please note that the NAND interface pins are routed to the B2B connector and can be used in the PINMUXING scheme if this boot option is not selected. The NAND FLASH is powered by the VCCIO7B power rail and it needs to be set to 3.3V or 1.8V if this option to be used (Please refer to Altera HPS boot configuration documents for the proper setting) QSPI NOR FLASH The NOVSOM QSPI FLASH supports board booting via the Cyclone V SoC QSPI interface on BANK7B. The carrier board pin strapping needs to be set for this boot option (BOOTSELs). Please note that the QSPI interface pins are routed to the B2B connector and can be used in the PINMUXING scheme if this boot option is not selected. The QSPI is powered by the VCCIO7B power rail and it needs to be set to 3.3V or 1.8V if this option to be used (Please refer to Altera HPS boot configuration documents for the proper setting) FPGA With this boot option, the FPGA is configured and then it configures the HPS, please refer to Altera HPS boot configuration documents for the proper setting HPS boot CLKSEL and PORSEL Both CLKSEL and PORSEL need to be set on carrier board to support the require setting. 2.9 On SoM FPGA Configuration Options QSPI NOR FLASH The NOVSOM supports FPGA configuration via the AS x4 interface, the carrier board pinstrapping needs to be set for this configuration option (MSELs). Please refer to Altera HPS boot configuration documents for the proper setting FPPx8/FPPx16/PS/JTAG All other valid configuration options for the FPGA are supported by routing the signals to the 2B2. A base board implantation is required to support these options unless a HPS to FPGA parallel configuration is selected, the carrier board pin strapping needs to be set for this configuration options (MSELs). Please refer to Altera HPS boot configuration documents for the proper setting. Property of NovTech, Inc, under NDA Page 10 of 31

11 2.10 Minimal Requirement to Boot the NOVSOM In order to boot the NOVSOM, the carrier board, at minimum, needs to drive the following signals: All Power Rails of the SoC with the correct sequencing. Reset signal, HPS_nPOR and HPS_nRST. Boot strapping options set correctly. All JTAG and configuration signals are terminated correctly. Optional: UART1 for terminal messages. 3. Mechanical Figure 2 Top view of the NOVSOM CV (note that the B2B connectors are mounted on the bottom side of the module) Property of NovTech, Inc, under NDA Page 11 of 31

12 3.1 B2B Part Numbers: SoM Carrier Board TE: (5mm B2B height) (8mm B2B height) Foxconn: QT H QT H (5mm B2B height) QT H (8mm B2B height) Please retrieve the datasheets for the base board connectors from: Property of NovTech, Inc, under NDA Page 12 of 31

13 4. Ordering Information Property of NovTech, Inc, under NDA Page 13 of 31

14 5. Pin Out Tables Table 2 J2 A side, 1 to 40 PIN SIGNAL CV F31 Ball J2 A1 GND Power Plane J2 A2 GND Power Plane J2 A3 VCCIO8A_DIFFIO_RX_T31_F31_P G mil Differential routed with T31_F31_N J2 A4 VCCIO8A_DIFFIO_RX_T31_F31_N G mil Differential routed with T31_F31_P J2 A5 GND Power Plane J2 A6 VCCIO8A_DIFFIO_TX_T40_F31_P G7 1445mil Differential routed with T40_F31_N J2 A7 VCCIO8A_DIFFIO_TX_T40_F31_N F6 1360mil Differential routed with T40_F31_P J2 A8 GND Power Plane J2 A9 VCCIO8A_DIFFIO_RX_T17_F31_P H8 1566mil Differential routed with T17_F31_N J2 A10 VCCIO8A_DIFFIO_RX_T17_F31_N G8 1536mil Differential routed with T17_F31_P J2 A11 GND Power Plane J2 A12 GND Power Plane J2 A13 VCCIO8A_DIFFIO_TX_T10_F31_P C7 1074mil Differential routed with T10_F31_N J2 A14 VCCIO8A_DIFFIO_TX_T10_F31_P B7 1001mil Differential routed with T10_F31_P J2 A15 GND Power Plane J2 A16 VCCIO8A_DIFFIO_TX_T16_F31_P A6 892mil Differential routed with T16_F31_N J2 A17 VCCIO8A_DIFFIO_TX_T16_F31_N A5 868mil Differential routed with T16_F31_P J2 A18 GND Power Plane J2 A19 VCCIO8A_DIFFIO_RX_T27_F31_P B6 937mil Differential routed with T27_F31_N J2 A20 VCCIO8A_DIFFIO_RX_T27_F31_N B5 921mil Differential routed with T27_F31_P J2 A21 GND Power Plane J2 A22 GND Power Plane J2 A23 VCCIO8A_DIFFIO_RX_T37_F31_P J mil Differential routed with T37_F31_N J2 A24 VCCIO8A_DIFFIO_RX_T37_F31_N J9 1241mil Differential routed with T37_F31_P J2 A25 GND Power Plane J2 A26 VCCIO8A_DIFFIO_TX_T18_F31_P A4 837mil Differential routed with T18_F31_N J2 A27 VCCIO8A_DIFFIO_TX_T18_F31_N A3 807mil Differential routed with T18_F31_P J2 A28 GND Power Plane J2 A29 VCCIO8A_DIFFIO_TX_T28_F31_P C3 708mil Differential routed with T28_F31_N J2 A30 VCCIO8A_DIFFIO_TX_T28_F31_N B3 777mil Differential routed with T28_F31_P J2 A31 GND Power Plane J2 A32 GND Power Plane J2 A33 VCCIO8A_DIFFIO_TX_T30_F31_P D2 631mil Differential routed with T30_F31_N J2 A34 VCCIO8A_DIFFIO_TX_T30_F31_N C2 708mil Differential routed with T30_F31_P J2 A35 GND Power Plane J2 A36 VCCIO8A_DIFFIO_TX_T36_F31_P E1 649mil Differential routed with T36_F31_N J2 A37 VCCIO8A_DIFFIO_TX_T36_F31_N D1 584mil Differential routed with T36_F31_P J2 A38 GND Power Plane J2 A39 VCCIO8A_DIFFIO_TX_T34_F31_P E3 665mil Differential routed with T34_F31_N J2 A40 VCCIO8A_DIFFIO_TX_T34_F31_N E2 618mil Differential routed with T34_F31_P Property of NovTech, Inc, under NDA Page 14 of 31

15 Table 3 J2 A side, PIN SIGNAL CV F31 Ball J2 A41 GND Power Plane J2 A42 GND Power Plane J2 A43 VCCIO8A_DIFFIO_RX_T9_P K mil Differential routed with T9_N J2 A44 VCCIO8A_DIFFIO_RX_T9_N J mil Differential routed with T9_P J2 A45 GND Power Plane J2 A46 FPGA_GXB_REFCLK2L_F31_P P9 1047mil Differential routed with CLK2L_F31_N J2 A47 FPGA_GXB_REFCLK2L_F31_N P8 976mil Differential routed with CLK2L_F31_P J2 A48 GND Power Plane J2 A49 FPGA_GXB_RX_L8_F31_P J2 610mil Differential routed with L8_F31_N J2 A50 FPGA_GXB_RX_L8_F31_N J1 568mil Differential routed with L8_F31_P J2 A51 GND Power Plane J2 A52 FPGA_GXB_RX_L7_F31_P L2 609mil Differential routed with L7_F31_N J2 A53 FPGA_GXB_RX_L7_F31_N L1 565mil Differential routed with L7_F31_P J2 A54 GND Power Plane J2 A55 FPGA_GXB_RX_L6_F31_P N2 598mil Differential routed with L6_F31_N J2 A56 FPGA_GXB_RX_L6_F31_N N1 556mil Differential routed with L6_F31_P J2 A57 GND Power Plane J2 A58 FPGA_GXB_REFCLK1L_P T9 914mil Differential routed with CLK1L_N J2 A59 FPGA_GXB_REFCLK1L_N T8 871mil Differential routed with CLK1L_P J2 A60 GND Power Plane J2 A61 GND Power Plane J2 A62 FPGA_GXB_RX_L5_P R2 618mil Differential routed with L5_N J2 A63 FPGA_GXB_RX_L5_N R1 574mil Differential routed with L5_P J2 A64 GND Power Plane J2 A65 FPGA_GXB_RX_L4_P U2 611mil Differential routed with L4_N J2 A66 FPGA_GXB_RX_L4_N U1 566mil Differential routed with L4_P J2 A67 GND Power Plane J2 A68 FPGA_GXB_RX_L3_P W2 639mil Differential routed with L3_N J2 A69 FPGA_GXB_RX_L3_N W1 594mil Differential routed with L3_P J2 A70 GND Power Plane J2 A71 GND Power Plane J2 A72 FPGA_GXB_RX_L2_P AA2 606mil Differential routed with L2_N J2 A73 FPGA_GXB_RX_L2_N AA1 559mil Differential routed with L2_P J2 A74 GND Power Plane J2 A75 FPGA_GXB_RX_L1_P AC2 608mil Differential routed with L1_N J2 A76 FPGA_GXB_RX_L1_N AC1 563mil Differential routed with L1_P J2 A77 GND Power Plane J2 A78 FPGA_GXB_RX_L0_P AE2 624mil Differential routed with L0_N J2 A79 FPGA_GXB_RX_L0_N AE1 580mil Differential routed with L0_P J2 A80 GND Power Plane Property of NovTech, Inc, under NDA Page 15 of 31

16 Table 4 J2 A side, PIN SIGNAL CV F31 Ball J2 A81 N.C. J2 A82 FPGA_VCCL_GXBL L5/R5 Power J2 A83 FPGA_VCCA_FPLL AA8/K9 Power J2 A84 FPGA_VCCE_GXBL AA5/M6 Power J2 A85 VCCIO3A_FPGA_AS_DATA2 AE8 1102mil Routed on NOVSOM to QSPI NOR FLASH J2 A86 VCCIO3A_FPGA_TDI U8 1024mil J2 A87 VCCIO3A_FPGA_AS_DATA1 AE5 1304mil Routed on NOVSOM to QSPI NOR FLASH J2 A88 VCCIO3A_FPGA_DCLK U7 1819mil Routed on NOVSOM to QSPI NOR FLASH J2 A89 VCCIO3A_FPGA_AS_DATA0 AE6 1167mil Routed on NOVSOM to QSPI NOR FLASH J2 A90 GND Power Plane J2 A91 VCCIO3A_DIFFIO_RX_B15_F31_P AC mil Differential routed with B15_F31_N J2 A92 VCCIO3A_DIFFIO_RX_B15_F31_N AD mil Differential routed with B15_F31_P J2 A93 VCCIO3A_DIFFIO_RX_B1_P AD mil Differential routed with B1_N J2 A94 VCCIO3A_DIFFIO_RX_B1_N AE mil Differential routed with B1_P J2 A95 VCCIO3A_DIFFIO_RX_B10_F31_P AG1 683mil Differential routed with B10_F31_N J2 A96 VCCIO3A_DIFFIO_RX_B10_F31_N AH2 681mil Differential routed with B10_F31_P J2 A97 VCCIO3A_DIFFIO_RX_B3_N AD mil Differential routed with B3_P J2 A98 VCCIO3A_DIFFIO_RX_B3_P AC9 1211mil Differential routed with B3_N J2 A99 VCCIO3A_DIFFIO_TX_B2_P AD9 1211mil Differential routed with B2_N J2 A100 GND Power Plane J2 A101 VCCIO3A_DIFFIO_TX_B9_F31_P AF8 1025mil Differential routed with B9_F31_N J2 A102 VCCIO3A_DIFFIO_TX_B9_F31_N AG7 1002mil Differential routed with B9_F31_P J2 A103 VCCIO3A_DIFFIO_RX_B11_F31_P AA mil Differential routed with B11_F31_N J2 A104 VCCIO3A_DIFFIO_RX_B11_F31_N AB mil Differential routed with B11_F31_P J2 A105 VCCIO3A_DIFFIO_TX_B8_P AF9 1178mil Differential routed with B8_P J2 A106 VCCIO3A_DIFFIO_TX_B8_N AG8 1140mil Differential routed with B8_N J2 A107 FPGA_VREFB3AN0 AD6 Power J2 A108 FPGA_VCCIO3A AC11/AD8 Power J2 A109 FPGA_VCCIO3A AC11/AD8 Power J2 A110 GND Power Plane Property of NovTech, Inc, under NDA Page 16 of 31

17 Table 5 J2 B side, 1 to 40 PIN SIGNAL CV F31 Ball J2 B1 GND Power Plane J2 B2 GND Power Plane J2 B3 VCCIO8A_DIFFIO_RX_T39_F31_P F9 1231mil Differential routed with T39_F31_N J2 B4 VCCIO8A_DIFFIO_RX_T39_F31_N F8 1191mil Differential routed with T39_F31_P J2 B5 GND Power Plane J2 B6 VCCIO8A_DIFFIO_TX_T4_P A11 985mil Differential routed with T4_N J2 B7 VCCIO8A_DIFFIO_TX_T4_N A10 969mil Differential routed with T4_P J2 B8 GND Power Plane J2 B9 VCCIO8A_DIFFIO_TX_T8_F31_P A9 875mil Differential routed with T8_F31_N J2 B10 VCCIO8A_DIFFIO_TX_T8_F31_N A8 859mil Differential routed with T8_F31_P J2 B11 GND Power Plane J2 B12 GND Power Plane J2 B13 VCCIO8A_DIFFIO_TX_T12_F31_P C8 896mil Differential routed with T12_F31_N J2 B14 VCCIO8A_DIFFIO_TX_T12_F31_N B8 829mil Differential routed with T12_F31_P J2 B15 GND Power Plane J2 B16 VCCIO8A_DIFFIO_TX_T6_F31_P C12 966mil Differential routed with T6_F31_N J2 B17 VCCIO8A_DIFFIO_TX_T6_F31_N B11 897mil Differential routed with T6_F31_P J2 B18 GND Power Plane J2 B19 VCCIO8A_DIFFIO_TX_T24_F31_P E8 970mil Differential routed with T24_F31_N J2 B20 VCCIO8A_DIFFIO_TX_T24_F31_N D7 909mil Differential routed with T24_F31_P J2 B21 GND Power Plane J2 B22 GND Power Plane J2 B23 VCCIO8A_DIFFIO_TX_T38_F31_P E7 932mil Differential routed with T38_F31_N J2 B24 VCCIO8A_DIFFIO_TX_T38_F31_N E6 915mil Differential routed with T38_F31_P J2 B25 GND Power Plane J2 B26 VCCIO8A_DIFFIO_TX_T20_F31_P D6 743mil Differential routed with T20_F31_N J2 B27 VCCIO8A_DIFFIO_TX_T20_F31_N C5 670mil Differential routed with T20_F31_P J2 B28 GND Power Plane J2 B29 VCCIO8A_DIFFIO_TX_T26_F31_P B2 767mil Differential routed with T26_F31_N J2 B30 VCCIO8A_DIFFIO_TX_T26_F31_N B1 724mil Differential routed with T26_F31_P J2 B31 GND Power Plane J2 B32 GND Power Plane J2 B33 VCCIO8A_DIFFIO_TX_T22_F31_P D5 654mil Differential routed with T22_F31_N J2 B34 VCCIO8A_DIFFIO_TX_T22_F31_N C4 567mil Differential routed with T22_F31_P J2 B35 GND Power Plane J2 B36 VCCIO8A_DIFFIO_TX_T32_F31_P E4 497mil Differential routed with T32_F31_N J2 B37 VCCIO8A_DIFFIO_TX_T32_F31_N D4 571mil Differential routed with T32_F31_P J2 B38 GND Power Plane J2 B39 VCCIO8A_DIFFIO_RX_T25_F31_P J7 696mil Differential routed with T25_F31_N J2 B40 VCCIO8A_DIFFIO_RX_T25_F31_N H7 587mil Differential routed with T25_F31_P Property of NovTech, Inc, under NDA Page 17 of 31

18 Table 6 J2 B side, 41 to 80 PIN SIGNAL CV F31 Ball J2 B41 GND Power Plane J2 B42 GND Power Plane J2 B43 VCCIO8A_DIFFIO_RX_T29_F31_P K12 834mil Differential routed with T29_F31_N J2 B44 VCCIO8A_DIFFIO_RX_T29_F31_N J12 920mil Differential routed with T29_F31_P J2 B45 GND Power Plane J2 B46 VCCIO8A_DIFFIO_RX_T33_F31_P K7 621mil Differential routed with T33_F31_N J2 B47 VCCIO8A_DIFFIO_RX_T33_F31_N K8 663mil Differential routed with T33_F31_P J2 B48 GMD Power Plane J2 B49 FPGA_GXB_TX_L8_F31_P H4 570mil Differential routed with L8_F31_N J2 B50 FPGA_GXB_TX_L8_F31_N H3 527mil Differential routed with L8_F31_P J2 B51 GND Power Plane J2 B52 FPGA_GXB_TX_L7_F31_P K4 510mil Differential routed with L7_F31_N J2 B53 FPGA_GXB_TX_L7_F31_N K3 469mil Differential routed with L7_F31_P J2 B54 GND Power Plane J2 B55 FPGA_GXB_TX_L6_F31_P M4 503mil Differential routed with L6_F31_N J2 B56 FPGA_GXB_TX_L6_F31_N M3 460mil Differential routed with L6_F31_P J2 B57 GND Power Plane J2 B58 FPGA_GXB_TX_L5_P P4 496mil Differential routed with L5_N J2 B59 FPGA_GXB_TX_L5_N P3 452mil Differential routed with L5_P J2 B60 GND Power Plane J2 B61 GND Power Plane J2 B62 FPGA_GXB_TX_L4_P T4 480mil Differential routed with L4_N J2 B63 FPGA_GXB_TX_L4_N T3 436mil Differential routed with L4_P J2 B64 GND Power Plane J2 B65 FPGA_GXB_TX_L3_P V4 477mil Differential routed with L3_N J2 B66 FPGA_GXB_TX_L3_N V3 432mil Differential routed with L3_P J2 B67 GND Power Plane J2 B68 FPGA_GXB_REFCLK0L_P W8 672mil Differential routed with CLK0L_N J2 B69 FPGA_GXB_REFCLK0L_N W7 627mil Differential routed with CLK0L_P J2 B70 GND Power Plane J2 B71 GND Power Plane J2 B72 FPGA_GXB_TX_L2_P Y4 491mil Differential routed with L2_N J2 B73 FPGA_GXB_TX_L2_N Y3 447mil Differential routed with L2_P J2 B74 GND Power Plane J2 B75 FPGA_GXB_TX_L1_P AB4 489mil Differential routed with L1_N J2 B76 FPGA_GXB_TX_L1_N AB3 445mil Differential routed with L1_P J2 B77 GND Power Plane J2 B78 FPGA_GXB_TX_L0_P AD4 500mil Differential routed with L0_N J2 B79 FPGA_GXB_TX_L0_N AD3 457mil Differential routed with L0_P J2 B80 GND Power Plane Property of NovTech, Inc, under NDA Page 18 of 31

19 Table 7 J2 B side, 81 to 110 PIN SIGNAL CV F31 Ball J2 B81 N.C. Future use J2 B82 FPGA_VCCH_GXBL AB6/P6 Power J2 B83 FPGA_VCCPGM AA23/J11 Power J2 B84 FPGA_VCC_AUX H10/J16 Power J2 B85 VCCIO3A_FPGA_TDO AB9 756mil J2 B86 VCCIO3A_FPGA_nCS0 AB8 1102mil Routed on NOVSOM to QSPI NOR FLASH J2 B87 VCCIO3A_FPGA_TMS V9 1165mil J2 B88 VCCIO3A_FPGA_AS_DATA3 AC7 885mil Routed on NOVSOM to QSPI NOR FLASH J2 B89 VCCIO3A_FPGA_TCK AC5 707mil J2 B90 GND Power Plane J2 B91 VCCIO3A_DIFFIO_RX_B5_P AD7 760mil Differential routed with B5_N J2 B92 VCCIO3A_DIFFIO_RX_B5_N AE7 765mil Differential routed with B5_P J2 B93 VCCIO3A_DIFFIO_TX_B16_F31_P AG2 484mil Differential routed with B16_F31_N J2 B94 VCCIO3A_DIFFIO_TX_B16_F31_N AH3 497mil Differential routed with B16_F31_P J2 B95 VCCIO3A_DIFFIO_TX_B6_P AG3 573mil Differential routed with B6_N J2 B96 VCCIO3A_DIFFIO_TX_B6_N AH4 546mil Differential routed with B6_P J2 B97 VCCIO3A_DIFFIO_RX_B7_P AF4 658mil Differential routed with B7_N J2 B98 VCCIO3A_DIFFIO_RX_B7_N AF5 684mil Differential routed with B7_P J2 B99 VCCIO3A_DIFFIO_TX_B2_N AE9 1176mil Differential routed with B2_P J2 B100 GND Power Plane J2 B101 VCCIO3A_DIFFIO_TX_B12_F31_P AF6 814mil Differential routed with B12_F31_N J2 B102 VCCIO3A_DIFFIO_TX_B12_F31_N AG6 785mil Differential routed with B12_F31_P J2 B103 VCCIO3A_DIFFIO_TX_B4_P AE mil Differential routed with B4_N J2 B104 VCCIO3A_DIFFIO_TX_B4_N AF mil Differential routed with B4_P J2 B105 VCCIO3A_DIFFIO_RX_B14_F31_P AJ1 592mil Differential routed with B14_F31_N J2 B106 VCCIO3A_DIFFIO_RX_B14_F31_N AJ2 634mil Differential routed with B14_F31_P J2 B107 VCCIO3A_DIFFIO_TX_B13_F31_P AG5 845mil Differential routed with B13_F31_N J2 B108 VCCIO3A_DIFFIO_TX_B13_F31_N AH5 871mil Differential routed with B13_F31_P J2 B109 FPGA_VCCPD3A AA10/AC10 J2 B110 GND Power Plane Property of NovTech, Inc, under NDA Page 19 of 31

20 Table 8 J3 A side, 1 to 40 PIN SIGNAL CV F31 Ball J3 A1 GND Power Plane J3 A2 VCCIO3B_DIFFIO_TX_B20_F31_P AK2 576mil Differential routed with B20_F31_N J3 A3 VCCIO3B_DIFFIO_TX_B20_F31_N AK3 589mil Differential routed with B20_F31_P J3 A4 VCCIO3B_DIFFIO_RX_B19_F31_P AA mil Differential routed with B19_F31_N J3 A5 VCCIO3B_DIFFIO_RX_B19_F31_N AB mil Differential routed with B19_F31_P J3 A6 VCCIO3B_DIFFIO_TX_B21_F31_P AJ4 609mil Differential routed with B21_F31_N J3 A7 VCCIO3B_DIFFIO_TX_B21_F31_N AK4 569mil Differential routed with B21_F31_P J3 A8 VCCIO3B_DIFFIO_RX_B22_F31_P AE mil Differential routed with B22_F31_N J3 A9 VCCIO3B_DIFFIO_RX_B22_F31_N AF13 997mil Differential routed with B22_F31_P J3 A10 VCCIO3B_DIFFIO_TX_B28_N AK8 666mil Differential routed with B28_P J3 A11 GND Power Plane J3 A12 VCCIO3B_DIFFIO_RX_B23_F31_P AD mil Differential routed with B23_F31_N J3 A13 VCCIO3B_DIFFIO_RX_B23_F31_N AE14 993mil Differential routed with B23_F31_P J3 A14 VCCIO3B_DIFFIO_TX_B29_P AJ9 629mil Differential routed with B29_N J3 A15 VCCIO3B_DIFFIO_TX_B29_N AK9 582mil Differential routed with B29_P J3 A16 VCCIO3B_DIFFIO_RX_B34_P AJ11 643mil Differential routed with B34_N J3 A17 VCCIO3B_DIFFIO_RX_B34_N AK11 597mil Differential routed with B34_P J3 A18 VCCIO3B_DIFFIO_RX_B35_P AA mil Differential routed with B35_N J3 A19 VCCIO3B_DIFFIO_RX_B35_N AA mil Differential routed with B35_P J3 A20 VCCIO3B_DIFFIO_TX_B36_P AK12 618mil Differential routed with B36_N J3 A21 GND Power Plane J3 A22 VCCIO3B_DIFFIO_RX_B31_P AF14 771mil Differential routed with B31_N J3 A23 VCCIO3B_DIFFIO_RX_B31_N AF15 769mil Differential routed with B31_P J3 A24 VCCIO3B_DIFFIO_TX_B40_P AJ14 628mil Differential routed with B40_N J3 A25 VCCIO3B_DIFFIO_TX_B40_N AK14 583mil Differential routed with B40_P J3 A26 FPGA_VCCIO3B AJ8/AJ13 Power J3 A27 FPGA_VCCIO3B AJ8/AJ13 Power J3 A28 FPGA_VCCIO3B AJ8/AJ13 Power J3 A29 FPGA_VCCPD3B4A AB18/ Power J3 A30 FPGA_VCCPD3B4A AB18/ Power J3 A31 GND Power Plane J3 A32 VCCIO4A_DIFFIO_TX_B45_P AJ16 584mil Differential routed with B45_N J3 A33 VCCIO4A_DIFFIO_TX_B45_N AK16 538mil Differential routed with B45_P J3 A34 VCCIO4A_DIFFIO_RX_B71_F31_P V mil Differential routed with B71_F31_N J3 A35 VCCIO4A_DIFFIO_RX_B71_F31_N W mil Differential routed with B71_F31_P J3 A36 VCCIO4A_DIFFIO_RX_B51_P V mil Differential routed with B51_N J3 A37 VCCIO4A_DIFFIO_RX_B51_N W mil Differential routed with B51_P J3 A38 VCCIO4A_DIFFIO_RX_B43_P V mil Differential routed with B43_N J3 A39 VCCIO4A_DIFFIO_RX_B43_N W mil Differential routed with B43_P J3 A40 VCCIO4A_DIFFIO_TX_B44_P AE16 821mil Differential routed with B44_N Property of NovTech, Inc, under NDA Page 20 of 31

21 Table 9 J3 A side, 41 to 80 PIN SIGNAL CV F31 Ball J3 A41 GND Power Plane J3 A42 VCCIO4A_DIFFIO_TX_B44_N AF16 775mil Differential routed with B44_P J3 A43 VCCIO4A_DIFFIO_RX_B50_P AJ17 640mil Differential routed with B50_N J3 A44 VCCIO4A_DIFFIO_RX_B50_N AK18 589mil Differential routed with B50_P J3 A45 VCCIO4A_DIFFIO_TX_B52_P AJ19 636mil Differential routed with B52_N J3 A46 VCCIO4A_DIFFIO_TX_B52_N AK19 588mil Differential routed with B52_P J3 A47 VCCIO4A_DIFFIO_RX_B42_P AE17 856mil Differential routed with B42_N J3 A48 VCCIO4A_DIFFIO_RX_B42_N AF18 818mil Differential routed with B42_P J3 A49 VCCIO4A_DIFFIO_RX_B47_P AA mil Differential routed with B47_N J3 A50 VCCIO4A_DIFFIO_RX_B47_N AB mil Differential routed with B47_P J3 A51 GND Power Plane J3 A52 VCCIO4A_DIFFIO_RX_B55_P AC mil Differential routed with B55_N J3 A53 VCCIO4A_DIFFIO_RX_B55_N AD17 970mil Differential routed with B55_P J3 A54 VCCIO4A_DIFFIO_RX_B63_F31_P Y mil Differential routed with B63_F31_N J3 A55 VCCIO4A_DIFFIO_RX_B63_F31_N AA mil Differential routed with B63_F31_P J3 A56 VCCIO4A_DIFFIO_RX_B58_P AE18 981mil Differential routed with B58_N J3 A57 VCCIO4A_DIFFIO_RX_B58_N AE19 985mil Differential routed with B58_P J3 A58 VCCIO4A_DIFFIO_RX_B54_P AF19 939mil Differential routed with B55_N J3 A59 VCCIO4A_DIFFIO_RX_B54_N AG20 898mil Differential routed with B54_P J3 A60 GND Power Plane J3 A61 VCCIO4A_DIFFIO_RX_B74_P AD mil Differential routed with B74_N J3 A62 VCCIO4A_DIFFIO_RX_B74_N AD mil Differential routed with B74_P J3 A63 VCCIO4A_DIFFIO_RX_B70_P AE22 975mil Differential routed with B70_N J3 A64 VCCIO4A_DIFFIO_RX_B70_N AE23 978mil Differential routed with B70_P J3 A65 VCCIO4A_DIFFIO_RX_B66_P AF23 928mil Differential routed with B66_N J3 A66 VCCIO4A_DIFFIO_RX_B66_N AF24 923mil Differential routed with B66_P J3 A67 VCCIO4A_DIFFIO_TX_B64_P AK23 823mil Differential routed with B64_N J3 A68 VCCIO4A_DIFFIO_TX_B64_N AK24 827mil Differential routed with B64_P J3 A69 VCCIO4A_DIFFIO_RX_B67_P AC mil Differential routed with B67_N J3 A70 GND Power Plane J3 A71 VCCIO4A_DIFFIO_RX_B67_N AD mil Differential routed with B67_P J3 A72 VCCIO4A_DIFFIO_RX_B79_F31_P AA mil Differential routed with B79_F31_N J3 A73 VCCIO4A_DIFFIO_RX_B79_F31_N AB mil Differential routed with B79_F31_P J3 A74 VCCIO4A_DIFFIO_TX_B65_P AJ24 922mil Differential routed with B65_F31_N J3 A75 VCCIO4A_DIFFIO_TX_B65_F31_N AJ25 934mil Differential routed with B65_P J3 A76 VCCIO4A_DIFFIO_RX_B78_P AC mil Differential routed with B78_N J3 A77 VCCIO4A_DIFFIO_RX_B78_N AC mil Differential routed with B78_P J3 A78 VCCIO4A_DIFFIO_TX_B73_P AK28 787mil Differential routed with B73_F31_N J3 A79 VCCIO4A_DIFFIO_TX_B73_F31_N AK29 796mil Differential routed with B73_P J3 A80 GND Power Plane Property of NovTech, Inc, under NDA Page 21 of 31

22 Table 10 J3 A side, 81 to 110 PIN SIGNAL CV F31 Ball J3 A81 VCCIO4A_DIFFIO_TX_B72_N AK mil Differential routed with B72_P J3 A82 VCCIO4A_DIFFIO_TX_B72_P AJ mil Differential routed with B72_N J3 A83 VCCIO4A_DIFFIO_TX_B68_N AK mil Differential routed with B687_F31_P J3 A84 VCCIO4A_DIFFIO_TX_B68_F31_P AJ mil Differential routed with B68_N J3 A85 VCCIO4A_DIFFIO_TX_B60_N AK mil Differential routed with B60_P J3 A86 VCCIO4A_DIFFIO_TX_B60_P AK mil Differential routed with B60_N J3 A87 VCCIO4A_DIFFIO_TX_B53_N AJ mil Differential routed with B53_P J3 A88 VCCIO4A_DIFFIO_TX_B53_P AJ mil Differential routed with B53_N J3 A89 VCCIO5A_DIFFIO_RX_R2_N AC mil Differential routed with R2_P J3 A90 GND Power Plane J3 A91 VCCIO5A_DIFFIO_RX_R2_P AD mil Differential routed with R2_N J3 A92 VCCIO5A_DIFFIO_RX_R9_F31_N AB mil Differential routed with R9_F31_P J3 A93 VCCIO5A_DIFFIO_RX_R9_F31_P AA mil Differential routed with R9_F31_N J3 A94 VCCIO5A_DIFFIO_RX_R8_N AB mil Differential routed with R8_P J3 A95 VCCIO5A_DIFFIO_RX_R8_P AB mil Differential routed with R8_N J3 A96 VCCIO5A_DIFFIO_TX_R3_N AH mil Differential routed with R3_P J3 A97 VCCIO5A_DIFFIO_TX_R3_P AJ mil Differential routed with R3_N J3 A98 VCCIO5A_DIFFIO_RX_R13_F31_P V mil Differential routed with R13_F31_N J3 A99 VCCIO5A_DIFFIO_RX_R13_F31_N W mil Differential routed with R13_F31_P J3 A100 GND Power Plane J3 A101 VCCIO5A_DIFFIO_RX_R15_F31_P AD mil Differential routed with R15_F31_N J3 A102 VCCIO5A_DIFFIO_RX_R15_F31_N AC mil Differential routed with R15_F31_P J3 A103 VCCIO5A_DIFFIO_RX_R4_N Y mil Differential routed with R4_P J3 A104 VCCIO5A_DIFFIO_RX_R4_P W mil Differential routed with R4_N J3 A105 FPGA_VCCIO4A AA17/ Power J3 A106 FPGA_VCCIO4A AA17/ Power J3 A107 FPGA_VCCIO4A AA17/ Power J3 A108 FPGA_VCCIO4A AA17/ Power J3 A109 FPGA_VREFB4AN0 Ak17 Power J3 A110 GND Power Plane Property of NovTech, Inc, under NDA Page 22 of 31

23 Table 11 J3 B side, 1 to 40 PIN SIGNAL CV F31 Ball J3 B1 GND Power Plane J3 B2 VCCIO3B_DIFFIO_TX_B25_P AJ6 491mil Differential routed with B25_N J3 B3 VCCIO3B_DIFFIO_TX_B25_N AJ7 497mil Differential routed with B25_P J3 B4 VCCIO3B_DIFFIO_RX_B27_P AB mil Differential routed with B27_N J3 B5 VCCIO3B_DIFFIO_RX_B27_N AC14 960mil Differential routed with B27_P J3 B6 VCCIO3B_DIFFIO_RX_B18_F31_P AF11 870mil Differential routed with B18_F31_N J3 B7 VCCIO3B_DIFFIO_RX_B18_F31_N AG11 775mil Differential routed with B18_F31_P J3 B8 VCCIO3B_DIFFIO_TX_B24_F31_P AJ5 413mil Differential routed with B24_F31_N J3 B9 VCCIO3B_DIFFIO_TX_B24_F31_N AK6 356mil Differential routed with B24_F31_P J3 B10 VCCIO3B_DIFFIO_TX_B28_P AK7 571mil Differential routed with B28_N J3 B11 GND Power Plane J3 B12 VCCIO3B_DIFFIO_TX_B32_P AH7 435mil Differential routed with B32_N J3 B13 VCCIO3B_DIFFIO_TX_B32_N AH8 436mil Differential routed with B32_P J3 B14 VCCIO3B_DIFFIO_TX_B17_F31_P AG10 509mil Differential routed with B17_F31_N J3 B15 VCCIO3B_DIFFIO_TX_B17_F31_N AH9 433mil Differential routed with B17_F31_P J3 B16 VCCIO3B_DIFFIO_TX_B33_P AH10 441mil Differential routed with B33_N J3 B17 VCCIO3B_DIFFIO_TX_B33_N AJ10 394mil Differential routed with B33_P J3 B18 VCCIO3B_DIFFIO_RX_B39_P W15 916mil Differential routed with B39_N J3 B19 VCCIO3B_DIFFIO_RX_B39_N Y mil Differential routed with B39_P J3 B20 VCCIO3B_DIFFIO_TX_B36_N AK13 572mil Differential routed with B36_P J3 B21 GND Power Plane J3 B22 VCCIO3B_DIFFIO_TX_B37_P AH12 423mil Differential routed with B37_N J3 B23 VCCIO3B_DIFFIO_TX_B37_N AJ12 381mil Differential routed with B37_P J3 B24 VCCIO3B_DIFFIO_RX_B26_P AG12 459mil Differential routed with B26_N J3 B25 VCCIO3B_DIFFIO_RX_B26_N AG13 457mil Differential routed with B26_P J3 B26 VCCIO3B_DIFFIO_RX_B30_P AH13 419mil Differential routed with B30_N J3 B27 VCCIO3B_DIFFIO_RX_B30_N AH14 419mil Differential routed with B30_P J3 B28 VCCIO3B_DIFFIO_RX_B38_P AG15 423mil Differential routed with B38_N J3 B29 VCCIO3B_DIFFIO_RX_B38_N AH15 418mil Differential routed with B38_P J3 B30 FPGA_VREFB3BN0 AJ15 Power J3 B31 GND Power Plane J3 B32 VCCIO4A_DIFFIO_TX_B41_N AG17 580mil Differential routed with B41_P J3 B33 VCCIO4A_DIFFIO_TX_B41_P AG16 518mil Differential routed with B41_N J3 B34 VCCIO4A_DIFFIO_TX_B48_N AH18 560mil Differential routed with B48_P J3 B35 VCCIO4A_DIFFIO_TX_B48_P AH17 496mil Differential routed with B48_N J3 B36 VCCIO4A_DIFFIO_RX_B59_P Y17 764mil Differential routed with B59_N J3 B37 VCCIO4A_DIFFIO_RX_B59_N AA18 732mil Differential routed with B59_P J3 B38 VCCIO4A_DIFFIO_TX_B49_P AG18 511mil Differential routed with B49_F31_N J3 B39 VCCIO4A_DIFFIO_TX_B49_F31_N AH19 461mil Differential routed with B49_P J3 B40 VCCIO4A_DIFFIO_RX_B46_N AH20 444mil Differential routed with B46_P Property of NovTech, Inc, under NDA Page 23 of 31

24 Table 12 J3 B side, 41 to 80 PIN SIGNAL CV F31 Ball J3 B41 GND Power Plane J3 B42 VCCIO4A_DIFFIO_RX_B46_P AG21 488mil Differential routed with B46_N J3 B43 VCCIO4A_DIFFIO_TX_B57_P AG22 471mil Differential routed with B57_F31_N J3 B44 VCCIO4A_DIFFIO_TX_B57_F31_N AH22 427mil Differential routed with B57_P J3 B45 VCCIO4A_DIFFIO_TX_B61_N AJ22 376mil Differential routed with B61_P J3 B46 VCCIO4A_DIFFIO_TX_B61_P AH23 429mil Differential routed with B61_N J3 B47 VCCIO4A_DIFFIO_RX_B62_P AF20 563mil Differential routed with B62_N J3 B48 VCCIO4A_DIFFIO_RX_B62_N AF21 564mil Differential routed with B62_P J3 B49 VCCIO4A_DIFFIO_RX_B75_P Y19 838mil Differential routed with B75_N J3 B50 VCCIO4A_DIFFIO_RX_B75_N AA20 783mil Differential routed with B75_P J3 B51 GND Power Plane J3 B52 VCCIO4A_DIFFIO_TX_B56_P AG23 489mil Differential routed with B56_N J3 B53 VCCIO4A_DIFFIO_TX_B56_N AH24 431mil Differential routed with B56_P J3 B54 VCCIO4A_DIFFIO_TX_B69_P AG25 471mil Differential routed with B69_N J3 B55 VCCIO4A_DIFFIO_TX_B69_N AH25 423mil Differential routed with B69_P J3 B56 VCCIO4A_DIFFIO_TX_B76_F31_P AG26 466mil Differential routed with B76_N J3 B57 VCCIO4A_DIFFIO_TX_B76_N AH27 492mil Differential routed with B76_F31_P J3 B58 VCCIO4A_DIFFIO_TX_B80_P AD24 634mil Differential routed with B80_N J3 B59 VCCIO4A_DIFFIO_TX_B80_N AE24 583mil Differential routed with B80_P J3 B60 GND Power Plane J3 B61 VCCIO4A_DIFFIO_TX_B77_P AF25 591mil Differential routed with B77_N J3 B62 VCCIO4A_DIFFIO_TX_B77_N AF26 590mil Differential routed with B77_P J3 B63 VCCIO5A_DIFFIO_TX_R1_N AH28 434mil Differential routed with R1_P J3 B64 VCCIO5A_DIFFIO_TX_R1_P AG27 512mil Differential routed with R1_N J3 B65 VCCIO5A_DIFFIO_TX_R12_F31_P AG28 491mil Differential routed with R12_F31_N J3 B66 VCCIO5A_DIFFIO_TX_R12_F31_N AF28 535mil Differential routed with R12_F31_P J3 B67 VCCIO5A_DIFFIO_TX_R10_F31_P AE27 653mil Differential routed with R10_F31_N J3 B68 VCCIO5A_DIFFIO_TX_R10_F31_N AE28 630mil Differential routed with R10_F31_P J3 B69 VCCIO5A_DIFFIO_TX_R5_P AE26 747mil Differential routed with R5_N J3 B70 GND Power Plane J3 B71 VCCIO5A_DIFFIO_TX_R5_N AD27 727mil Differential routed with R5_P J3 B72 VCCIO5B_DIFFIO_RX_R21_N AB27 776mil Differential routed with R21_P J3 B73 VCCIO5B_DIFFIO_RX_R21_P AA26 855mil Differential routed with R21_N J3 B74 VCCIO5B_DIFFIO_TX_R20_F31_P AB28 892mil Differential routed with R20_F31_N J3 B75 VCCIO5B_DIFFIO_TX_R20_F31_N AA28 886mil Differential routed with R20_F31_P J3 B76 VCCIO5B_DIFFIO_RX_R23_N Y27 950mil Differential routed with R23_P J3 B77 VCCIO5B_DIFFIO_RX_R23_P Y mil Differential routed with R23_N J3 B78 VCCIO5B_DIFFIO_RX_R17_F31_P W mil Differential routed with R17_F31_N J3 B79 VCCIO5B_DIFFIO_RX_R17_F31_N V mil Differential routed with R17_F31_P J3 B80 GND Power Plane Property of NovTech, Inc, under NDA Page 24 of 31

25 Table 13 J3 B side, 81 to 110 PIN SIGNAL CV F31 Ball J3 B81 VCCIO5A_DIFFIO_TX_R14_F31_P AF29 932mil Differential routed with R14_F31_N J3 B82 VCCIO5A_DIFFIO_TX_R14_F31_N AF30 867mil Differential routed with R14_F31_P J3 B83 VCCIO5B_DIFFIO_TX_R22_P AE29 996mil Differential routed with R22_N J3 B84 VCCIO5B_DIFFIO_TX_R22_N AD29 979mil Differential routed with R22_P J3 B85 VCCIO5A_DIFFIO_TX_R16_F31_P AH30 919mil Differential routed with R16_F31_N J3 B86 VCCIO5A_DIFFIO_TX_R16_F31_N AG30 931mil Differential routed with R16_F31_P J3 B87 VCCIO5B_DIFFIO_TX_R18_F31_P AC mil Differential routed with R18_F31_N J3 B88 VCCIO5B_DIFFIO_TX_R18_F31_N AC mil Differential routed with R18_F31_P J3 B89 VCCIO5B_DIFFIO_TX_R24_P AD mil Differential routed with R24_N J3 B90 GND Power Plane J3 B91 VCCIO5B_DIFFIO_TX_R24_N AC mil Differential routed with R24_P J3 B92 VCCIO5B_DIFFIO_RX_R19_F31_P AB mil Differential routed with R19_F31_N J3 B93 VCCIO5B_DIFFIO_RX_R19_F31_N AA mil Differential routed with R19_F31_P J3 B94 VCCIO5A_DIFFIO_TX_R7_P AA mil Differential routed with R27_N J3 B95 VCCIO5A_DIFFIO_TX_R7_N AB mil Differential routed with R27_P J3 B96 VCCIO5A_DIFFIO_RX_R11_F31_P Y mil Differential routed with R11_F31_N J3 B97 VCCIO5A_DIFFIO_RX_R11_F31_N Y mil Differential routed with R11_F31_P J3 B98 VCCIO5A_DIFFIO_RX_R6_P W mil Differential routed with R6_N J3 B99 VCCIO5A_DIFFIO_RX_R6_N W mil Differential routed with R6_P J3 B100 GND Power Plane J3 B101 FPGA_VCCPD5A V22/V24 Power J3 B102 FPGA_VCCPD5B U23 Power J3 B103 FPGA_VREFB5AN0 AC24 Power J3 B104 FPGA_VREFB5BN0 AA29 Power J3 B105 FPGA_VCCIO5B AA27/AE30 Power J3 B106 FPGA_VCCIO5B AA27/AE30 Power J3 B107 FPGA_VCCIO5A AB24 Power J3 B108 FPGA_VCCIO5A AB24 Power J3 B109 FPGA_VCCIO5A AB24 Power J3 B110 GND Power Plane Property of NovTech, Inc, under NDA Page 25 of 31

26 Table 14 J4 A side, 1 to 40 PIN SIGNAL CV F31 Ball J4 A1 GND Power Plane J4 A2 VCC_HPS G23/L16 Power Plane J4 A3 VCC_HPS G23/L16 Power Plane J4 A4 VCC_HPS G23/L16 Power Plane J4 A5 VCC_HPS G23/L16 Power Plane J4 A6 VCC_HPS G23/L16 Power Plane J4 A7 VCC_HPS G23/L16 Power Plane J4 A8 VCC_HPS G23/L16 Power Plane J4 A9 VCC_HPS G23/L16 Power Plane J4 A10 VCC_HPS G23/L16 Power Plane J4 A11 GND Power Plane J4 A12 FPGA_VCC M9/M11 Power Plane J4 A13 FPGA_VCC M9/M11 Power Plane J4 A14 FPGA_VCC M9/M11 Power Plane J4 A15 FPGA_VCC M9/M11 Power Plane J4 A16 FPGA_VCC M9/M11 Power Plane J4 A17 FPGA_VCC M9/M11 Power Plane J4 A18 FPGA_VCC M9/M11 Power Plane J4 A19 FPGA_VCC M9/M11 Power Plane J4 A20 FPGA_VCC M9/M11 Power Plane J4 A21 GND Power Plane J4 A22 VCCIO6A_HPS_GPIO1 J mil J4 A23 VCCIO6A_HPS_GPIO4 N mil J4 A24 VCCIO6A_HPS_GPIO5 P mil J4 A25 VCCIO6A_HPS_GPIO0 M mil J4 A26 VCCIO6A_HPS_GPIO3 M mil J4 A27 VCCIO6A_HPS_GPIO2 N mil J4 A28 VCCIO6A_HPS_GPIO6 P mil J4 A29 VCCIO6A_HPS_GPIO8 T mil J4 A30 VCCIO6A_HPS_GPIO13 Y mil J4 A31 GND Power Plane J4 A32 VCCIO6A_HPS_GPIO12 V mil J4 A33 VCCIO6A_HPS_GPIO9 U mil J4 A34 VCCIO6A_HPS_GPIO10 T mil J4 A35 VCCIO6A_HPS_GPIO11 U mil J4 A36 VCCIO6A_HPS_GPIO7 V mil J4 A37 VCCIO7A_HPS_I2C0_SCL D mil Routed on NOVSOM to EEPROM J4 A38 VCCIO7A_HPS_I2C0_SDA C mil Routed on NOVSOM to EEPROM J4 A39 VCCIO7A_HPS_UART0_TX G mil J4 A40 VCCIO7A_HPS_UART0_RX B mil Property of NovTech, Inc, under NDA Page 26 of 31

27 Table 15 J4 A side, 41 to 80 PIN SIGNAL CV F31 Ball J4 A41 GND Power Plane J4 A42 VCCIO7A_HPS_SPIM0_MISO B mil J4 A43 VCCIO7A_HPS_SPIM0_CLK A mil J4 A44 VCCIO7A_HPS_SPIM0_SS0 H mil J4 A45 VCCIO7A_HPS_SPIM0_MOSI C mil J4 A46 N.C J4 A47 N.C J4 A48 N.C. J4 A49 N.C. J4 A50 VCCIO7B_HPS_NAND_RB2 x 630mil Routed from NAND chip to B2B J4 A51 GND Power Plane J4 A52 VCCIO7B_HPS_NAND_DQ0 A mil Routed on NOVSOM to NAND FLASH J4 A53 VCCIO7B_HPS_NAND_DQ1 E mil Routed on NOVSOM to NAND FLASH J4 A54 VCCIO7B_HPS_NAND_DQ2 B mil Routed on NOVSOM to NAND FLASH J4 A55 VCCIO7B_HPS_NAND_DQ3 K mil Routed on NOVSOM to NAND FLASH J4 A56 VCCIO7B_HPS_NAND_DQ4 A20 945mil Routed on NOVSOM to NAND FLASH J4 A57 VCCIO7B_HPS_NAND_DQ5 G mil Routed on NOVSOM to NAND FLASH J4 A58 VCCIO7B_HPS_NAND_DQ6 B mil Routed on NOVSOM to NAND FLASH J4 A59 VCCIO7B_HPS_NAND_DQ7 B18 966mil Routed on NOVSOM to NAND FLASH J4 A60 GND Power Plane J4 A61 VCCIO7B_HPS_QSPI_IO1 H mil Routed on NOVSOM to QSPI NOR FLASH J4 A62 VCCIO7B_HPS_QSPI_IO2 A mil Routed on NOVSOM to QSPI NOR FLASH J4 A63 VCCIO7B_HPS_QSPI_SS0 A mil Routed on NOVSOM to QSPI NOR FLASH J4 A64 VCCIO7C_HPS_SDMMC_PWREN B17 971mil J4 A65 VCCIO7C_HPS_SDMMC_D1 C mil Routed on NOVSOM to SD Slot J4 A66 VCCIO7C_HPS_SDMMC_CMD F mil Routed on NOVSOM to SD Slot J4 A67 VCCIO7C_HPS_SDMMC_D0 G mil Routed on NOVSOM to SD Slot J4 A68 VCCIO7C_HPS_SDMMC_D3 B mil Routed on NOVSOM to SD Slot J4 A69 VCCIO7C_HPS_SDMMC_CLK A mil Routed on NOVSOM to SD Slot J4 A70 GND Power Plane J4 A71 VCCIO7D_HPS_RGMII0_RXD0 A15 824mil J4 A72 VCCIO7D_HPS_RGMII0_TX_CTL B15 870mil J4 A73 VCCIO7D_HPS_RGMII0_RXD1 C15 932mil J4 A74 VCCIO7D_HPS_RGMII0_RXD3 A14 836mil J4 A75 VCCIO7D_HPS_RGMII0_RX_CLK N mil J4 A76 VCCIO7D_HPS_RGMII0_RXD2 E14 992mil J4 A77 VCCIO7D_HPS_RGMII0_TXD3 D14 928mil J4 A78 VCCIO7D_HPS_RGMII0_MDIO C14 886mil J4 A79 FPGA_VCCIO8A A7/B4 J4 A80 GND Power Plane Property of NovTech, Inc, under NDA Page 27 of 31

28 Table 16 J4 A side, 81 to 110 PIN SIGNAL CV F31 Ball J4 A81 FPGA_VCCIO8A A7/B4 J4 A82 FPGA_VCCIO8A A7/B4 J4 A83 FPGA_VCCIO8A A7/B4 J4 A84 VCCIO9A_FPGA_CONF_DONE F3 1558mil J4 A85 VCCIO9A_FPGA_MSEL0 L8 1386mil J4 A86 VCCIO9A_FPGA_MSEL1 K6 1466mil J4 A87 VCCIO9A_FPGA_MSEL2 G6 1167mil J4 A88 VCCIO9A_FPGA_MSEL3 L7 1344mil J4 A89 VCCIO9A_FPGA_MSEL4 L9 1361mil J4 A90 GND Power Plane J4 A91 VCCIO8A_DIFFIO_RX_T1_P H mil Differential routed with T1_N J4 A92 VCCIO8A_DIFFIO_RX_T1_N G mil Differential routed with T1_P J4 A93 GND Power Plane J4 A94 VCCIO8A_DIFFIO_RX_T19_F31_P E mil Differential routed with T19_F31_N J4 A95 VCCIO8A_DIFFIO_RX_T19_F31_N D12 947mil Differential routed with T19_F31_P J4 A96 GND Power Plane J4 A97 VCCIO8A_DIFFIO_RX_T23_F31_P F mil Differential routed with T23_F31_N J4 A98 VCCIO8A_DIFFIO_RX_T23_F31_N E mil Differential routed with T23_F31_P J4 A99 GND Power Plane J4 A100 GND Power Plane J4 A101 GND Power Plane J4 A102 VCCIO8A_DIFFIO_TX_T14_F31_P C10 944mil Differential routed with T14_F31_N J4 A103 VCCIO8A_DIFFIO_TX_T14_F31_N C9 937mil Differential routed with T14_F31_P J4 A104 GND Power Plane J4 A105 VCCIO8A_DIFFIO_RX_T35_F31_P G mil Differential routed with T35_F31_N J4 A106 VCCIO8A_DIFFIO_RX_T35_F31_N F mil Differential routed with T35_F31_P J4 A107 GND Power Plane J4 A108 VCCIO8A_DIFFIO_RX_T11_F31_P E9 1184mil Differential routed with T11_F31_N J4 A109 VCCIO8A_DIFFIO_RX_T11_F31_N D9 1126mil Differential routed with T11_F31_P J4 A110 GND Power Plane Property of NovTech, Inc, under NDA Page 28 of 31

29 Table 17 J4 B side, 1 to 40 PIN SIGNAL CV F31 Ball J4 B1 GND Power Plane J4 B2 DDR_VTT_VCNTL x Power, apply 3.3V for VTT solution J4 B3 DDR_VTT_VCNTL x Power, apply 3.3V for VTT solution J4 B4 DDR_VTT_VCNTL x Power, apply 3.3V for VTT solution J4 B5 DDR_PS D28/G29 Power J4 B6 DDR_PS D28/G29 Power J4 B7 DDR_PS D28/G29 Power J4 B8 DDR_PS D28/G29 Power J4 B9 DDR_PS D28/G29 Power J4 B10 DDR_PS D28/G29 Power J4 B11 GND Power Plane J4 B12 DDR_PS D28/G29 Power J4 B13 DDR_PS D28/G29 Power J4 B14 DDR_PS D28/G29 Power J4 B15 VCCPLL_HPS L21 Power J4 B16 VCC_AUX_SHARED J21 Power J4 B17 VCCRSTCLK_HPS J20 Power J4 B18 VREFB7A7B7C7DN0_HPS E22 Power J4 B19 VCCPD7A_HPS K19 Power J4 B20 VCCPD7B_HPS K18 Power J4 B21 GND Power Plane J4 B22 VCCPD7C_HPS J17 Power J4 B23 VCCPD7D_HPS K16 Power J4 B24 VCCPD6A6B_HPS M21/N22 Power J4 B25 VCCIO7A_HPS F22/H21 Power J4 B26 VCCIO7B_HPS E20/G19 Power J4 B27 VCCIO7C_HPS D18 Power J4 B28 VCCIO7D_HPS H16 Power J4 B29 VCCIO7A_HPS_TCK H mil J4 B30 VCCIO7A_HPS_PORSEL F mil J4 B31 GND Power Plane J4 B32 VCCIO7A_HPS_nPOR F mil J4 B33 VCCIO7A_HPS_TMS A29 985mil J4 B34 VCCIO7A_HPS_TRST A28 910mil J4 B35 VCCIO7A_HPS_TDO B mil J4 B36 VCCIO7A_HPS_TDI B27 951mil J4 B37 VCCIO7A_HPS_nRST C mil J4 B38 VCCIO7A_HPS_CLK2 F mil J4 B39 VCCIO7A_HPS_TRACE_CLK B mil J4 B40 VCCIO7A_HPS_TRACE_D1 C mil Property of NovTech, Inc, under NDA Page 29 of 31

30 Table 18 J4 B side, 41 to 80 PIN SIGNAL CV F31 Ball J4 B41 GND Power Plane J4 B42 VCCIO7A_HPS_TRACE_D0 B25 878mil J4 B43 VCCIO7A_HPS_TRACE_D6 C mil J4 B44 VCCIO7A_HPS_TRACE_D4 A24 818mil J4 B45 VCCIO7A_HPS_TRACE_D2 A25 770mil J4 B46 VCCIO7A_HPS_TRACE_D7 E23 973mil J4 B47 VCCIO7A_HPS_TRACE_D3 H mil J4 B48 VCCIO7A_HPS_TRACE_D5 G mil J4 B49 VCCIO7A_HPS_CAN0_RX E24 893mil J4 B50 VCCIO7A_HPS_CAN0_TX D24 857mil J4 B51 GND Power Plane J4 B52 VCCIO7B_HPS_NAND_CE2 x 134mil Routed from NAND chip to B2B J4 B53 VCCIO7B_HPS_NAND_CE F mil Routed on NOVSOM to NAND FLASH J4 B54 VCCIO7B_HPS_NAND_RB F mil Routed on NOVSOM to NAND FLASH J4 B55 VCCIO7B_HPS_NAND_RE F21 930mil Routed on NOVSOM to NAND FLASH J4 B56 VCCIO7B_HPS_NAND_CLE J mil Routed on NOVSOM to NAND FLASH J4 B57 VCCIO7B_HPS_NAND_ALE H mil Routed on NOVSOM to NAND FLASH J4 B58 VCCIO7B_HPS_NAND_WE D20 778mil Routed on NOVSOM to NAND FLASH J4 B59 VCCIO7B_HPS_NAND_WP D21 779mil Routed on NOVSOM to NAND FLASH J4 B60 GND Power Plane J4 B61 VCCIO7B_HPS_QSPI_IO0 C mil Routed on NOVSOM to QSPI NOR FLASH J4 B62 VCCIO7B_HPS_QSPI_SS1 C19 765mil J4 B63 VCCIO7B_HPS_QSPI_IO3 E mil Routed on NOVSOM to QSPI NOR FLASH J4 B64 VCCIO7B_HPS_QSPI_CLK D mil Routed on NOVSOM to QSPI NOR FLASH J4 B65 VCCIO7C_HPS_SDMMC_D5 C18 709mil J4 B66 VCCIO7C_HPS_SDMMC_D6 G17 872mil J4 B67 VCCIO7C_HPS_SDMMC_D7 E18 783mil J4 B68 VCCIO7C_HPS_SDMMC_CLK_IN E17 764mil J4 B69 VCCIO7C_HPS_SDMMC_D2 D mil Routed on NOVSOM to SD Slot J4 B70 GND Power Plane J4 B71 VCCIO7C_HPS_SDMMC_D4 H17 906mil J4 B72 VCCIO7D_HPS_RGMII0_TX_CLK F16 806mil J4 B73 VCCIO7D_HPS_RGMII0_RX_CTL M mil J4 B74 VCCIO7D_HPS_RGMII0_TXD2 D16 727mil J4 B75 VCCIO7D_HPS_RGMII0_TXD0 E16 754mil J4 B76 VCCIO7D_HPS_RGMII0_TXD1 G16 826mil J4 B77 VCCIO7D_HPS_RGMII0_MDC D15 694mil J4 B78 FPGA_VCCPD8A K11/K13.. J4 B79 FPGA_VCCPD8A K11/K13.. J4 B80 GND Power Plane Property of NovTech, Inc, under NDA Page 30 of 31

31 Table 19 J4 B side, 81 to 110 PIN SIGNAL CV F31 Ball J4 B81 FPGA_VCCIO8A A7/B4 Power J4 B82 VCCBAT H9 Power J4 B83 FPGA_VREFB8AN0 B10 Power J4 B84 VCCIO9A_FPGA_nCONFIG J5 1967mil J4 B85 VCCIO9A_FPGA_nSTATUS F4 1552mil J4 B86 VCCIO9A_FPGA_nCE G5 1619mil J4 B87 GND Power Plane J4 B88 VCCIO8A_DIFFIO_RX_T13_F31_P H14 991mil Differential routed with T13_F31_N J4 B89 VCCIO8A_DIFFIO_RX_T13_F31_N G13 950mil Differential routed with T13_F31_P J4 B90 GND Power Plane J4 B91 GND Power Plane J4 B92 VCCIO8A_DIFFIO_RX_T21_F31_P H13 947mil Differential routed with T21_F31_N J4 B93 VCCIO8A_DIFFIO_RX_T21_F31_N H12 939mil Differential routed with T21_F31_P J4 B94 GND Power Plane J4 B95 VCCIO8A_DIFFIO_RX_T5_F31_P F15 866mil Differential routed with T5_F31_N J4 B96 VCCIO8A_DIFFIO_RX_T5_F31_N F14 869mil Differential routed with T5_F31_P J4 B97 GND Power Plane J4 B98 VCCIO8A_DIFFIO_TX_T2_F31_P B13 734mil Differential routed with T2_F31_N J4 B99 VCCIO8A_DIFFIO_TX_T2_F31_N A13 691mil Differential routed with T2_F31_P J4 B100 GND Power Plane J4 B101 GND Power Plane J4 B102 VCCIO8A_DIFFIO_RX_T3_F31_P C13 818mil Differential routed with T3_F31_N J4 B103 VCCIO8A_DIFFIO_RX_T3_F31_N B12 769mil Differential routed with T3_F31_P J4 B104 GND Power Plane J4 B105 VCCIO8A_DIFFIO_RX_T15_F31_P F mil Differential routed with T15_F31_N J4 B106 VCCIO8A_DIFFIO_RX_T15_F31_N E13 989mil Differential routed with T15_F31_P J4 B107 GND Power Plane J4 B108 VCCIO8A_DIFFIO_RX_T7_F31_P D11 984mil Differential routed with T7_F31_N J4 B109 VCCIO8A_DIFFIO_RX_T7_F31_N D mil Differential routed with T7_F31_P J4 B110 GND Power Plane Property of NovTech, Inc, under NDA Page 31 of 31