DDR2: The New DRAM Standard

Transcription

1 DD: The New DRAM Standard Summary Memory has evolved significantly over the years because of die shrinks, density increases, speed improvements, and other advances inspired by market demands. As a result, technologies such as SDR and DDR SDRAM are becoming outdated in favor of newer architectures. The current DRAM standard is DD, which boasts a number of advantages over its predecessors. Tom Kinsley Enabling Applications Engineer, Server Segment 006 Micron Technology, Inc. All rights reserved

2 DD: The New DRAM Standard Taking the Next Step Historically DRAM manufacturers have introduced a new architecture every four to five years. They have also performed die and process shrinks about every one to two years. This is partly due to the constant demand for higherspeed, higher-density memory devices, and partly due to the competitive nature of the DRAM industry. Micron developed its first DRAM almost 30 years ago. The original product was a simple device that consisted of a few asynchronous control inputs, address pins, and I/O lines. Shortly thereafter, in the late 1970s, enhanced, central processing units (CPUs) began to flood the market and soon became central to most PCs. Then Apple and IBM introduced their unique versions of personal computers, and the challenge was on for the DRAM industry to keep pace by improving memory designs. It wasn t long before the need for higher performance created demand for an improved DRAM architecture. A Push from the Market The lucrative emerging computer industry generated intense competition, with the main players creating faster computers with additional functions and better graphics all of which required more memory. This highly charged, competitive market which continually produced faster and more sophisticated computers became well established, as new computer companies opened up worldwide. The original memory designs were not suitable for the new computers. It wasn t long before the need for higher performance created demand for an improved DRAM architecture. What began as fast page mode (FPM) DRAM evolved into extended data-out (EDO) DRAM in the late 1980s. By the middle of the 1990s, the preferred architecture was synchronous DRAM (SDR). Over the next few years, as the new mainstay for the majority of personal computers, SDRAM technology advanced from initial speeds of PC66 (clock speed of 66 MHz) to PC100 (100 MHz) and PC133 (133 MHz). The rapid increase in processor speeds quickly became incompatible with standard SDR SDRAM. 006 Micron Technology, Inc. All rights reserved. Page

3 DD: The New DRAM Standard DDR SDRAM A year later, in 000, double data rate SDRAM was introduced. DDR SDRAM, which provides data on both the rising and falling clock edges, operates at more than twice the speed of the fastest SDR SDRAM device. This advancement triggered yet another surge in technology upgrades. DD SDRAM Second generation DDR SDRAM represents a significant advancement. It achieves extraordinary performance and provides numerous benefits over previous DRAM architectures. This technology of the future supports peak bandwidths in traditional 64-bit wide modules up to 6.4 GB/s. At the component level, this equates to an amazing transfer rate of 800 bits per second, per pin. Additionally, the newly introduced fully buffered DIMMs (FB- DIMMs), which use DD components, support peak channel bandwidths of 9.6 GB/s. With the phenomenal benefits that DD offers as a high-volume, cost-effective solution, it is now the memory of choice, displacing DDR and SDRAM. 7GB 6.4GB/s 6GB 5GB 4GB GB/s (64-bit Bus) 3GB GB 1GB 51MB/s SDR DDR DD Technology Figure Micron Technology, Inc. All rights reserved. Page 3

4 DD: The New DRAM Standard Peak Bandwidth Bandwidth equates to throughput and performance, and performance can also be related to low power consumption. For memory, peak bandwidth equals bytes per second (B/s). The simple way to calculate this is to first determine the bits per second, per pin. DD outperforms other memory architectures, yet consumes substantially less power. For DD, the data transfer rate (or bits per second) is twice that of the device input clock rate. For example, if the clock rate is approximately 333 MHz, the data transfer rate would be about double, or about 667Mb per second, per pin. However, the memory throughput encompasses all pins on the bus, not just a single device pin. In this case, if the data bus is 64 bits wide, multiply 667 Mb/s by 64 bits to get Gb/s. Most engineers refer to bandwidth in bytes per second, so if you divide gigabits by 8, it equals 5.3 GB/s. DD outperforms other memory architectures, yet consumes substantially less power. The maximum bandwidth of a 64-bit wide DDR400 module is 3. GB/s, but a 64-bit wide DD module can support a peak bandwidth of 6.4 GB/s which is twice as fast. A comparison of the same modules running at 3. GB/s shows that DD modules will consume about 60 percent less power than DDR400 modules (see Figure ) GB/s 7GB/s Watts/GB per second GB/s.6GB/s 3.GB/s 5.3GB/s 6GB/s 5GB/s 4GB/s 3GB/s GB/s 1GB/s SDR (3.3V) DDR (.5V) DD (1.8V) Technology Figure 006 Micron Technology, Inc. All rights reserved. Page 4

5 DD: The New DRAM Standard New Features Wider Bus The DD core has a 4n-prefetch, which makes the internal bus four times as wide as the external bus and reduces the internal array cycle time. This makes the DD internal bus run slower compared to the internal DDR bus. COL0,COL1 4n/Prefetch READ LATCH MUX DATA DQS GENERATOR To external bus Outputs for READ cycles 4 64 bit internal bus to the core array INPUT REGISTERS WRITE FIFO & DRIVERS 8 MASK Strobes From external bus Inputs for WRITE cycles Internal CK, CK# CK OUT CK IN 64 DATA DQ0 - DQ DATA Figure 3 More Banks All DD devices have at least four internal banks, but the higher-density devices 1Gb and above have eight internal banks. Having more banks enables the memory controller with extreme flexibility when it comes to storing or accessing data. With more banks available, the page-to-hit ratio is also improved. 006 Micron Technology, Inc. All rights reserved. Page 5

6 DD: The New DRAM Standard With all eight banks open, the probability of a page hit is twice as great when compared to DDR. Interleaving Servers or networking applications frequently access random data that could be stored in any of the many banks. The ability to interleave between banks simultaneously is a tremendous advantage for applications accessing random data. This is significant because bank interleaving is extremely effective for concurrent operations and hides the timing overhead that may be required for opening and closing each individual bank. Increased Page Hits Having additional banks in a desktop or notebook helps increase the number of page hits. Often, these types of applications utilize somewhat sequential data that is cached in memory. A page hit means the requested data was found in a bank that was already open and the data is immediately available, without the time required to open a new bank. In high-density DD, eight banks are available. With all eight banks open, the probability of a page hit is twice as great when compared to DDR. BANK 7 BANK 6 BANK 5 BANK 4 BANK 3 BANK BANK1 BANK 0 ROW- ADDRESS LATCH & DECODER BANK 7 BANK 6 BANK 5 BANK 4 BANK3 BANK BANK1 BANK0 MEMORY ARRAY SENSE AMPLIFIERS I/O GATING DM MASK LOGIC COLUMN DECODER Up to (8) Banks Figure Micron Technology, Inc. All rights reserved. Page 6

7 DD: The New DRAM Standard Additive Latency Another added feature in DD devices is additive latency. Adding READ or WRITE latency can enable the memory controller to optimize the placement of commands on the command bus and to pipeline a continuous sequence of operational codes. Additive Latency Control (for optimized command bus) A0 A13, BA0 BA WE# CAS# RAS# CS# CK# CK CKE ODT ADDRESS REGISTER MODE REGISTERS COMMAND DECODE CONTROL LOGIC REFRESH COUNTER ROW- ADDRESS MUX COLUMN- ADDRESS COUNTER/ LATCH BANK CONTROL LOGIC 1KB or KB page size for all DD Figure 5 Without additive latency, a READ or WRITE command cannot occur immediately after an ACTIVE command. Without additive latency, the command bus is limited by t RCD, and the maximum data throughput may be less. Refer to Figure 6 for an example. CK# CK T0 T1 T T3 T4 T5 T6 T7 ACTIVE 0 READ 0 ACTIVE 1 READ 1 ACTIVE READ ACTIVE 3 READ 3 Command Bus utilizing Additive Latency (note there are not any unusual command cycles) ACTIVE 0 NOP t RCD (MIN) ACTIVE 1 READ 0 ACTIVE READ 1 NOP READ Command WithOUT using Additive Latency (note there are several NOPs) AL = CL = 3 RL = 5 DQ DOUT Bank 0 DOUT Bank 0 DOUT Bank 0 BL = 4, CL = 3, AL =, RL = AL + CL = 5 Figure 6 TRANSITIONING DATA DON T CARE 006 Micron Technology, Inc. All rights reserved. Page 7

8 DD: The New DRAM Standard System Performance To improve system timing and signal integrity, DD supports differential clocks, differential strobes, reduced-drive I/O for all configurations, and on-die termination (ODT). These features are unmatched by any previous memory technology. Differential Signals Differential signals offset the deficiencies of traditional, single-ended signals, including a simultaneously switching output noise (SSO) or ground bounce that affects the accuracy of the input receivers. With differential signals, the switch point is always in the center and does not move with voltage level variations, so slight variations in voltage levels do not skew timing. Because differential signals are complementary and are typically routed in very close proximity to each other, they are more immune to local board-level effects. Two Output Drive Levels Typically on point-to-point systems, the closer the device output impedance is matched to the board impedance, the better the signal quality. On DD devices, all configurations support two output drive levels. This enables designers to use approximately 40-ohm impedance or 18-ohm impedance to best match the drive level to the board. On-Die Termination Along with differential signals, all DD I/O pins have ODT. This allows the memory controller to enable signal termination when and where needed. On high-speed DD components, ODT can be dynamically configured for 50 ohm, 75 ohm, or 150 ohm equivalent pull-ups to VTT. ODT can signifi- DQ0 DQ On-Die-Termination UDQS, UDQS#, LDQS, LDQS# UDM, LDM VDDQ ODT CONTROL sw3 sw sw3 sw 8 sw3 sw sw3 sw VssQ sw1 sw1 R1 R1 sw1 R1 R1 sw1 R1 R1 Figure Micron Technology, Inc. All rights reserved. Page 8

9 DD: The New DRAM Standard cantly improve signal integrity and save board space by eliminating the need for external resistors. Enhanced DD FBDIMMs FBDIMMs are the newest and most versatile DRAM memory solution developed to date. They are optimized for high speed and have virtually unlimited density when utilized with multiple, deep-slotted channels (up to eight slots per channel). FBDIMMs support each individual channel with 50 percent more peak bandwidth than a discrete DD device. The high-speed channel used for FBDIMMs enables the memory controller to WRITE and READ to the modules in parallel with a :1 READ to WRITE ratio. For example, if a DD device has a peak bandwidth of 6.4 GB/s, the FBDIMM high-speed interface has a peak bandwidth of 9.6 GB/s (6.4 GB/s for READs plus 3. GB/s for simultaneous WRITEs). Unmatched Innovation DD reduces power consumption, maximizes DRAM throughput, improves signal integrity, and maximizes flexibility. As an industry leader, Micron offers a comprehensive portfolio of DD products in numerous configurations and densities. Micron s 51Mb and 1Gb devices support speeds up to DD-800, which amounts to 6.4GB/s for a 64-bit data bus; and the first functional Gb (51 Meg x 4) DD device is expected to hit production volume soon. Add to that a wide variety of high-performance, high-bandwidth FBDIMMs and very low profile DIMMs, and you have a comprehensive, flexible, and reliable DRAM portfolio. For additional DD information, including Micron s part catalog and latest data sheets, refer to our Web site at Micron Technology, Inc. All rights reserved. Page 9

10 Contact Information Micron Semiconductor Products, Inc S Federal Way, P.O. Box 6 Boise, ID Tel: Micron Europe Limited (England) Micron House, Wellington Business Partk Dukes Ride, Crowthorne Berkshire RG45 6LS United Kingdom Tel: +44 (0) Micron Technology Italia, Srl Via Antonia Pacinotti Avezzano (AQ) Italy Tel: About Micron Micron Technology, Inc., one of the world s most efficient and innovative semiconductor companies, manufactures and markets a full line of DRAM components and modules, NAND Flash memory, CMOS image sensors, and other semiconductors. Our broad product line includes both legacy and leading-edge solutions, offered in multiple generations, densities, configurations, and packages to meet the diverse needs of our customers. With operations in 18 countries, customers can count on us to deliver the expert design, manufacturing, sales, and technical support and ultimately, the high-performance, advanced semiconductor solutions that go into successful product designs. Micron Semiconductor Asia, Pte. Ltd. 5 Upper Aljunied Link #06-06 Quartz Industrial Building Singapore Tel: Micron Technology Asia Pacific, Inc. Suite 508, 5th Floor 333 Keelung Road, Sec 1 Taipei, 110 Taiwan, ROC Tel: Micron Japan, Ltd. Atago Green Hills MORI Tower 34th Floor 5-1 Atago, Chome Minato-ku, Tokyo, Japan Tel: Micron Semiconductor, (Shanghai) Co., Ltd. Suite 3701, 37F, Bund Center Yan An Dong Lu Shanghai 0000, China Tel: Products and specifications discussed herein are subject to change by Micron without notice. Products are warranted only to meet Micron s production data sheet specifications. All information discussed herein is provided AS IS and without warranties of any kind. Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.