Memory Challenges. Issues & challenges in memory design: Cost Performance Power Scalability

Transcription

1 Memory Devices 1

2 Memory Challenges Issues & challenges in memory design: Cost Performance Power Scalability 2

3 Memory - Overview Definitions: RAM random access memory DRAM dynamic RAM SRAM static RAM Volatile memory the RAMs lose data when power is removed Nonvolatile memory retain data when the power is off ISP in-system programmable 3

4 Functionality Static RAM (SRAM) A word, once written at a location, remains stored as long as power is on, unless the same location is written to again Basic structure and operations Read operation: while the address is asserted, and CS (chip select) and OE (output enable) are asserted, DOUT are read out Write operation: while the address and CS/WE are asserted (write enable), a data word placed on DIN (data input) is written into the memory 4

5 SRAM Timing (1) Read operation timing parameters t AA access time from address t ACS access time from chip select t OE output-enable time t OZ output-disable time t OH output-hold time 5

6 SRAM Timing (2) Write operation timing parameters t AS address setup time before write t AH address hold time after write t CSW chip-select setup time before end of write t WP write pulse width t DS data setup time before end of write t DH data hold time after end of write 6

7 Synchronous SRAM Synchronous Clocked interfaces for control, address and data Internal structure Edge-triggered registers AREG for address CREG for control INREG for input data OUTREG for output data 7

8 Functionality Operation of One Bit Cell Dynamic RAM (DRAM) Periodically refresh the stored data by reading it and then writing ing it back, otherwise the data disappears Write operation: Set word line HIGH; To store 1, set bit line HIGH, charging the capacitor; To store 0, set LOW on the bit line, discharging the capacitor Read operation: Set word line HIGH; Bit line is precharged halfway between HIGH and LOW; The capacitor voltage pulls the bit line slightly higher or lower; A sense amplifier detects this small change and recovers 1 or 0. 1-bit storage cell 8

9 DRAM Basic Structure Basic one transistor storage cell together with cross-coupled coupled latch sense amplifier 9

10 DRAM Refreshing Reading destroys the original voltage on the capacitor, so that the recovered data must be written back into the cell after reading DRAM uses refresh cycles to periodically update memory cells Sequentially reading the degraded contents of each cell into a D latch and writing it back to a solid LOW or HIGH Voltage stored in a DRAM cell after writing and refresh operations 10

11 DRAM Internal Structure The physical array is square, for example, 64K X 1 containing 256 X 256 bits Only 8 multiplexed address inputs, saving pins which are important for compact design of memory system A complete 16-bit address is presented in two steps controlled by two signals: RAS_L row address strobe CAS_L column address strobe 11 Internal structure of a 64K X 1 DRAM

12 Read operation DRAM Timing (1) Read a selected row into the row latch column address is applied and stored in the column address register on the falling edge of CAS_L The column address is used to select one bit of the read row As long as CAS_L is asserted, a three-state pin, DOUT, is output-enabled As soon as RAS_L is negated, the entire row is written back 12

13 DRAM Timing (2) Write operation WE_L(write enable) must be asserted before CAS_L is asserted to select a write cycle and to disable DOUT for the rest of the cycle once the selected row is read into the row latch, WE_L also forces the input bit on DIN to be merged into the row latch, in the bit position selected by column address When the row is subsequently written back into the array on the rising edge of RAS_L, it contains a new value in the selected column 13

14 DRAM Other Timing Types CAS-before-RAS refresh cycle Read-modify-write cycle Page-mode read cycle Page-mode write cycle 14

15 Synchronous DRAM (SDRAM) Why synchronous The conventional RAS/CAS edge-based DRAM can not run fast and need to meet timing margins when interfacing with the rest of the system External signals CLK: samples an SDRAM s s control signal and address inputs on the rising edge of a common clock signal CKE: clock enable signal so that inputs are ignored if CKE is not asserted RAS_L, CAS_L and WE_L: command words High-order address bits: interpreted as a bank select to indicate which bank a command word applies to 15

16 DRAM Other Types FPM (Fast Page Mode) DRAM EDO DRAM (Extended Data Out DRAM) RLDRAM (Reduced Latency DRAM) 16

17 Special Application Memory (1) Video RAM (VRAM) 17

18 Special Application Memory (2) Dual-Port RAM 18

19 Read-Only Memory (ROM) Mask ROM Programmable ROM (PROM) Erasable programmable ROM (EPROM) Electrically erasable programmable ROM (EEPROM) 19

20 Flash Memory Electrically erasable, programmable, and nonvolatile Write or erase data in blocks Much faster than EEPROM 20

21 Banks and Ranks Bank: the entire memory array of individual bit cells is divided into sub-arrays called banks Banks allow a device s s memory core to be repaired of manufacturing defects by mapping in redundant core components Banks increase performance of a single device by facilitating concurrent operations Rank: A term that is descriptive of a multichip memory module A rank is a group of memory chips on a memory module that get selected simultaneously and that together form a data word width identical to the width of the memory data bus 21

22 Definition: DDR (Double Data Rate) SDRAM DDR SDRAM (double data rate synchronous DRAM) is a type of DRAM that realize twice the data transfer rate of conventional SDRAM DDR SDRAM is synchronous DRAM that realizes high- speed data transfer while adhering to the specifications of SDRAM as much as possible Differences from SDRAM Functions and specifications Commands Operation timing 22

23 Difference between DDR and SDR SDRAM - Functions and specifications * Conventional SDRAM is referred to as SDR SDRAM (single data rate synchronous DRAM) 23

24 Difference between DDR and SDR SDRAM - Functions and specifications (cont( cont) Twice data transfer rate is achieved by using 2-bit 2 prefetch architecture, with read cycle as example here 24

25 Difference between DDR and SDR SDRAM - Functions and specifications (cont( cont) Explanation of read cycle 2n bits of data are transferred from the memory cell array to the I/O buffer every clock Data transferred to the I/O buffer is output n bits at a time every half clock As the internal bus width is twice the external bus width, a data output rate twice the data rate of the internal bus is achieved 25

26 Use of DLL in DDR SDRAM DLL (delay locked loop) circuit is used in DDR SDRAM A fast access time and high operation frequencies are realized by controlling and adjusting the time lag between external clock and internal clock 26

27 Operation Timing of DDR SDRAM Read cycle timing Write cycle timing 27

28 Operation Timing of DDR SDRAM (cont( cont) Explanation of operation timing - Command signal READ/WRIT at rising edge of clock (CK) - Data input/output timing employs differential clock (CK and /CK) - Data strobe signal (DQS) is adopted to achieve high-speed data transfer. DQS is output from the device and received by the receiver, which adjusts the data (DQ) capture timing using DQS - Data is edge-aligned to DQS for read data and center-aligned for write data. This means that when controller receives read data from DDR SDRAM, it will internally delay the received strobe to the center of the received data window 28

29 FCRAM (Fast Cycle RAM) New technology developed by the Fujitsu Corporation Change the DRAM core itself. The process included pipeline operation and core segmentation with the added benefit of power reduction Address input can be made in parallel with command input. With this pipelining scheme, it s s possible to start a command operation while a data read or write operation is still in process, resulting in an improvement of the cycle time 29

30 FCRAM (cont( cont) FCRAM cores are used in three types of FCRAM memory devices: Network FCRAM FCRAM with a DDR synchronous interface used in networking, graphics, and multimedia Mobile FCRAM FCRAM with an asynchronous SRAM interface for mobile phone applications Consumer FCRAM FCRAM with a synchronous SDR SDRAM interface for use in consumer applications such as cameras, battery-driven devices, and car navigation systems 30

31 FCRAM (cont( cont) Representative values of Network, Mobile, and Consumer FCRAM 31

32 FCRAM (cont( cont) Representative values of Network, Mobile, and Consumer FCRAM (cont) 32

33 SigmaRAM Definition and features: Definition and features: A family of SRAM products jointly defined by the SigmaRAM Consortium The SigmaRAM family consists of devices featuring common I/O buses Designed especially for networking applications, the family of devices features higher speed, new packaging, an improved clocking scheme, multimode operation, and low power SigmaRAM packaging is also designed for networking 33

34 RLDRAM (Reduced Latency DRAM) Definition and features: Definition and features: Codeveloped by Micron Technology and Infineon Technologies Its defining characteristics include High density High bandwidth Reduced cycle time SRAM-like access Ideal for switch and router applications, and also for other high-bandwidth, high-speed, and latency-sensitive applications 34

35 DDR SRAM (Double( Data Rate SRAM DDR, DDRII SRAM) DSRAM has evolved over time to exhibit higher clock frequencies, shorter cycle times, and higher densities 35

36 DDR SRAM (cont( cont) Feature comparison of DDR and DDRII SRAM 36

37 Flash Memory Electrically erasable, programmable and nonvolatile Data to be written or erased in blocks other than one byte at a time like EEPROM Applications: digital cellular phones, digital cameras, LAN switches, etc; also can be used as embedded memory or in packaged, removable memory cards, and is also a variable choice for solid data storage replacing magnetic tapes and low-density hard disk drives Flash densities: range from 1 Mb to 8Gb Flash access times: most applications use flash devices with random access times of ns 37

38 Flash Memory (cont( cont) Flash memory performance increases with greater complexity Performance here refers to the speed with which several read and write operations can be made The major benefit of operating in page mode versus the standard mode is the greater speed A page is a small group of memory words that are accessed, internal to the memory, in parallel rather than one at a time 38

39 Flash Memory (cont( cont) Example timing diagram for page-mode read (byte mode) - The page size of the example device is 8 words (16 bytes). The higher address bits A3-A19 select the page, and the LSB bits A0-A2 (in word mode) and A-1 to A2 (in byte mode) select the specific word/byte within page - The first read has an access time t ACC, which is typical of a standard flash device, however a subsequent page read access to a location anywhere within the same page is much faster, and this access time is denoted as t PACC - Fast page-mode accesses are obtained by keeping A3-A19 constant and changing A0-A2 to select the specific word, or changing A-1 to A2 to select the specific byte within that page 39

40 Flash Cards Flash memory chips are conveniently packaged as flash cards and come in several formats, including the full-size PC Card (ATA PC Card) and the smaller CompactFlash, SmartMedia, and similar formats 40

41 FeRAM (Ferroelectric RAM) and MRAM (Magnetoresistive RAM) Features and performance: Features and performance: The next-generation nonvolatile memory for imminent commercialization MRAM uses magnetic, thin film elements on a silicon substrate. Data is written and read by pulsing wires that are perpendicular to each other with one set above and the other below the magnetic 7 MRAM can reach theoretical write times down to 2.3 ns, 1,000 times faster than the fastest nonvolatile flash and 20 times faster than FeRAM MRAM access times are as fast as 3 ns, or 20 times faster than DRAM, consuming less than 1/100 the energy of DRAM MRAM s resistance to radiation makes it to be considered a prime replacement for SRAM, which suffers more and more from densityinduced, soft-error rates as it scales below 0.1um 41

42 Quad Data Rate (QDR) SRAM Address Rate: 2-word 2 burst QDR SRAM - Sustain both a 2-word 2 read and a 2-word 2 write each clock cycle - The SRAM utilizes first ½ clock cycle to perform a read nad the other ½ clock cycle to perform a write operation. - The address bus is shared for the read and write data ports, necessitating double address rate (DAR) operation - The clock to register, the read address and the clock to register and the write address are 180 out of phase 42

43 QDR SRAM (cont( cont) Address Rate: 4-word 4 burst QDR SRAM - Sustain both a 4-word 4 read and a 4-word 4 write every clock cycle - The SRAM utilizes first clock cycle to perform a read nad the other clock cycle to perform a write operation. - The 4-word 4 read data is output during two cycles (4-word burst) - Double data address rate (DAR) is needed - The rising edge of the positive signal of differential master clock signal is used to register the read address. The next rising edge is used to latch the write address. 43

44 QDR SRAM (cont( cont) Write data placement One approach to using separate input and output clocks of the QDR SRAMs QDR SRAMs have both input and output clocks 44

45 QDR SRAM (cont( cont) Timing diagram for QDR Window of valid data = (t KHKH t CO ) + t DOH - t KHKH : rising edge of clock to rising edge of clock 180 out of phase - t CO : clock to data output time - t DOH : the data hold time 45

46 Direct Rambus DRAM (DRDRAM) PC memory system architecture for RDRAM Electrical topology comparison The RDRAM memory interface features: - The highest bandwidth per pin - Supported DRAM densities from Mb with a roadmap to support up to 1 Gb - Speed bins of 800, 1,066, 1,200, 1,333 Mbps with a roadmap to support up to 1,600 Mbps - Memory configurable into single or dual RIMM modules supporting bandwidths from 1.6 GB/s to 5.3 GB/s with a roadmap to support up to 12.8 GB/set quad-channel module 46

47 DRDRAM (cont( cont) Comparison of consumer HDTV decoder designs showing reduced chip count with the use of RDRAM Memory system architecture comparison 47

48 DRDRAM (cont( cont) Overview of a 16-bit wide-channel system 48

49 DRDRAM (cont( cont) Overview of a Rambus 16-bit system motherboard 49

50 Clock generator architecture DRDRAM (cont( cont) Channel termination Clock output drivers with example component values shown for a channel impedance of 28 Ohm 50