MEM1G72D2FBD-25A1 8 Gigabyte (1G x 72 Bit)

Transcription

1 Datasheet Rev MEM1G72D2FBD-25A1 8 Gigabyte (1G x 72 Bit) 8 Gigabyte (1G x 72 Bit) Fully Buffered DDR2 DIMM memory module RoHS Compliant Product Datasheet Version MEM1G72D2FBD-25A1

2 Version: Rev. 1.1, MAR 2011 SPD-data for -25 speed added Version: Rev. 1.0, OCT Inital release We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sales@memphis.ag Datasheet Version MEM1G72D2FBD-25A1

3 Features JEDEC-compatible DDR2 240-Pin Fully Buffered Dual-In-Line Memory Module (FBDIMM) Capacity: 8GB, organized 1Gig x 72 Bit Maximum Data Transfer Rate MEM1G72D2FBD-25A1: 6.40 GB/Sec Maximum Data Transfer Rate : 5.30 GB/Sec 3.2 Gb/s, 4 Gb/s, and 4.8 Gb/s link transfer rates Power Supply for DRAM: VDD, VDDQ =1.8± 0.1 V Power Supply for AMB: VCCFBD = / V 72 Bit Data Bus Width with ECC Buffer interface with high-speed differential point-to-point Link at 1.5 volt Channel error detection and reporting Channel fail-over mode support Programmable CAS Latency (CL): 3, 4, 5, 6 (Clock) Posted CAS by programmable additive latency (AL = 0,1,2,3 and 4 Clock) for better command and data bus efficiency Automatic DDR2 DRAM bus and channel calibration MBIST and IBIST test functions Transmitter de-emphasis to reduce ISI Transparent mode for DRAM test support Serial Presence Detect (SPD) with EEPROM Gold Edge Contacts 100% RoHS-Compliant Standard Module Height 30.35mm (1.19 inch) Operating Temperature Range 0 to 95 C tcase (Note: The average refresh-interval must be reduced to 3.9μs (MAX) when tcase exceeds +85 C) Datasheet Version MEM1G72D2FBD-25A1

4 Table 1 - Ordering Information for RoHS Compliant Product Part Number Speed Memory Clock Clock Cycles (CL-t RCD -t RP Temperature Range Module Type AMB type MEM1G72D2FBD-25A1L4 PC MHz to 95 C 8GB FBDIMM IDT AMB0780L4 L4 PC Mhz to 95 C 8GB FBDIMM IDT AMB0780L4 Note: The average refresh-interval must be reduced to 3.9μs (MAX) when TCASE exceeds +85 C Table 2 - Performance Range Speed Max Clock Frequency (min. Clock Cycle min. CAS Latency) MEM1G72D2FBD-25A1L4 PC MHz (2.5ns@CL=5) PC MHz (3.0ns@CL=5) PC MHz (3.75ns@CL=4) PC MHz (5.0ns@CL=3) L4 PC MHz (3.0ns@CL=5) PC MHz (3.75ns@CL=4) PC MHz (5.0ns@CL=3) Table 3 DRAM component information Brand Part No Type. Max. DRAM Speed DRAM Packing # of DRAMs per module Memphis MEM2G04D2DABG Mx4 CL5 FBGA 60 ball, lead free 36 Memphis MEM2G04D2DABG Mx4 CL5 FBGA 60 ball, lead free 36 Table 4 - Addressing Parameter Value Refresh count 8K Row address 32K A[14:0] Device bank address 8 BA[2:0] Device configuration 2Gb (512Mx4) Column address 2K A[11, 9:0] Module rank address 2 /S[1:0] Number of devices 36 Datasheet Version MEM1G72D2FBD-25A1

5 Table 5 - Pin Assignment Pin Name Pin Name Pin Name Pin Name 1 VDD 121 VDD VDD 122 VDD 62 VSS 182 VSS 3 VDD 123 VDD 63 PN SN10 4 VSS 124 VSS VDD 125 VDD 65 VSS 185 VSS 6 VDD 126 VDD 66 PN SN11 7 VDD 127 VDD VSS 128 VSS 68 VSS 188 VSS 9 VCC 129 VCC 69 VSS 189 VSS 10 VCC 130 VCC 70 PS0 190 SS0 11 VSS 131 VSS VCC 132 VCC 72 VSS 192 VSS 13 VCC 133 VCC 73 PS1 193 SS1 14 VSS 134 VSS VTT 135 VTT 75 VSS 195 VSS 16 VID1 136 VID0 76 PS2 196 SS DNU/M_Test VSS 138 VSS 78 VSS 198 VSS 19 RFU 139 RFU 79 PS3 199 SS3 20 RFU 140 RFU VSS 141 VSS 81 VSS 201 VSS 22 PN0 142 SN0 82 PS4 202 SS VSS 144 VSS 84 VSS 204 VSS 25 PN1 145 SN1 85 VSS 205 VSS RFU 206 RFU 27 VSS 147 VSS 87 RFU 207 RFU 28 PN2 148 SN2 88 VSS 208 VSS VSS 209 VSS 30 VSS 150 VSS 90 PS9 210 SS9 31 PN3 151 SN VSS 212 VSS 33 VSS 153 VSS 93 PS5 213 SS5 34 PN4 154 SN VSS 215 VSS 36 VSS 156 VSS 96 PS6 216 SS6 37 PN5 157 SN VSS 218 VSS 39 VSS 159 VSS 99 PS7 219 SS7 40 PN SN VSS 221 VSS 42 VSS 162 VSS 102 PS8 222 SS8 43 VSS 163 VSS RFU 164 RFU 104 VSS 224 VSS 45 RFU 165 RFU 105 RFU 225 RFU 46 VSS 166 VSS 106 RFU 226 RFU 47 VSS 167 VSS 107 VSS 227 VSS 48 PN SN VDD 228 SCK VDD VSS 170 VSS 110 VSS 230 VSS 51 PN6 171 SN6 111 VDD 231 VDD VDD 232 VDD 53 VSS 173 VSS 113 VDD 233 VDD 54 PN7 174 SN7 114 VSS 234 VSS VDD 235 VDD 56 VSS 176 VSS 116 VDD 236 VDD 57 PN8 177 SN8 117 VTT 237 VTT SA2 238 VDDSPD 59 VSS 179 VSS 119 SDA 239 SA0 60 PN9 180 SN9 120 SCL 240 SA1 Datasheet Version MEM1G72D2FBD-25A1

6 Table 6 - Pin Description Pin Name Description Pin Name Description SCK System Clock Input, positive line 1 AMB reset signal System Clock Input, negative line 1 VCC AMB Core Power and AMB Channel Interface Power PN[13:0] Primary Northbound Data, positive lines VDD SDRAM Power and AMB DRAM I/O Power Primary Northbound Data, negative lines PS[9:0] Primary Southbound Data, positive lines VSS Ground ] Primary Southbound Data, negative lines VDDSPD EEPROM Power VTT SDRAM Address/Command/Clock Termination Power (VDD/2) SN[13:0] Secondary Northbound Data, positive lines SDA EEPROM Data Input / Output Secondary Northbound Data, negative lines SCL EEPROM Clock Input SS[9:0] Secondary Northbound Data, positive lines SA[2:0] EEPROM Address Inputs, also used to select DIMM number in the AMB Secondary Northbound Data, negative lines RFU Reserved for Future use 2 VID[1:0] DNU / M_Test Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs. VID[0] is VDD value: OPEN=1.8V, GND=1.5V; VID[1] is VCC value: OPEN=1.5V, GND=1.2V. The DNU / M_Test pin provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module.it is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. Note: 1 System Clock Signals SCK and switch at one half the DRAM CK, frequency. 2 Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility. Datasheet Version MEM1G72D2FBD-25A1

7 Figure 1 - PCB Dimension 240 Pin DDR2 Fully Buffered DIMM Notes: Dimensioning and tolerancing conform to ASME Y14.5M Tolerances an all dimensions ± 0.15 unless otherwise specified. All dimensions are in millimeters. Datasheet Version MEM1G72D2FBD-25A1

8 Figure 2 - Dimension with Heatspreader Datasheet Version MEM1G72D2FBD-25A1

9 Datasheet Version MEM1G72D2FBD-25A1 Figure 3 - Functional Block Diagram (Page 1 of 3) /S1 /S0 U2 U18 0 U1 U17 U4 U20 U3 U D4-D7 2 2 D8-D D12-D15 0 U5 U21 4 D16-D19 U6 U22 U7 U23 U8 U D20-D D24-D D28-D31 4 U33 U CB0-CB3

10 Datasheet Version MEM1G72D2FBD-25A1 Figure 4 - Functional Block Diagram (Page 2 of 3) /S1 /S0 U10 U26 9 D32-D35 U9 U25 U12 U28 U11 U D36-D D44-D47 9 U13 U29 13 D48-D51 U14 U30 U15 U31 U16 U D52-D D56-D D60-D63 13 D40-D43 U35 U CB4-CB7

11 Figure 5 - Functional Block Diagram (Page 3 of 3) VTT Terminators VCC B1 VDDSPD E1, B1 VDD U1-U36, B1 VREF U1-U36 VSS U1-U36, E1, B1 All address / command / control / clock VTT D0-D63 PN0-PN13 CB0-CB7 /PN0-/PN PS0-PS /PS0-/PS9 /S0-> (U1-U16,U33,U35) SN0-SN13 CKE0->CKE (U1-U16,U33,U35) /SN0-/SN13 SS0-SS9 /SS0-/SS9 AMB B1 /S1-> (U17-U32,U34,U36) CKE1->CKE (U17-U32,U34,U36) ODT->ODT0 (U1-U36) SCL BA0-BA2 (U1-U36) SDA A0-A15 (U1-U36) SA1-SA2 /RAS (U1-U36) SA0 /CAS (U1-U36) /RESET /WE (U1-U36) SCK, /SCK CK, /CK (U1-U36) SDA SDA VDD VDDSPD SCL SCL E1 WP SA0 SA1 SA2 SA0 SA1 SA2 Datasheet Version MEM1G72D2FBD-25A1

12 Electrical Parameter Table 7 - Absolute Maximum DC Ratings Parameter Symbol Rating Unit Notes Voltage on any pin relative to V SS V IN V OUT -0.3V ~ 1.75 V 1 Voltage on V CC pin relative to V SS V CC -0.3V ~ 1.75 V 1 Voltage on V DD pin relative to V SS V DD -0.5V ~ 2.3 V 1 Voltage on V TT pin relative to V SS V TT -0.5V ~ 2.3 V 1 Storage temperature T STG -55 ~ 100 o C 1 DRAM Operation temperature (Ambient) T CASE 0 ~ 95 o C 1,2 AMB Operation temperature (Ambient) T CASE 0 ~ 110 o C 1 Notes: tresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. At C operation temperature range, doubling refresh commands in frequency to a 32ms period ( trefi=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. Table 8 - DC Electrical Characteristics and Operating Conditions Parameter / Condition Symbol Rating Units Notes Min Typ. Max AMB supply voltage VCC V DRAM supply voltage VDD V Termination voltage VTT 0.48 x VDD 0.5 x VDD 0.52 x VDD V EEPROM supply voltage VDDSPD V 1 SPD Input HIGH (logic 1) voltage VIH(DC) VDDSPD V 2 SPD Input LOW (logic 0) voltage VIL(DC) V 2 RESET Input HIGH (logic 1) voltage VIH(DC) V 3 RESET Input LOW (logic 0) voltage VIL(DC) V 2 Leakage Current (RESET) IL ua 3 Leakage Current (link) IL -5-5 ua 4 Notes: 1 Applies to AMD and SPD. 2 Applies to serial memory buffer (SMB) and SPD bus signals. 3 Applies to AMD CMOS signal /RESET. 4 For all other AMB-related DC parameters, please refer to the high-speed differential link interface specification Datasheet Version MEM1G72D2FBD-25A1

13 Table 9 - Timing Parameters Parameter / Condition Symbol Min Max Units Notes EI Assertion Pass-Thru Timing tei Propagtet - 4 clks EI Desertion Pass-Thru Timing teid - bitlock clks 2 EI Assertion Duration tei clks 1,2 Bit Lock Interval tbitlock frames 1 Frame Lock Interval tframelock frames 1 Notes: 1 Defined in FB-DIMM Architecture and Protocol Spec. 2 Clocks defined as core clocks = 2x SCK input Table 10 - IDD Specifications with Conditions and Operation Current Parameter / Condition Symbol Current Units Notes Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH; Command and address lines stable Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IBIST overall IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and CKE driven LOW MEM1G72D2FBD- 25A1L4 MEM1G72D2FBD- 3A1L4 ICC_IDLE_ IDD_IDLE_ ICC_IDLE_ IDD_IDLE_ ICC_ACTIVE_ IDD_ACTIVE_ ICC_ACTIVE_ IDD_ACTIVE_ ICC_TRAINING IDD_TRAINING ICC_IBIST IDD_IBIST ICC_EI IDD_EI Table 11 - VTT currents Parameter / Condition Symbol Typ MAX Units Idle current, DDR2 SDRAM device power down ITT1-700 ma Active power, 50% DDR2 SDRAM BW ITT2-700 ma Datasheet Version MEM1G72D2FBD-25A1

14 Table 12 - SPD Information Byte NO. Description 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage Note Hex MEM1G72D2FBD-25A1-25A1-3A1 CRC coverage Byte, CRC coverage Byte, SPD Byte Total: 256Byte, SPD Byte Total: 256Byte, SPD Use: 176Byte SPD Use: 176Byte 1 SPD Revision Rev 1.1 Rev Key Byte / DRAM Device Type DDR2 SDRAM FB-DIMM DDR2 SDRAM FB-DIMM Voltage Levels of this Assembly Channel 1.5V; DRAM 1.8V Channel 1.5V; DRAM 1.8V SDRAM Addressing No. of Row: 15; No. of Col: No. of Row: 15; No. of Col: ; No. of Rank: 8 11; No. of Rank: 8 5 Module Physical Attributes Height: 30.35mm, Height: 30.35mm, Thickness: Max 8mm Thickness: Max 8mm 6 Module Type / Thickness FB-DIMM, (width: FB-DIMM, (width: mm) mm) 7 Module Organization 2 Rank / x4 2 Rank / x Fine Timebase Dividend and Divisor 5/2 (2.5ps) 5/2 (2.5ps) Medium Timebase Dividend 1/4 (0.25ns) 1/4 (0.25ns) Medium Timebase Divisor 1/4 (0.25ns) 1/4 (0.25ns) SDRAM Minimum Cycle Time (tckmin) 2.5ns 3ns 0A 0C 12 SDRAM Maximum Cycle Time (tckmax) 8ns 8ns SDRAM /CAS Latencies Supported CL 3, 4, 5 CL 3, 4, SDRAM Minimum /CAS Latency Time (tcas) 12.5ns 15ns 32 3C 15 SDRAM Write Recovery Times Supported 2, 3, 4, 5 CLK 2, 3, 4, 5 CLK SDRAM Write Recovery Time (twr) 15ns 15ns 3C 3C 17 SDRAM Write Latencies Supported 2, 3, 4, 5, 6, 7, 8 CLK 2, 3, 4, 5, 6, 7, 8 CLK SDRAM Additive Latencies Supported 0, 1, 2, 3, 4 CLK 0, 1, 2, 3, 4 CLK SDRAM Minimum /RAS to /CAS Delay (trcd) 12.5ns 15ns 32 3C 20 SDRAM Minimum Row Active to Row Active Delay (trrd) 7.5ns 7.5ns 1E 1E 21 SDRAM Minimum Row Precharge Time (trp) 12.5ns 15ns 32 3C 22 SDRAM Upper Nibbles for tras and trc SDRAM Minimum Active to Precharge Time (tras) 45ns 45ns B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (trc) 52.5ns 60ns D2 F SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command 195ns 195ns 0C 03 0C 03 Period (trfc) 27 SDRAM Internal Write to Read Command Delay (twtr) 7.5ns 7.5ns 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (trtp) 7.5ns 7.5ns 1E 1E 29 SDRAM Burst Lengths Supported BL 4, 8 BL 4, SDRAM Terminations Supported 50, 75, 150 ohm 50, 75, 150 ohm SDRAM Drivers Supported Weak Driver Weak Driver SDRAM Average Refresh Interval (trefi) / Double Refresh mode bit 7.8us (Double 7.8us (Double C2 C2 / High Temperature self-refresh rate support indication above 85 o C) above 85 o C) 33 Bits 7:4: Tcasemax Delta. Bits 3:0: DT4R4W Delta 95 o C 95 o C Thermal resistance of SDRAM device package from top (case) to A 7A ambient (Psi T-A SDRAM) at still air condition based on JESD51-2 standard. 35 DT0: Case temperature rise from ambient due to IDD0/activateprecharge operation minus 2.8 o C offset temperature 36 DT2N/DT2Q: Case temperature rise from ambient due to IDD2N/precharge standby operation from UDIMM and due to IDD2Q/precharge quiet standby operation for RDIMM E 2E 37 DT2P: Case temperature rise from ambient due to IDD2P/precharge power-down operation 38 DT3N: Case temperature rise from ambient due to IDD3N/active standby operation 39 DT4R/Mode Bit: Bits 7:1 Case temperature rise from ambient due to IDD4R/page open burst read operation. Bit 0: Mode bit to specify if DT4W is greater or less than DT4R. - 4C 4C Datasheet Version MEM1G72D2FBD-25A1

15 Byte NO. Description Note Hex MEM1G72D2FBD-25A1-25A1-3A DT5B: Case temperature rise from ambient due to IDD5B/burst refresh operation 41 DT7: Case temperature rise from ambient due to IDD7/bank interleave read mode operation Reserved Reserved FB-DIMM ODT Values Rank0/1 (150ohm) Rank0/1 (150ohm) Reserved FB-DIMM Channel Protocols Supported Back-to-Back Access Turnaround Time AMB Read Access Time for DDR2-800 (AMB.LINKPARNXT[1:0]=11) AMB Read Access Time for DDR2-667 (AMB.LINKPARNXT[1:0]=10) AMB Read Access Time for DDR2-533 (AMB.LINKPARNXT[1:0]=01) Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A AMB) 88 AMB DT Idle_ AMB DT Idle_1-6C 6C 90 AMB DT Idle_2-6C 6C 91 AMB DT Active_1-8B 8B 92 AMB DT Active_ AMB DT L0s Reserved AMB Case Temperature Maximum (Tcase_max) 111 C 111 C Airflow impedance and category bits - 0A 0A 100 Reserved AMB Personality Bytes: Pre-initialization (1) - A5 A5 102 AMB Personality Bytes: Pre-initialization (2) AMB Personality Bytes: Pre-initialization (3) - DA DA 104 AMB Personality Bytes: Pre-initialization (4) AMB Personality Bytes: Pre-initialization (5) AMB Personality Bytes: Pre-initialization (6) - 9C 9C 107 AMB Personality Bytes: Post-initialization (1) - DB DB 108 AMB Personality Bytes: Post-initialization (2) AMB Personality Bytes: Post-initialization (3) AMB Personality Bytes: Post-initialization (4) - AF AF 111 AMB Personality Bytes: Post-initialization (5) - FA F0 112 AMB Personality Bytes: Post-initialization (6) - FA F0 113 AMB Personality Bytes: Post-initialization (7) - E8 E8 114 AMB Personality Bytes: Post-initialization (8) - E8 E AMB Manufacturer s JEDEC ID Code - 7F B3 7F B Module ID: Module Manufacturer s JEDEC ID Code Manufacturer's data Manufacturer's data 119 Module ID: Module Manufacturing Location Manufacturer's data Manufacturer's data Module ID: Module Manufacturing Date Manufacturer's data Manufacturer's data Module ID: Module Serial Number Manufacturer's data Manufacturer's data Cyclical Redundancy Code 6E 88 E Module Part Number Manufacturer's data Manufacturer's data Module Revision Code Manufacturer's data Manufacturer's data SDRAM Manufacturing s JEDEC ID Code Manufacturer's data Manufacturer's data Manufacturer s Specific Date Manufacturer's data Manufacturer's data Open for customer use Manufacturer's data Manufacturer's data Datasheet Version MEM1G72D2FBD-25A1

16 Contents Features 3 Table 1 - Ordering Information for RoHS Compliant Product 4 Table 2 - Performance Range 4 Table 3 DRAM component information 4 Table 4 - Addressing 4 Table 5 - Pin Assignment 5 Table 6 - Pin Description 6 Figure 1 - PCB Dimension 240 Pin DDR2 Fully Buffered DIMM 7 Figure 2 - Dimension with Heatspreader 8 Figure 3 - Functional Block Diagram (Page 1 of 3) 9 Figure 4 - Functional Block Diagram (Page 2 of 3) 10 Figure 5 - Functional Block Diagram (Page 3 of 3) 11 Electrical Parameter 12 Table 7 - Absolute Maximum DC Ratings 12 Table 8 - DC Electrical Characteristics and Operating Conditions 12 Table 9 - Timing Parameters 13 Table 10 - IDD Specifications with Conditions and Operation Current 13 Table 11 - VTT currents 13 Table 12 - SPD Information 14 Contents 16 List of Tables 17 List of Figures 17 MEMPHIS Global Presence 18 Datasheet Version MEM1G72D2FBD-25A1

17 List of Tables Table 1 - Ordering Information for RoHS Compliant Product 4 Table 2 - Performance Range 4 Table 3 DRAM component information 4 Table 4 - Addressing 4 Table 5 - Pin Assignment 5 Table 6 - Pin Description 6 Table 7 - Absolute Maximum DC Ratings 12 Table 8 - DC Electrical Characteristics and Operating Conditions 12 Table 9 - Timing Parameters 13 Table 10 - IDD Specifications with Conditions and Operation Current 13 Table 11 - VTT currents 13 Table 12 - SPD Information 14 List of Figures Figure 1 - PCB Dimension 240 Pin DDR2 Fully Buffered DIMM 7 Figure 2 - Dimension with Heatspreader 8 Figure 3 - Functional Block Diagram (Page 1 of 3) 9 Figure 4 - Functional Block Diagram (Page 2 of 3) 10 Figure 5 - Functional Block Diagram (Page 3 of 3) 11 Datasheet Version MEM1G72D2FBD-25A1

18 MEMPHIS Global Presence EMEA (Europe, Middle East, Africa) Germany (Headquarter): Spain: Russia: Memphis Electronic AG Saalburgstr. 155 D Bad Homburg v.d.h. Germany Phone: +49 (0) Fax: +49 (0) Memphis Electronic AG Representative Office Spain Marina 60, 5, 1, 2 Barcelona Spanien Tel.: a.hacelas@memphis.ag Memphis Electronic AG Representative Office Russia Prospect 60 let Oktiabria Office Moscow Russia Phone: p.krylov@memphis.ag Americas (american economic area) USA: Toll Free: Memphis Electronic Inc S Shepherd Dr, Suite 910 Houston, Texas 77019, USA Phone: Fax: ussales@memphis.ag Memphis Electronic Inc. Boston Office 20 Sunset Rock Lane Reading, Massachusetts USA Phone.: Fax: ussales@memphis.ag Memphis Electronic Inc. San Jose Office 6576 Bose Lane CA San Jose, USA Phone: Fax: g.swanson@memphis.ag APAC (Asian Pacific economic area) China: Singapore: Japan: Memphis Electronic Hong Kong Ltd. Room B, 18/F., EGL Tower 83 Hung To Road, Kwun Tong Hong Kong Tel.: Fax: hksales@memphis.ag Memphis Electronic Hong Kong Ltd. Shanghai Representative Office Unit 753A, Tower 3, 88 Keyuan Road, Pudong, Shanghai, , China Tel.: Fax: hksales@memphis.ag Memphis Electronic Hong Kong Ltd. Singapore Representative Office 25 International Business Park #04-103D German Centre Singapore Phone: Fax: hksales@memphis.ag Memphis Electronic Japan Japan Representative Office #418, Sotokanda Stork bldg.4f, , Sotokanda, Chiyoda-ku Tokyo, , Japan Tel.: Fax: hksales@memphis.ag Datasheet Version MEM1G72D2FBD-25A1