DD333-S512 PDRB X DATA SHEET. Memory Module Part Number DD333-S512 BUFFALO INC. (1/7)

Transcription

1 DATA SHEET Memory Module Part Number DD333-S512 (1/7)

2 1. Description 184pin Unbuffered DIMM PC2700/CL=2.5(166MHz Double Data Rate) 2. Module Specification Specification Capacity 512MByte Physical Bank(s) 1 Module Organization 64M x 64bit Module Type Unbuffered NonECC Speed Grade PC2700/CL=2.5 (166MHz Double Data Rate) PC2100/CL=2 (133MHz Double Data Rate) Interface SSTL_2 Power Supply Voltage 2.5V 0.2V Burst Lengths 2,4,8 DRAM Organization 64M x 8bit DDR SDRAM PCB Part No. UE0832-A PCB Layer 6 Layers Contact Tab 184pin GOLD Flash Plating Ni : min 2.00µm / Au : min 0.05µm Serial PD Support 3. Mechanical Design and Module Pinout Mechanical Design and Pinout Reference standard Mechanical Design and Pinout DDR-I 184Pin DIMM (PDRB X057-xx) Y(PCB Height) Z1 Z2 : 31.75mm : 2.72mm MAX(Single Sided) : Undefined 4. Block Diagram Block Diagram Reference standard Block Diagram PC2700 Unbuffered DIMM(x8bitDRAM 1Bank) (PDRB X074-xx) (2/7)

3 5. Electrical Specifications 5.1 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage Any Pin Relative to Vss V T -0.5~V CCQ +0.5 (max3.6) V Supply Voltage Relative to Vss V CC,V CCQ -0.5~3.6 V Power Dissipation P D 12 W Short Circuit Output Current I O 50 ma Operating Temperature T OPR 0~70 C Storage Temperature T STG -55~125 C 5.2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit Supply Voltage V CC V Input/Output Supply Voltage V CCQ V Reference Voltage V REF 0.49x V CCQ 0.51x V CCQ V Termination Voltage V TT V REF V REF V High Level Input Voltage (DC) V IHD V REF V CCQ +0.3 V Low Level Input Voltage (DC) V ILD -0.3 V REF V High Level Input Voltage (AC) V IHA V REF V Low Level Input Voltage (AC) V ILA V REF V 5.3 Pin Capacitances CK Input Pin Capacitance /S Input Pin Capacitance CKE Input Pin Capacitance DQS Input/Output Pin Capacitance DQ Input/Output Pin Capacitance Parameter Symbol Maximum Pin Capacitance Unit CK0, /CK0 C ICK0 11 pf CK1, /CK1 C ICK pf CK2, /CK2 C ICK pf /S0 C IS0 28 pf /S1 C IS1 pf /S2 C IS2 pf /S3 C IS3 pf CKE0 C ICKE0 28 pf CKE1 C ICKE1 pf DQS0~DQS7 C IDQS0 5.5 pf DQS8 C IDQS1 pf DM0~DM7,DQS9~DQS16 C IDQS2 5.5 pf DM8, DQS17 C IDQS3 pf DQ0~DQ63 C OUT0 5.5 pf CB0~7 C OUT1 pf /RESET Input Pin Capacitance /RESET C IRESET pf Other Input Pin Capacitance A,BA,/RAS,/CAS,/WE C IN 28 pf (3/7)

4 5.4 D.C. Characters Parameter Symbol Value Unit Test Condition Operationg Current for One Bank Active-precharge I CC0 MAX 1600 * ma t RC = t RC (min) Operationg Current for One Bank Operation I CC1 MAX 1720 * ma BL=2 Precharge Power-down Standby Current I CC2P MAX 144 * ma CKE V IL Precharge Floating Standby Current I CC2F MAX 480 * ma Precharge Quiet Standby Current I CC2Q MAX 320 * ma CKE, /S V IL Address,CMD Changing once per clock cycle CKE, /S V IH Address,CMD stable at keeping V IH or V IL Active Power-down Standby Current I CC3P MAX 280 * ma CKE V IL Active Standby Current I CC3N MAX 600 * ma CKE, /S V IH,t RC = t RAS (max) Operating Current for Burst Read I CC4R MAX 2000 * ma BL=2 Operating Current for Burst Write I CC4W MAX 2000 * ma BL=2 Auto Refresh Current I CC5 MAX 2680 * ma t RC t RFC (min) Self Refresh Current I CC6 MAX 40 * ma CKE 0.2V Operating Current for Four Bank Operation I CC7 MAX 3680 * ma BL=4 Input Leakage Current I IL MIN -16 * μa MAX 16 * μa V SS V IN V CC Output High Current I OH MIN * ma V OH = 1.95V, V TT =V REF Output Low Current I OL MIN 15.2 * ma V OL = 0.49V, V TT =V REF 5.5 A.C. Timing Characters * : No guarantee against this value. Parameter Symbol MIN MAX Unit Clock Period /CAS Latency = t /CAS Latency = 2.5 CLK 6 12 ns Clock High Level Width t CH CLK Clock Low Level Width t CL CLK DQS output access time from CLK t DQSCK ns DQ output access time from CLK t AC ns DQS-DQ Skew per Group,per Access t DQSQ 0.45 ns DQS Read Preamble t RPRE CLK DQS Read Postamble t RPST CLK DQ DM Input Setup Time Relative to DQS t DS 0.45 ns DQ DM Input Hold Time Relative to DQS t DH 0.45 ns DQS Write Preamble Setup Time t WPRES 0 ns DQS Write Preamble Hold Time t WPREH 0.25 CLK DQS Write Postamble Time t WPST CLK Write Command to First DQS Latching Transition t DQSS CLK DQS Falling Edge to CLK Rising-Setup Time t DSS 0.2 CLK DQS Falling Edge to CLK Rising-Hold Time t DSH 0.2 CLK DQS Input High Pulse Width t DQSH 0.35 CLK DQS Input Low Pulse Width t DQSL 0.35 CLK Data Hold Skew Factor t QHS 0.55 ns Address,Command Input Setup Time t IS 0.75 ns Address,Command Input Hold Time t IH 0.75 ns Active-Active/Auto Refresh Clock Period t RC 60 ns Auto Refresh Command Period t RFC 72 ns Active to Precharge Command t RAS 42 70,000 ns Active to Read or Write Delay t RCD 18 ns Precharge Command Period t RP 18 ns Active Bank A to Active Bank B Command t RRD 12 ns Write Recovery Time t WR 15 ns Average Periodic Refresh Interval t REF 7.8 μs Load Mode Register Command Cycle Time t MRD 12 ns (4/7)

5 6. Serial Presence Detect (SPD) Data Structure Byte No. DD333-S512 Function Hex Value Function Supported 0 Defines # of bytes written into serial memory at module manufacturer Bytes 1 Total # of bytes of SPD memory device Bytes 2 Fundamental memory type (FPM, EDO, SDRAM..) 07 DDR-SDRAM 3 # of row addresses on this assembly 0D 13 4 # Column Addresses on this assembly 0B 11 5 # Module Banks on this assembly 01 1Bank 6 Data Width of this assembly Data Width continuation 00 64bits 8 Voltage interface standard of this assembly 04 SSTL2 9 SDRAM Cycle time (highest CAS latency) ns (CL=2.5 ) 10 SDRAM Access from Clock (highest CAS latency) ns (CL=2.5) 11 DIMM Configuration type (non-parity, ECC) 00 NON-ECC 12 Refresh Rate/Type μs 13 Primary SDRAM Width 08 x8 bit 14 Error Checking SDRAM width 00 Non Use 15 Minimum Clock Delay Back to Back Random Column Address 01 1 CLK 16 Burst Lengths Supported 0E Burst Lengths (2,4,8) 17 # of Banks on Each SDRAM Device 04 4Bank 18 CAS# Latency 0C CAS Latency =2, CS# Latency 01 CS Latency =0 20 Write Latency 02 WE Latency =1clk 21 SDRAM Module Attributes 20 Differential CLK 22 SDRAM Device Attributes: General 00 Tolerance 0.2V 23 SDRAM Cycle time (2nd highest CAS latency) ns(CL=2) 24 SDRAM Access from Clock (2nd highest CAS latency) ns(CL=2) 25 SDRAM Cycle time (3rd highest CAS latency) 00 Non Support 26 SDRAM Access from Clock (3rd highest CAS latency) 00 Non Support 27 Minimum Row Precharge Time (trp) ns 28 Row Activate to Row Activate Min. (trrd) ns 29 RAS to CAS Delay Min (trcd) ns 30 Minimum RAS Pulse Width (trasmin) 2A 42ns 31 Density of each bank on module MB 32 Command and Address signal input setup time ns 33 Command and Address signal input hold time ns 34 Data signal input setup time ns 35 Data signal input hold time ns Reserved for VCSDRAM 00 Undefined 41 SDRAM Device Minimum Active to Active/Auto Refresh Time(tRC) 3C 60ns 42 SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh(tRFC) 48 72ns 43 SDRAM Device Maximum device cycle time(tckmax) 30 12ns 44 SDRAM Device Maximum skew between DQS and DQ signals(tdqsq) 2D 0.45ns 45 DDR SDRAM Device Maximum Read DataHold Skew Factor(tQHS) ns Superset Information (may be used in future) 00 Undefined 62 SPD Data Revision Code 00 Rev. code Checksum for bytes Checksum Manufacturer s JEDEC ID code per JEP-106 7F BUFFALO 72 Manufacturing Location Manufacturer s Part Number 20 BLANK Revision Code 00 Undefined Manufacturing Date Undefined Assembly Serial Number Undefined Manufacturer Specific Data Undefined 126 Intel specification frequency 00 Undefined 127 Intel Specification CAS# Latency support 00 Undefined 128+ Unused storage locations Undefined (5/7)

6 7. Packing/Label Specification Packing/Label Specification Reference standard Packing/Label Specification for 5.25inchWidth DIMM (PDRB X062-xx) (6/7)

7 8. Revision History Rev. Date Changes Issued 01 Nov S.Fukui(A07) (7/7)