Memory Module Specifications KVR667D2D8F5K2/4G. 4GB (2GB 256M x 72-Bit x 2 pcs.) PC CL5 ECC 240-Pin FBDIMM Kit DESCRIPTION SPECIFICATIONS

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1 Memory Module Specifications KVR667D2D8F5K2/4G 4GB (2GB 256M x 72-Bit x 2 pcs.) PC CL5 ECC 240- FBDIMM Kit DESCRIPTION s KVR667D2D8F5K2/4G is a kit of two 2GB (256M x 72-bit) PC CL5 (Synchronous DRAM) fully buffered ECC dual rank memory modules. Total kit capacity is 4GB (4096MB). Each module is based on eighteen 28M x 8-bit 667MHz DDR2 FBGA components. Each module also includes an AMB device (Advanced Memory Buffer). The electrical and mechanical specifications are as follows: SPECIFICATIONS FBDIMM Module 240-pin JEDEC Standard R/C B Memory Organization 2 rank of x8 devices DDR2 DRAM Interface SSTL_8 DDR2 Speed Grade 667 Mbps CAS Latency Module Bandwidth 5.3 GB/s DRAM VDD = VDDQ =.8V AMB VCC = VCCFBD =.5V EEPROM VDDSPD = 3.3V (typical) Heat Spreader Full DIMM Heat Spreader (FDHS) PCB Height 30.35mm, double-side RoHS Compliant Kingston.com Document No. VALUERAM B00 2/23/09 Page

2 DDR2 240-pin FBDIMM out: V DD 2 V DD 3 PN3 5 SN3 6 PN9 8 SN9 9 PS9 2 SS9 2 V DD 22 V DD 32 PN3 52 SN3 62 V SS 82 V SS 92 V SS 22 V SS 3 V DD 23 V DD 33 V SS 53 V SS 63 PN0 83 SN0 93 PS5 23 SS5 4 V SS 24 V SS 34 PN4 54 SN4 64 PN0 84 SN0 94 PS5 24 SS5 5 V DD 25 V DD 35 PN4 55 SN4 65 V SS 85 V SS 95 V SS 25 V SS 6 V DD 26 V DD 36 V SS 56 V SS 66 PN 86 SN 96 PS6 26 SS6 7 V DD 27 V DD 37 PN5 57 SN5 67 PN 87 SN 97 PS6 27 SS6 8 V SS 28 V SS 38 PN5 58 SN5 68 V SS 88 V SS 98 V SS 28 V SS 9 V CC 29 V CC 39 V SS 59 V SS KEY 99 PS7 29 SS7 0 V CC 30 V CC 40 PN3 60 SN3 69 V SS 89 V SS 00 PS7 220 SS7 V SS 3 V SS 4 PN3 6 SN3 70 PS0 90 SS0 0 V SS 22 V SS 2 V CC 32 V CC 42 V SS 62 V SS 7 PS0 9 SS0 02 PS8 222 SS8 3 V CC 33 V CC 43 V SS 63 V SS 72 V SS 92 V SS 03 PS8 223 SS8 4 V SS 34 V SS 44 RFU* 64 RFU* 73 PS 93 SS 04 V SS 224 V SS 5 V TT 35 V TT 45 RFU* 65 RFU* 74 PS 94 SS 05 RFU** 225 RFU** 6 VID 36 VID0 46 V SS 66 V SS 75 V SS 95 V SS 06 RFU** 226 RFU** 7 RESET 37 DNU/M_Test 47 V SS 67 V SS 76 PS2 96 SS2 07 V SS 227 V SS 8 V SS 38 V SS 48 PN2 68 SN2 77 PS2 97 SS2 08 V DD 228 SCK 9 RFU** 39 RFU** 49 PN2 69 SN2 78 V SS 98 V SS 09 V DD 229 SCK 20 RFU** 40 RFU** 50 V SS 70 V SS 79 PS3 99 SS3 0 V SS 230 V SS 2 V SS 4 V SS 5 PN6 7 SN6 80 PS3 200 SS3 V DD 23 V DD 22 PN0 42 SN0 52 PN6 72 SN6 8 V SS 20 V SS 2 V DD 232 V DD 23 PN0 43 SN0 53 V SS 73 V SS 82 PS4 202 SS4 3 V DD 233 V DD 24 V SS 44 V SS 54 PN7 74 SN7 83 PS4 203 SS4 4 V SS 234 V SS 25 PN 45 SN 55 PN7 75 SN7 84 V SS 204 V SS 5 V DD 235 V DD 26 PN 46 SN 56 V SS 76 V SS 85 V SS 205 V SS 6 V DD 236 V DD 27 V SS 47 V SS 57 PN8 77 SN8 86 RFU* 206 RFU* 7 V TT 237 V TT 28 PN2 48 SN2 58 PN8 78 SN8 87 RFU* 207 RFU* 8 SA2 238 VDDSPD 29 PN2 49 SN2 59 V SS 79 V SS 88 V SS 208 V SS 9 SDA 239 SA0 30 V SS 50 V SS 60 PN9 80 SN9 89 V SS 209 V SS 20 SCL 240 SA 90 PS9 20 SS9 RFU = Reserved Future Use. * These pin positions are reserved for forwarded clocks to be used in future module implementations ** These pin positions are reserved for future architecture flexibility ) The following signals are CRC bits and thus appear out of the normal sequence: PN2/PN2, SN2/SN2, PN3/PN3, SN3/SN3, PS9/PS9, SS9/SS9 Kingston.com Document No. VALUERAM B00 2/23/09 Page 2

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4 Functional Block Diagram: S S0 DQS0 DQS0 DQS9 DQS4 DQS4 DQS3 DQ0 DQ DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NU/ CS DQS DQS I/O D0 NU/ CS DQS DQS I/O D9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 NU/ CS DQS DQS I/O D4 NU/ CS DQS DQS I/O D3 DQS DQS DQS0 DQS5 DQS5 DQS4 DQ8 DQ9 DQ0 DQ DQ2 DQ3 DQ4 DQ5 NU/ CS DQS DQS I/O D NU/ CS DQS DQS I/O D0 DQ40 DQ4 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 NU/ CS DQS DQS I/O D5 NU/ CS DQS DQS I/O D4 DQS2 DQS2 DQS DQS6 DQS6 DQS5 DQ6 DQ7 DQ8 DQ9 DQ20 DQ2 DQ22 DQ23 NU/ CS DQS DQS I/O D2 NU/ CS DQS DQS I/O D DQ48 DQ49 DQ50 DQ5 DQ52 DQ53 DQ54 DQ55 NU/ CS DQS DQS I/O D6 NU/ CS DQS DQS I/O D5 DQS3 DQS3 DQS2 DQS7 DQS7 DQS6 PN0-PN3 PN0-PN3 PS0-PS9 PS0-PS9 SCL SDA SA-SA2 SA0 RESET SCK/SCK DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ3 A M B NU/ CS DQS DQS NU/ CS DQS DQS I/O D3 I/O D2 SN0-SN3 SN0-SN3 SS0-SS9 SS0-SS9 S0 -> CS (D0-D8) CKE0 -> CKE (D0-D8) S -> CS (D9-D7) CKE -> CKE (D9-D7) ODT -> ODT (all s) BA0-BA2 (all s) A0-A5 (all s) RAS (all s) CAS (all s) WE (all s) CK/CK (all s) Notes:. DQ-to-I/O wiring may be changed within a byte. 2. There are two physical copies of each address/command/control/clock SCL WP A0 Serial PD A A2 SA0 SA SA2 DQS8 DQS8 DQS All address/command/control/clock SDA DQ56 DQ57 DQ58 DQ59 DQ60 DQ6 DQ62 DQ63 V TT CB0 CB CB2 CB3 CB4 CB5 CB6 CB7 V TT V CC V DD V REF V SS NU/ CS DQS DQS I/O D7 NU/ CS DQS DQS I/O D8 V DDSPD NU/ CS DQS DQS I/O D6 NU/ CS DQS DQS I/O D7 Terminators AMB SPD, AMB D0-D7, AMB D0-D7 D0-D7, SPD, AMB Kingston.com Document No. VALUERAM B00 2/23/09 Page 4

5 Architecture: Advanced Memory Buffer Description: Name Description Count FB-DIMM Channel Signals 99 SCK System Clock Input, positive line SCK System Clock Input, negative line PN[3:0] Primary Northbound Data, positive lines 4 PN[3:0] Primary Northbound Data, negative lines 4 PS[9:0] Primary Southbound Data, positive lines 0 PS[9:0] Primary Southbound Data, negative lines 0 SN[3:0] Secondary Northbound Data, positive lines 4 SN[3:0] Secondary Northbound Data, negative lines 4 SS[9:0] Secondary Southbound Data, positive lines 0 SS[9:0] Secondary Southbound Data, negative lines 0 FBDRES To an external precision calibration resistor connected to Vcc DDR2 Interface Signals 75 DQS[8:0] Data Strobes, positive lines 9 DQS[8:0] Data Strobes, negative lines 9 DQS[7:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. 9 DQS[7:9] Data Strobes (x4 DRAM only), negative lines 9 DQ[63:0] Data 64 CB[7:0] Checkbits 8 A[5:0]A, A[5:0]B Addresses. A0 is part of the pre-charge command 32 BA[2:0]A, BA[2:0]B Bank Addresses 6 RASA, RASB Part of command, with CAS, WE, and CS[:0]. 2 CASA, CASB Part of command, with RAS, WE, and CS[:0]. 2 WEA, WEB Part of command, with RAS, CAS, and CS[:0]. 2 ODTA, ODTB On-die Termination Enable 2 CKE[:0]A, CKE[:0]B Clock Enable (one per rank) 4 CS[:0]A, CS[:0]B Chip Select (one per rank) 4 CLK[3:0] CLK[:0] used on 9 and 8 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be output disabled when not in use. 4 CLK[3:0] Negative lines for CLK[3:0] 4 DDRC_C4 DDR Compensation: Common return pin for DDRC_B8 and DDRC_C8. DDRC_B8 DDR Compensation: Resistor connected to common return pin DDRC_C4 DDRC_C8 DDR Compensation: Resistor connected to common return pin DDRC_C4 DDRC_B2 DDR Compensation: Resistor connected to V SS DDRC_C2 DDR Compensation: Resistor connected to V DD Kingston.com Document No. VALUERAM B00 2/23/09 Page 5

6 Advanced Memory Buffer Description: SCL SPD Bus Interface Signals 5 Serial Presence Detect (SPD) Clock Input SDA SPD Data Input / Output SA[2:0] SPD Address Inputs, also used to select the DIMM number in the AMB Miscellaneous Signals 63 PLLTSTOP LL Clock Observability Output VCCAPLL VSSAPLLA Analog VCC for the PLL. Tied with low pass filter to VCC. nalog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM. TEST_pin Leave floating on the DIMM 6 TESTLO_pin Tie to ground on the DIMM 2 5 BFUNC Tie to ground to set functionality as buffer on DIMM. RESET AMB reset signal NC No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power islands. RFUR eserved for Future Use 8 Power/Ground Signals 23 V CC AMB Core Power (.5 Volt) 24 V CCFBD AMB Channel I/O Power (.5 Volt) 8 V DD AMB DRAM I/O Power (.8 Volt) 24 V DDSPD SPD Power (3.3 Volt) V SS Ground Total 655. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency. 2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production DIMMs with a direct connection to ground. Kingston.com Document No. VALUERAM B00 2/23/09 Page 6

7 Package Dimensions: AMB Advanced Memory Buffer T E C H N O L O G Y (Units = millimeters) (8.8) MAX with heat sink Units: inches (millimeters) 45 x 0.007(0.8) (.9) (.06) (.06) (.37) (.7) Detail A Kingston.com Document No. VALUERAM B00 2/23/09 Page 7