JL2008A. Low-cost Mega Pixel Digital Still Camera Controller. Revision: 1.3 Date: 1/23/2006. JEILIN Technology Co., Ltd.

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1 JL2008A Low-cost Mega Pixel Digital Still Camera Controller Revision: 1.3 Date: 1/23/2006 JEILIN Technology Co., Ltd. 8F, No.179, Jian Yi Rd., Chung Ho, Taipei Hsien, Taiwan TEL: FAX:

2 Table of Contents 0. Revision History Generation Description Features Applications Functional Block Diagram Outline of JL2008A (LQFP128) Pin Description and Pin Configuration Electrical Characteristics Package Outline and Dimension...13 JEILIN Technology Co., Ltd. 2 of /1/23

3 0. Revision History Revision Description of Changes Date 1.0 First Release 2004/09/ Correct the following typos: 1. Figure 1 in page 5: Remove JL2005A character. 2004/12/29 2. Paragraph 6 in page 14: PQFP LQFP Add power-on default value for each I/O pin. 2. Add CCIR601 pin definition to some multi-function pins. 2005/11/ Standardize the Jeilin company logo. 2006/01/23 JEILIN Technology Co., Ltd. 3 of /1/23

4 3. Generation Description The JL2008A provides a complete solution for Low-cost Mega Pixel Camera for either toy camera or toy DV. It consists of several camera interfaces such as CMOS sensor, CCIR601 input, CSTN/STN LCD, SDRAM & DDR SDRAM, Secure Disk (SD) card, and Nand-Gate flash memory. It also combines color processing engine, image compression engine, low-voltage detection, UART transceiver, and USB1.1 interface in single chip, therefore either toy camera or toy DV can easily be built by JL2008A. 4. Features Four basic operation modes 1) Photo: Supported resolution ranges from VGA, 1.3M, 2.1M, to 3.0M pixels. 2) Video (Movie): Motion image is unceasingly recording until the memory is full. Following frame is a typical spec for reference. Simulated VGA: 20 fps@480x368 pixels QVGA: 20 fps@320x240 pixels 3) Voice: PCM format, 8Kbytes/sec 4) Web-cam: USB 1.1 Support CMOS image sensor with VGA, 1.3M, 2.1M, 3.0M or higher resolution Lens-vignetting compensation Advanced color interpolation, color adjustment function and 2D edge enhancement Auto bad-pixel cancellation Only one frame-buffer for image processing Hardwired super-resolution filter Real-time baseline JPEG compression AE/AWB measurement Support 8/16-bit DDR/SDR SDRAM up to 256Mb (16Mb, 64Mb, 128Mb, 256Mb) SDRAM chip test and downgrade SDRAM address remapping Status LCD controller Directly drive SRAM based CSTN LCD display with color dithering MSDC (MassStorage) interface for NAND-Gate flash, SD/MMC and SDRAM IMA ADPCM audio encoder with built-in 8-bit audio ADC Low-voltage Detection ADC for battery power Embedded turbo mode 8051 Support In-circuit Programming (ISP) function ISP provides an easy way to upgrade the firmware through PC. Built-in 64K bytes mask ROM. USB1.1 interface with MassStorage device class Access port for external host PWM waveform generator for mechanical shutter and flash light control 128-pin LQFP package JEILIN Technology Co., Ltd. 4 of /1/23

5 5. Applications Toy Camera Toy DV Middle-end Camera Thumb Disk Camera MP3 Camera IP Camera (need extra network controller) 6. Functional Block Diagram DDR/SDR SDRAM (16 ~ 256 Mb) JL2008A Image Sensor /CCIR601 Video Input Interface Color Processor DDR/SDR SDRAM Controller JPEG Encoder Storage Controller SD Card/ NAND-Gate Flash Flash Light Bus Arbiter Turbo mode 8051 (64K mask ROM) Image Processor ADPCM encoder 8 bit ADC/ Battery Detect USB1.1/ MSDC Key ROM CSTN LCD/ STN LCD Microphone PC Figure 1: Block diagram Video input interface: Support programmable timing generator for most off-the-shelf high resolution CMOS image sensor or CCIR601 timing. Color Processor: Perform auto bad-pixel cancellation, color interpolation, gamma correction, and most image enhancement filtering needed for color adjustment. Turbo mode 8051 (4 clock cycle/instruction) with ISP function and 64K mask ROM Image Processor: Super resolution, rotate and copy-paste with chroma keying function DDR/SDR SDRAM controller (8/16-bit): Burst-oriented mode DDR/SDR SDRAM controller with self-refresh mode and power-down mode support for power saving. Audio: Embedded 8 bit ADC and hardwired IMA-ADPCM encoder JPEG Encoder: 12 M pixels/s baseline jpeg encoding ability with downloadable quantization table and compression rate control index. USB1.1 Controller: USB 1.1 full speed with MSDC interface and embedded physical layer transceiver. Storage Controller: 4-bit high speed SD-Bus controller or NAND-Gate flash controller JEILIN Technology Co., Ltd. 5 of /1/23

6 JEILIN Technology Co., Ltd. 6 of /1/23 7. Outline of JL2008A (LQFP128) JL2008A LQFP128 S_D0 VDD25_1 VSS25_1 VSS33_1 VDD33_ S_ExClk S_PClk S_PWDN S_Reset S_HSync S_VSync S_D7 S_D6 S_D5 S_D4 S_D3 S_D2 S_D1 MPU_AD0 MPU_nPSEN MPU_nPSWR VSS33_USB DM DP VSS25_AD VDD33_USB AD_VTOP ADC_1 ADC_0 AD_VBOT VDD25_AD VDD25_3 VSS25_3 VSS33_3 VDD33_3 VSS33_XSC nreset VDD33_XSC XSCI XSCO GPIO_21 GPIO_20 GPIO_18 GPIO_19 D_nCAS D_nRAS D_BS0 D_BS1 D_A10 D_DQ15 GPIO_22 GPIO_23 GPIO_25 GPIO_24 S_D9 S_D8 GPIO_1 D_UDQS D_nCLK D_CLK D_DQ11 D_DQ0 SDA SCL GPIO_5 MPU_A13 GPIO_0 GPIO_2 GPIO_3 GPIO_4 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 MPU_ALE MPU_AD1 MPU_AD2 MPU_A8 MPU_A9 MPU_A10 MPU_A11 MPU_AD3 MPU_AD4 MPU_AD5 MPU_AD6 MPU_AD7 MPU_A14 MPU_A15 D_DQ1 D_DQ2 D_DQ3 D_DQ4 D_DQ5 D_DQ6 D_DQ7 D_LDQS D_LDQM D_nWE D_A0 D_A1 D_A2 D_A3 D_DQ14 D_DQ13 D_DQ12 D_DQ9 D_DQ8 D_UDQM D_CKE D_A11 D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 127 VDD25_PLL 128 VSS25_PLL 45 GPIO_17 98 D_DQ10 65 MPU_A12 Figure 2: Pin Out

7 8. Pin Description and Pin Configuration No. Name Type Default Description Note 1 VDD33_XSC P - Crystal oscillator pad power 2 XSCI I - Crystal oscillator pad input 3 XSCO O - Crystal oscillator pad output 4 VSS33_XSC P - Crystal oscillator pad ground 5 nreset IS - Power on chip reset, active low 6 S_PWDN O2 Z CMOS sensor power down 7 S_Reset O2 Z CMOS sensor reset 8 S_ExClk O2 H CMOS sensor external clock 9 S_PClk I Z CMOS sensor pixel clock Clk_ S_HSync B2 Z CMOS sensor horizontal synchronous HSync_ S_VSync B2 Z CMOS sensor vertical synchronous VSync_ S_D0 B2 Z CMOS image sensor data bus, bit 0 GPIO_27 *1 13 S_D1 B2 Z CMOS image sensor data bus, bit 1 GPIO_28 *1 14 S_D2 B2 Z CMOS image sensor data bus, bit 2 D0_601 GPIO_29 *1 15 S_D3 B2 Z CMOS image sensor data bus, bit 3 D1_601 GPIO_30 *1 16 S_D4 B2 Z CMOS image sensor data bus, bit 4 D2_601 GPIO_31 *1 17 S_D5 B2 Z CMOS image sensor data bus, bit 5 D3_601 GPIO_32 *1 18 S_D6 B2 Z CMOS image sensor data bus, bit 6 D4_601 GPIO_33 *1 19 S_D7 B2 Z CMOS image sensor data bus, bit 7 D5_601 GPIO_34 *1 20 VDD25_1 P - Core power 21 VSS25_1 P - Ground 22 VDD33_1 P - IO power 23 VSS33_1 P - Ground 24 S_D8 B2 Z CMOS image sensor data bus, bit 8 D6_601 GPIO_35 *1 25 S_D9 B2 Z CMOS image sensor data bus, bit 9 D7_601 GPIO_36 *1 26 SCL OD Z IIC clock 27 SDA OD Z IIC data Alt[1:0]= 00 Alt[1:0]= 01 Alt[1:0]= 10 Alt[1:0]= 11 *8 28 GPIO_0 B2 H SD_Clk O Nand_ALE O 29 GPIO_1 B2 Z Nand_nCE O HB_Mem_nCS I 30 GPIO_2 B2 Z SD_nIns I 31 GPIO_3 B2 Z SD_CMD B Nand_D0 B HB_Mem_Data(0) B 32 GPIO_4 B2 Z SD_Data0 B Nand_D1 B HB_Mem_Data(1) B 33 GPIO_5 B2 Z SD_Data1 B Nand_D2 B HB_Mem_Data(2) B 34 GPIO_6 B2 Z SD_Data2 B Nand_D3 B HB_Mem_Data(3) B JEILIN Technology Co., Ltd. 7 of /1/23

8 No. Name Type Default Description Note 35 GPIO_7 B2 Z SD_Data3 B Nand_D4 B HB_Mem_Data(4) B 36 GPIO_8 B2 L Pattern_Gen_0 O 37 GPIO_9 B2 Z O Nand_RDY I HB_Mem_Data(5) B 38 GPIO_10 B2 Z USB_Insert I 39 GPIO_11 B2 Z nint_0 I Nand_CLE O HB_Mem_Data(6) B 40 GPIO_12 B2 L Pattern_Gen_1 O 41 GPIO_13 B2 H M51_RAM_Rd O HB_Mem_Data(7) B 42 GPIO_14 B2 H M51_RAM_Wr O 43 GPIO_15 B2 Z UART_RX I HB_SPI_nSS_1 O 44 GPIO_16 B2 H UART_TX O 45 GPIO_17 B2 L SDRAM_Addr(12) O Nand_nRE O HB_Mem_nRd I 46 GPIO_18 B2 Z Nand_nWE O HB_Mem_nWr I 47 GPIO_19 B2 Z Nand_D5 B HB_Mem_Addr(0) I 48 GPIO_20 B2 Z Nand_D6 B HB_Mem_Addr(1) I 49 GPIO_21 B2 Z Nand_D7 B HB_Mem_Addr(2) I 50 MPU_nPSEN B2 H MPU program segment enable GPIO_37 *2 51 MPU_nPSWR B2 H MPU program segment write enable GPIO_38 *2 52 MPU_ALE B2 H MPU Address latch enable GPIO_39 *2 53 MPU_AD0 B2 L MPU address/data bus, bit 0 GPIO_40 *2 54 MPU_AD1 B2 L MPU address/data bus, bit 1 GPIO_41 *2 55 MPU_AD2 B2 L MPU address/data bus, bit 2 GPIO_42 *2 56 MPU_AD3 B2 L MPU address/data bus, bit 3 GPIO_43 *2 57 MPU_AD4 B2 L MPU address/data bus, bit 4 GPIO_44 *2 58 MPU_AD5 B2 L MPU address/data bus, bit 5 GPIO_45 *2 59 MPU_AD6 B2 L MPU address/data bus, bit 6 GPIO_46 *2 60 MPU_AD7 B2 L MPU address/data bus, bit 7 GPIO_47 *2 61 MPU_A8 B2 L MPU address bus, bit 8 GPIO_48 *2 62 MPU_A9 B2 L MPU address bus, bit 9 GPIO_49 *2 63 MPU_A10 B2 L MPU address bus, bit 10 GPIO_50 *2 64 MPU_A11 B2 L MPU address bus, bit 11 GPIO_51 *2 65 MPU_A12 B2 L MPU address bus, bit 12 GPIO_52 *2 66 MPU_A13 B2 L MPU address bus, bit 13 GPIO_53 *2 67 MPU_A14 B2 L MPU address bus, bit 14 GPIO_54 *2 68 MPU_A15 B2 L MPU address bus, bit 15 GPIO_55 *2 69 D_DQ0 B2 Z 16 bit SDRAM : DQ_0 8 bit SDRAM : DQ_0 Key_0 *3 JEILIN Technology Co., Ltd. 8 of /1/23

9 No. Name Type Default Description Note 70 D_DQ1 B2 Z 16 bit SDRAM : DQ_1 *3 Key_1 8 bit SDRAM : GPIO_56 *4 71 D_DQ2 B2 Z 16 bit SDRAM : DQ_2 *3 Key_2 8 bit SDRAM : DQ_1 72 D_DQ3 B2 Z 16 bit SDRAM : DQ_3 *3 Key_3 8 bit SDRAM : GPIO_57 *4 73 D_DQ4 B2 Z 16 bit SDRAM : DQ_4 *3 Key_4 8 bit SDRAM : DQ_2 74 D_DQ5 B2 Z 16 bit SDRAM : DQ_5 *3 Key_5 8 bit SDRAM : GPIO_58 *4 75 D_DQ6 B2 Z 16 bit SDRAM : DQ_6 *3 Key_6 8 bit SDRAM : DQ_3 76 D_DQ7 B2 Z 16 bit SDRAM : DQ_7 *3 Key_7 8 bit SDRAM : GPIO_59 *4 77 D_LDQS B2 L DDR SDRAM low byte data strobe 78 D_LDQM O2 L SDRAM low byte data write mask 79 VDD25_3 P - Core power 80 VSS25_3 P - Ground 81 VDD33_3 SDR SDRAM IO Power P - (VDD25_3) (DDR SDRAM IO Power) 82 VSS33_3 P - SDRAM Ground 83 D_nWE O2 H SDRAM write enable, active low 84 D_nCAS O2 H SDRAM column address strobe, active low 85 D_nRAS O2 H SDRAM raw address strobe, active low 86 DRAM_BS0 O2 L SDRAM bank address, bit 0 87 DRAM_BS1 O2 L SDRAM bank address, bit 1 88 D_A10 B2 Z SDRAM address bus, bit 10 M51_nEA *7 89 D_A0 B2 Z SDRAM address bus, bit 0 Init_Latch(0) *6 90 D_A1 B2 Z SDRAM address bus, bit 1 Init_Latch(1) *6 91 D_A2 B2 Z SDRAM address bus, bit 2 Init_Latch(2) *6 92 D_A3 B2 Z SDRAM address bus, bit 3 Init_Latch(3) *6 93 D_DQ15 B2 Z 16 bit SDRAM : DQ_15 Key_15 *3 8 bit SDRAM : DQ_7 94 D_DQ14 B2 Z 16 bit SDRAM : DQ_14 Key_14 *3 8 bit SDRAM : GPIO_60 *4 JEILIN Technology Co., Ltd. 9 of /1/23

10 No. Name Type Default Description Note 95 D_DQ13 B2 Z 16 bit SDRAM : DQ_13 Key_13 *3 8 bit SDRAM : DQ_6 96 D_DQ12 B2 Z 16 bit SDRAM : DQ_12 Key_12 *3 8 bit SDRAM : GPIO_61 *4 97 D_DQ11 B2 Z 16 bit SDRAM : DQ_11 Key_11 *3 8 bit SDRAM : DQ_5 98 D_DQ10 B2 Z 16 bit SDRAM : DQ_10 Key_10 *3 8 bit SDRAM : GPIO_62 *4 99 D_DQ9 B2 Z 16 bit SDRAM : DQ_9 Key_9 *3 8 bit SDRAM : DQ_4 100 D_DQ8 B2 Z 16 bit SDRAM : DQ_8 Key_8 *3 8 bit SDRAM : GPIO_63 *4 101 D_UDQS B2 Z SDRAM high byte data strobe 102 D_UDQM O2 Z SDRAM high byte data write mask Alt[1:0]= 00 Alt[1:0]= 01 Alt[1:0]= 10 Alt[1:0]= 11 *8 103 GPIO_22 B4 Z HB_SPI_nSS_0 B 104 GPIO_23 B4 Z HB_SPI_SCK B 105 GPIO_24 B4 Z HB_SPI_MISO B 106 GPIO_25 B4 Z HB_SPI_MOSI B 107 D_nClk O2 L DDR SDRAM inverted clock 108 D_CLK O2 H SDRAM clock 109 D_CKE O2 L SDRAM clock enable 110 D_A11 B2 Z SDRAM address, bit D_A9 B2 Z SDRAM address bus, bit 9 Test_Mode[1] *5 112 D_A8 B2 Z SDRAM address bus, bit 8 Test_Mode[0] *5 113 D_A7 B2 Z SDRAM address bus, bit 7 Init_Latch(7) *6 114 D_A6 B2 Z SDRAM address bus, bit 6 Init_Latch(6) *6 115 D_A5 B2 Z SDRAM address bus, bit 5 Init_Latch(5) *6 116 D_A4 B2 Z SDRAM address bus, bit 4 Init_Latch(4) *6 117 VDD25_AD P - ADC power 118 AD_VTOP A - ADC reference voltage decoupling, nominal value is 1.75V (Should be connected with a 0.1uF capacitor) 119 AD_VBOT A - ADC reference voltage decoupling, nominal value is 0.75V (Should be connected with a 0.1uF capacitor) 120 ADC_0 A - 8 bit ADC input channel 0 (for Audio recording only) 121 ADC_1 A - 8 bit ADC input channel 1 JEILIN Technology Co., Ltd. 10 of /1/23

11 No. Name Type Default Description Note 122 VSS25_AD P - ADC ground 123 VDD33_USB P - USB1.1 transceiver power 124 DP A - USB D+ signal 125 DM A - USB D- signal 126 VSS33_USB P - USB1.1 transceiver ground 127 VDD25_PLL P - Power for PLL 128 VSS25_PLL P - Ground for PLL Pin Type: P - Power/Ground Pin A - Analog Pin I - 3.3V CMOS Input Pin IS - 3.3V CMOS Schmitt-Trigger Input Pin O2-3.3V CMOS output pin with 2mA driving ability O4-3.3V CMOS output pin with 4mA driving ability B2-3.3V CMOS Bi-directional Pin with 2mA driving ability B4-3.3V CMOS Bi-directional Pin with 4mA driving ability OD - Open drain pin All CMOS input pin can take 5V Tolerant Pin Note: 1) This pin functions as GPIO when CMOS sensor was power down. 2) This pin functions as GPIO when internal mask ROM was enabled. 3) To prevent from disturbing normal SDRAM data access, this pin must be weakly pulled up or pulled down in order for the purpose of Input Button. 4) When 8-bit SDRAM chip was selected, this pin can function as GPIO. 5) This pin must be pulled down to ground in order for normal operation. 6) Signal on this pin can be latched to internal register while the power-on-reset was active. After power-on-reset was removed, this pin will return to its normal function. 7) This pin is used to determine the firmware is executed from external ROM or internal mask ROM. Pull-down this pin for external ROM and pull-up this pin for internal ROM. 8) Two-bit Register, Alt[10], is used to determine the function of GPIO[25:0]. Alt[1:0] is controlled by firmware. JEILIN Technology Co., Ltd. 11 of /1/23

12 5 Electrical Characteristics Absolute Maximum Ratings SYMBOL PARAMETER RATING UNITS V CC Power Supply (3.3V) -0.3 to 3.6 V V CC1 Power Supply (2.5V) -0.3 to 2.75 V V IN Input Voltage -0.3 to VCC+0.3 V V OUT Output Voltage -0.3 to VCC+0.3 V T STG Storage Temperature -55 to 150 Recommended Operation Conditions SYMBOL PARAMETER MIN TYP MAX UNITS V CC Power Supply (3.3V) V V CC1 Power Supply (2.5V) V T OPR Operating Temperature DC Electrical Characteristics for 3.3 volts operation (Under Recommended Operating Conditions and V CC = 3.0V ~ 3.6V, Tj = 0 to + 70 ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IL Input Low Voltage CMOS V V IH Input High Voltage CMOS 2.0 Vcc+0.3 V V T- Schmitt input Low Voltage CMOS V V T+ Schmitt input High Voltage CMOS 2.0 Vcc+0.3 V V OL Output low voltage 0.4 V V OH Output high voltage 2.4 V JEILIN Technology Co., Ltd. 12 of /1/23

13 6 Package Outline and Dimension Package Outline (128-pin LQFP) JEILIN Technology Co., Ltd. 13 of /1/23

14 Package Outline (128-pin LQFP) continued JEILIN Technology Co., Ltd. 14 of /1/23

15 Dimension (128-pin LQFP) Dimension Min Nom Max A 1.60 A A b b c c D 16.0 BSC D BSC e 0.40 BSC E 16.0 BSC E BSC L L REF R R S 0.20 θ θ1 0 0 θ θ Unit: REF: BSC: mm Reference Basic Spacing between Centers (integrated circuit package dimension) JEILIN Technology Co., Ltd. 15 of /1/23

16 JEILIN Technology Co., Ltd. 8F, No. 179, Jian Yi Rd., Chung Ho, Taipei Hsien, Taiwan Tel: Fax: Website: JEILIN Technology Corp., Ltd. All rights reserved. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this document is subject to change without prior notice. The information contained in this document is presented only as a guide for applications of our products. No responsibility is assumed by JEILIN Technology for any infringements of intellectual property or other rights of the third parties, which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of JEILIN Technology or others. No part of this document may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of JEILIN Technology. JEILIN Technology Co., Ltd. 16 of /1/23