JL2003A. Dual-mode Toy CAM Controller (CIF/VGA + TV) Revision: 1.4 Date: 1/23/2006. JEILIN Technology Co., Ltd.

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1 JL2003A Dual-mode Toy CAM Controller (CIF/VGA + TV) Revision: 1.4 Date: 1/23/2006 JEILIN Technology Co., Ltd. 8F, No.179, Jian Yi Rd., Chung Ho, Taipei Hsien, Taiwan TEL: FAX:

2 Table of Contents 0. Revision History Generation Description Features Application Functional Block Diagram Pin Assignment Pin Description and Pin Configuration Package and Dimension...12 JEILIN Technology Co., Ltd. 2 of /1/23

3 0. Revision History Revision Description of Changes Date 1.0 Create 2002/03/ Append the Package of LQFP 128 Pin Assignment and Dimension 2002/10/ Add Table of Contents 2002/11/14 2. Modify the form of documentation 3. Correct the errors in pin description. For example, both SDA and SCL is bi-directional pin, not open-drain output pin. 4. Add Pin Configuration 5. Add LQFP128 Drawing 1.3 Remove some obsolete data. 2005/11/ Standardize the Jeilin company logo. 2006/01/23 JEILIN Technology Co., Ltd. 3 of /1/23

4 1. Generation Description JL2003A is a low-cost chipset for dual-mode Toy Camera. It consists of required camera interfaces such as CMOS sensor, SDRAM, I 2 C interface, USB 1.1, and TV encoder in order to construct a low-cost Toy Camera with TV Out. Functionally, JL2003A receives the image raw data from many popular CMOS sensors, and then store it into SDRAM. All the captured image/photo stored in SDRAM can be uploaded to PC, configured as motion image to PC, or converted to CCIR signal for TV display. Its USB 1.1 interface can provide the basic video conference function in network through PC. 2. Features Programmable sensor timing generator to support various CMOS sensors. On chip clamp for dark level compensation, 8 bits per channel. On chip gain for white balance, 8 bits per channel. On chip Gamma table per channel, 10-bit in, 8 bit out. On chip Contrast, Saturate, Hue, Brightness. On chip measurements on two programmable windows. Flexible SDRAM controller supporting 16~256Mb. SDRAM arbitrator allows sensor writing, TV reading, USB reading, CPU accessing. TV interface supports NTSC and PAL CCIR656 format. USB image transfer using isochroous mode. Embedded turbo 8051 running at 27 MHz, with 256 internal RAM, 16K internal ROM. Support standard 8051 ports, allowing for external ROM, and flexible use of GPIO. Sensor image preview on TV and PC simultaneously. Camera function, take picture on SDRAM. Playback pictures on TV and PC. Upload/download pictures to/from PC. Transfer picture to/from external storage media. 2X digital zoom while TV preview. 3. Application Toy Camera Pen Drive Camera Dual-mode PC camera Video conference Door Phone Camera Home Surveillance Camera JEILIN Technology Co., Ltd. 4 of /1/23

5 4. Functional Block Diagram SDRAM 16~256Mb CMOS Sensor photobit bimorphic fuji hyundai pixelart ICM Sensor I/F & Sensor TG SDRAM Controller TV I/F & TV TG Color Processing CCIR656 NTSC PAL TV Encoder Turbo 8051 USB1.1 PC P0 P1 P2 P3 JEILIN Technology Co., Ltd. 5 of /1/23

6 5. Pin Assignment LQFP128 NRESET S_D7 S_D6 S_D5 S_D4 S_D3 S_D2 S_D1 S_D0 S_RESET S_HSYNC S_VSYNC S_PCLK VCC GND S_EXCLK S_PWDN SCL SDA TST1 TST2 TST3 TST4 TV_VSYNC TV_HSYNC TV_LCC GND DPLUS DMINUS VCC TV_D7 TV_D GND 1 96 TV_D5 XI 2 95 TV_D4 XO 3 94 TV_D3 VCC 4 93 TV_D2 CKE 5 92 TV_D1 DCLK 6 91 TV_D0 DQ NEA DQ RMWAKE DQ GND DQ VCC DQ P17 GND P16 JL2003A VCC P15 DQ P14 LQFP128 DQ P13 DQ P12 DQ P11 DQ P10 DQ GND DQ VCC DQ P27 DQ P26 DQ P25 DQ P24 A P23 VCC P22 GND P21 A P20 A P07 A P06 A P05 A P A6 A7 A8 A9 A10 A11 BS0 BS1 NCS NRAS NCAS NWE LDQM UDQM GND VCC P30 P31 P32 P33 P34 P35 P36 P37 NPSEN ALE P00 P01 P02 P03 VCC GND JEILIN Technology Co., Ltd. 6 of /1/23

7 6. Pin Description and Pin Configuration Pin No. Pin Name Description Type Drive 1 VSS Digital Ground P 2 XI Crystal Input X 3 XO Crystal Output X 4 VCC Digital Power P 5 CKE SDRAM Clock Enable O 2mA 6 DCLK SDRAM Clock O 2mA 7 DQ_0 SDRAM Data Bus B,D 2mA 8 DQ_1 SDRAM Data Bus B,D 2mA 9 DQ_2 SDRAM Data Bus B,D 2mA 10 DQ_3 SDRAM Data Bus B,D 2mA 11 DQ_4 SDRAM Data Bus B,D 2mA 12 VSS Digital Ground P 13 VCC Digital Power P 14 DQ_5 SDRAM Data Bus B,D 2mA 15 DQ_6 SDRAM Data Bus B,D 2mA 16 DQ_7 SDRAM Data Bus B,D 2mA 17 DQ_8 SDRAM Data Bus B,D 2mA 18 DQ_9 SDRAM Data Bus B,D 2mA 19 DQ_10 SDRAM Data Bus B,D 2mA 20 DQ_11 SDRAM Data Bus B,D 2mA 21 DQ_12 SDRAM Data Bus B,D 2mA 22 DQ_13 SDRAM Data Bus B,D 2mA 23 DQ_14 SDRAM Data Bus B,D 2mA 24 DQ_15 SDRAM Data Bus B,D 2mA 25 A_0 SDRAM Address Bus O 2mA 26 VCC Digital Power P 27 VSS Digital Ground P 28 A_1 SDRAM Address Bus O 2mA 29 A_2 SDRAM Address Bus O 2mA 30 A_3 SDRAM Address Bus O 2mA 31 A_4 SDRAM Address Bus O 2mA 32 A_5 SDRAM Address Bus O 2mA 33 A_6 SDRAM Address Bus O 2mA JEILIN Technology Co., Ltd. 7 of /1/23

8 34 A_7 SDRAM Address Bus O 2mA 35 A_8 SDRAM Address Bus O 2mA 36 A_9 SDRAM Address Bus O 2mA 37 A_10 SDRAM Address Bus O 2mA 38 A_11 SDRAM Address Bus O 2mA 39 BS_0 SDRAM Bank Select O 2mA 40 BS_1 SDRAM Bank Select O 2mA 41 NCS SDRAM Chip Select (active low) O 2mA 42 NRAS SDRAM Row Address Strobe (active low) O 2mA 43 NCAS SDRAM Column Address Strobe (active low) O 2mA 44 NWE SDRAM Write Enable (active low) O 2mA 45 LDQM SDRAM Data Mask (low byte) O 2mA 46 UDQM SDRAM Data Mask (high byte) O 2mA 47 VSS Digital Ground P 48 VCC Digital Power P 49 P3_ Port3 B,U,T 4mA 50 P3_ Port3 B,U,T 4mA 51 P3_ Port3 B,U,T 4mA 52 P3_ Port3 B,U,T 4mA 53 P3_ Port3 B,U,T 4mA 54 P3_ Port3 B,U,T 4mA 55 P3_ Port3 B,U,T 4mA 56 P3_ Port3 B,U,T 4mA 57 NPSEN 8051 npsen O 2mA 58 ALE 8051 ALE O 2mA 59 P0_ Port0 B,U,T 4mA 60 P0_ Port0 B,U,T 4mA 61 P0_ Port0 B,U,T 4mA 62 P0_ Port0 B,U,T 4mA 63 VCC Digital Power P 64 VSS Digital Ground P 65 P0_ Port0 B,U,T 4mA 66 P0_ Port0 B,U,T 4mA 67 P0_ Port0 B,U,T 4mA 68 P0_ Port0 B,U,T 4mA 69 P2_ Port2 B,U,T 4mA JEILIN Technology Co., Ltd. 8 of /1/23

9 70 P2_ Port2 B,U,T 4mA 71 P2_ Port2 B,U,T 4mA 72 P2_ Port2 B,U,T 4mA 73 P2_ Port2 B,U,T 4mA 74 P2_ Port2 B,U,T 4mA 75 P2_ Port2 B,U,T 4mA 76 P2_ Port2 B,U,T 4mA 77 VCC Digital Power P 78 VSS Digital Ground P 79 P1_ Port1 B,U,T 4mA 80 P1_ Port1 B,U,T 4mA 81 P1_ Port1 B,U,T 4mA 82 P1_ Port1 B,U,T 4mA 83 P1_ Port1 B,U,T 4mA 84 P1_ Port1 B,U,T 4mA 85 P1_ Port1 B,U,T 4mA 86 P1_ Port1 B,U,T 4mA 87 VCC Digital Power P 88 VSS Digital Ground P 89 RMWAKE USB Remote Wakeup I 90 NEA 8051 nea I 91 TV_D_0 Data to TV Encoder O 2mA 92 TV_D_1 Data to TV Encoder O 2mA 93 TV_D_2 Data to TV Encoder O 2mA 94 TV_D_3 Data to TV Encoder O 2mA 95 TV_D_4 Data to TV Encoder O 2mA 96 TV_D_5 Data to TV Encoder O 2mA 97 TV_D_6 Data to TV Encoder O 2mA 98 TV_D_7 Data to TV Encoder O 2mA 99 VCC Digital Power P 100 DMINUS USB bus D- A 101 DPLUS USB bus D+ A 102 VSS Digital Ground P 103 TV_LLC Clock to TV Encoder O 2mA 104 TV_HSYNC HSYNC to TV Encoder O 2mA 105 TV_VSYNC VSYNC to TV Encoder O 2mA JEILIN Technology Co., Ltd. 9 of /1/23

10 106 TSTD Test Pin I,D 107 TSTC Test Pin I,D 108 TEST Test Pin I,D 109 USB_TESTINIT Test Pin I,D,T 110 SDA I 2 C Data Line B,T 4mA 111 SCL I 2 C Clock Line B,T 4mA 112 S_PWDN Sensor Power Down O 2mA 113 S_EXCLK Clock to Sensor O 2mA 114 VSS Digital Ground P 115 VCC Digital Power P 116 S_PCLK Clock from Sensor I,C,T 117 S_VSYNC Sensor VSYNC B,D,T 2mA 118 S_HSYNC Sensor HSYNC B,D,T 2mA 119 S_RESET Sensor Reset O 2mA 120 S_D_0 Sensor Image Date I,D,T 121 S_D_1 Sensor Image Date I,D,T 122 S_D_2 Sensor Image Date I,D,T 123 S_D_3 Sensor Image Date I,D,T 124 S_D_4 Sensor Image Date I,D,T 125 S_D_5 Sensor Image Date I,D,T 126 S_D_6 Sensor Image Date I,D,T 127 S_D_7 Sensor Image Date I,D,T 128 NRESET Power On Reset I,S,T Note: I - Input Pin O - Output Pin B - Bi-directional Pin T - 5V Tolerant Pin S - Schmitt Input Pin P - Power/Ground Pin A - USB Data Pin X - Crystal U- Pull-up Pin D- Pull-down Pin C- Clock Pin JEILIN Technology Co., Ltd. 10 of /1/23

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12 7. Package and Dimension Package Outline (128-pin LQFP) JEILIN Technology Co., Ltd. 12 of /1/23

13 Package Outline (128-pin LQFP) continued JEILIN Technology Co., Ltd. 13 of /1/23

14 Dimension of LQFP128 Dimension Min Nom Max A 1.60 A A b b c c D 16.0 BSC D BSC e 0.40 BSC E 16.0 BSC E BSC L L REF R R S 0.20 θ θ1 0 0 θ θ Unit: mm REF: Reference BSC: Basic Spacing between Centers (integrated circuit package dimension) JEILIN Technology Co., Ltd. 14 of /1/23

15 JEILIN Technology Co., Ltd. 8F, No. 179, Jian Yi Rd., Chung Ho, Taipei Hsien, Taiwan Tel: Fax: Website: JEILIN Technology Corp., Ltd. All rights reserved. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this document is subject to change without prior notice. The information contained in this document is presented only as a guide for applications of our products. No responsibility is assumed by JEILIN Technology for any infringements of intellectual property or other rights of the third parties, which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of JEILIN Technology or others. No part of this document may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of JEILIN Technology. JEILIN Technology Co., Ltd. 15 of /1/23