Recommended JTAG Circuitry for Debug with Intel Xscale Microarchitecture

Transcription

1 Recommended JTAG Circuitry for Debug with Intel Xscale Microarchitecture Application Note June 2001 Document Number:

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel XScale microarchitecture may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at Copyright Intel Corporation, 2001 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, icat, icomp, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. *ARM and StrongARM are registered trademarks of ARM, Ltd. 2 Application Note

3 Contents Contents 1.0 Introduction Requirements JTAG Signals / Header System Requirements Hardware Requirements Macraigor Raven* and Wind River Systems visionprobe* / visionice* ARM* Multi-ICE* References...9 Figures 1 JTAG Header Example JTAG Signals at Power-Up Example JTAG Signals at Debug Start-Up Example Power-Up Circuit for ntrst...8 Tables Application Note 3

4 Contents Revision History Date Revision Description June Initial release. 4 Application Note

5 Introduction 1.0 Introduction Certain restrictions exist in order to use JTAG based debuggers with the Intel XScale microarchitecture (ARM* Architecture compliant). This is primarily due to the Tap Controller reset requirements of the Intel processor with Intel XScale microarchitecture and the reset requirements of specific JTAG debuggers. The following sections outline these requirements along with suggestions for circuitry to alleviate potential problems. 2.0 Requirements The Intel processor with Intel XScale microarchitecture, like many others, requires that ntrst (Tap Reset) is asserted low during power up for at least 32 core clock cycles. This is to ensure a fully initialized boundary scan chain. Failure to comply with this requirement may result in spurious behavior of the application. The ARM Multi-ICE JTAG debugger requires that ntrst is always weakly pulled high. This requirement stems from the fact that the debugger can only assert ntrst (drive low). Both reset signals coming from the Multi-ICE (ntrst and nsrst) are open collector and must be weakly pulled high in order to avoid unintentional resets (System or TAP). Application Note 5

6 JTAG Signals / Header 3.0 JTAG Signals / Header Figure 1 is the pin definition (20-pin standard ARM connector) for JTAG (See specific Product Design Guide for part number information). Figure 1. JTAG Header VTref 1 2 Vsupply ntrst 3 4 TDI 5 6 TMS 7 8 TCK 9 10 RTCK TD nsrst DBGRQ DGBACK A The ARM Multi-ICE debugger along with the Macraigor Raven* and Wind River Systems visionprobe* / visionice* utilize this connector. The main difference to be noted is the specific implementation of ntrst for each debugger. The Macraigor Raven implementation actively drives ntrst (high and low). The Wind River Systems visionprobe / visionice can configure ntrst active or open collector (only drive low). ARM Multi-ICE is configured as open collector only. 6 Application Note

7 System Requirements 4.0 System Requirements In order to successfully invoke a debug session, the JTAG debug unit must be able to control ntrst and nsrst independently. The ntrst signal allows the debugger to get the TAP controller in a known state. The nsrst signal allows the debugger to control system/processor reset in order to download the debug handler via the JTAG interface. See Figure 2, Example JTAG Signals at Power-Up and Figure 3, Example JTAG Signals at Debug Start-Up. Figure 2. Note: Figure 2 and Figure 3 are examples and do not reflect actual signal timings. Example JTAG Signals at Power-Up VCC ntrst nsrst TCK TMS TDI TD0 A Figure 3. Example JTAG Signals at Debug Start-Up VCC ntrst nsrst TCK TMS TDI TD0 A Application Note 7

8 Hardware Requirements 5.0 Hardware Requirements Due to the conflicting requirements of Multi-ICE and the Intel processor, it is necessary to incorporate a circuit that can drive ntrst low at power up and weakly pull it high at all other times. This section details the circuits required for ntrst when using the Macraigor Raven, Wind River Systems visionprobe / visionice, and ARM Multi-ICE. Note: This section does not discuss circuitry needed for nsrst, due to varying system level requirements. 5.1 Macraigor Raven* and Wind River Systems visionprobe* / visionice* Both the Macraigor Raven and Wind River Systems visionprobe / visionice (when configured as active) do not require any special power-up circuitry. Simply, the requirement is that ntrst is weakly pulled down at the processor. It is suggested that the value of the pull-down resistor is 10kΩ or greater. The value of this resistor should be confirmed with the JTAG debugger manufacturer to ensure optimal performance. 5.2 ARM* Multi-ICE* The ARM Multi-ICE debugger requires special power-up circuitry due to the open collector implementation of the ntrst signal. This power-up circuit must ensure that ntrst is asserted (low)atpoweronandweaklypulledhighthereafter.seefigure 4, Example Power-Up Circuit for ntrst. This circuit is a universal solution and will work with other JTAG debug systems. Figure 4. Example Power-Up Circuit for ntrst ntrst-dgb 3.3 V 3.3 V 1 kω 3 MR# RESET# 2 220Ω ntrst 4 VCC µF MAX811S A Application Note

9 References 6.0 References 1. Multi-ICE System Design Considerations Application Note 72 ( 2. Intel I/O Processor Chipset with Intel XScale Microarchitecture Design Guide ( 3. Intel Processor Evaluation Platform Board Schematics ( 4. Max811/812 Datasheet ( Application Note 9

10 References This page intentionally left blank. 10 Application Note