Where Have We Been? Ch. 6 Memory Technology

Transcription

1 Where Have We Been? Combinational and Sequential Logic Finite State Machines Computer Architecture Instruction Set Architecture Tracing Instructions at the Register Level Building a CPU Pipelining Where Are We Going? Memory Technology 2 Ch. 6 Memory Technology Topics Memory Hierarchy Basics Static RAM Dynamic RAM Magnetic s Access Time Gap Impact of Moore s Law Moore s Law Transistors / Chip doubles every 18 months Performance factors of systems built with integrated circuit technology follow exponential curve e.g., computer speed / memory capacities double every 18 months Implications Computers 10 years from now will run 100 X faster Problems that appear computationally intractable today may be straightforward tomorrow Must not limit future planning with today s technology Example Application Domains Speech recognition Breaking secret codes Digital Video 4

2 Computer System Processor Reg Cache Cache Memory-I/O bus bus Memory Memory I/O I/O I/O I/O I/O I/O Display Display Network Network 5 Levels in Memory Hierarchy CPU CPU regs regs cache virtual memory C 8 B A 32 B 4/8 KB C Memory Memory H E size: speed: $/Mbyte: block size: Register L1 Cache Memory 256 B ns 8 B 16KB-64KB 2-3 ns $20/MB 32 B MB 60 ns $0.12/MB 4-8 KB GB 8-9 ms $0.002/MB larger, slower, cheaper 6 Static RAM (SRAM) Fast 1~2 nsec access time Persistent as long as power is supplied no refresh required Expensive ~$20/MByte 4/6 transistors/bit Stable High immunity to noise and environmental disturbances Technology for caches 7

3 Anatomy of an SRAM Cell bit line bit line b b word line Stable Configurations (6 transistors) Terminology: bit line: carries data word line: used for addressing 8 Example SRAM Configuration (16 x 8) W0 b7 b7 b1 b1 b0 b0 A0 A1 A2 A3 W1 Address Address decoder decoder W15 memory cells R/W Input/output lines d7 d1 d0 9 Dynamic RAM (DRAM) Slower than SRAM access time ~50 nsec (true DRAM, not SDRAM) Not persistent every row must be accessed every ~1 ms (refreshed) Cheaper than SRAM ~$0.12 / MByte 1 transistor/bit Fragile electrical noise, light, radiation Workhorse memory technology 10

4 Anatomy of a DRAM Cell Bit Line Access Transistor Word Line Storage Node C node C BL A DRAM cell is constructed using a capacitor and a single transistor The capacitor is the state storing element. The charge stored in the capacitor slowly drains away (in about ms, average is 32 ms). Also, whenever the cell is read the charge on the capacitor is depleted. Refreshing is needed periodically and after each read. 11 Addressing Arrays with Bits Array Size R rows, R = 2 r C columns, C = 2 c N = R * C bits of memory Addressing Addresses are n bits, where N = 2 n Row (address) = address / C leftmost r bits of address Col (address) = address % C rightmost bits of address Example: R = 2 C = 4 N = 8 Addr = 6 12 address = row col row 1 col 2 r n c Example 2-Level Decode DRAM (64Kx1) RAS 256 Rows row A15-A0 col Provide 16-bit address in two 8-bit chunks Row Row address address latch latch Column Column address address latch latch 8 \ 8 \ Row Row decoder decoder 256x256 cell cell array array 256 Columns column column R/W column column latch latch and and decoder decoder CAS 13 Dout Din

5 Observations About DRAMs Timing Access time (= 50ns) < cycle time (= 90ns) Need to rewrite row Must Refresh Periodically Perform complete memory cycle for each row Approximately once every 1ms Sqrt(n) cycles Handled in background by memory Inefficient Way to Get a Single Bit Effectively read entire row of Sqrt(n) bits 14 Magnetic s surface spins at ,000 RPM The surface consists of a set of concentric magnetized rings called tracks read/write head arm Each track is divided into sectors 15 The read/write head floats over the disk surface and moves back and forth on an arm from track to track. Capacity Parameter 18GB Example Number Platters 12 Surfaces / Platter 2 Number of tracks 6962 Number sectors / track 213 Bytes / sector 512 Total Bytes 18,221,948,928 16

6 Operation Operation Read or write complete sector Seek Position head over proper track Typically 6-9ms Rotational Latency Wait until desired sector passes under head Worst case: complete rotation 10,025 RPM 6 ms Read or Write Bits Transfer rate depends on # bits per track and rotational speed E.g., 213 * 512 = 18 MB/sec. Modern disks have external transfer rates of up to 100 MB/sec 17 Performance Getting First Byte Seek + Rotational latency = 7,000 19,000 µsec Getting Successive Bytes ~ 0.06 µsec each roughly 100,000 times faster than getting the first byte! Optimizing Performance: Large block transfers are more efficient Try to do other things while waiting for first byte switch context to other computing task processor is interrupted when transfer completes Processor Signals Controller Read sector X and store starting at memory address Y 2. Read Occurs Direct Memory Access (DMA) transfer Under control of I/O 3. I/O Controller Signals Completion Interrupts processor Can resume suspended process / System Interface (2) DMA Transfer Processor Reg Cache Cache Memory-I/O bus bus Memory Memory (1) Initiate Sector Read (3) Read Done I/O I/O 19

7 Magnetic Technology Seagate ST-12550N Barracuda 2 Linear density 52,187. bits per inch (BPI) Bit spacing 0.5 µm Track density 3,047. tracks per inch (TPI) Track spacing 8.3 µm Total tracks 2,707. tracks Rotational Speed RPM Avg Linear Speed 86.4 kilometers / hour Head Floating Height 0.13 microns Analogy: put the Sears Tower on its side fly it around the world, 2.5cm above the ground each complete orbit of the earth takes 8 seconds 20 CD Read Only Memory (CDROM) Basis Optical recording technology developed for audio CDs 74/80 minutes playing time 44,100 samples / second 2 X 16-bits / sample (Stereo) Raw bit rate = 172 KB / second Add extra 288 bytes of error correction for every 2048 bytes of data Cannot tolerate any errors in digital data, whereas OK for audio Bit Rate 172 * 2048 / ( ) = 150 KB / second For 1X CDROM N X CDROM gives bit rate of N * 150 E.g., 12X CDROM gives 1.76 MB / second Capacity 74 Minutes * 150 KB / second * 60 seconds / minute = 650 MB 21 Storage Trends SRAM metric :1980 $/MB 19,200 2, access (ns) metric :1980 DRAM $/MB 8, ,300 access (ns) typical size(mb) ,000 metric :1980 $/MB ,000 access (ms) typical size(mb) ,000 9,000 9,000 (Culled from back issues of Byte and PC Magazine) 22

8 Storage Price: $/MByte 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 SRAM DRAM 1.E+00 1.E-01 1.E Storage Access Times (nsec) 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 SRAM DRAM 1.E+03 1.E+02 1.E+01 1.E Processor clock rates Processors metric :1980 typical clock(mhz) processor Pentium P-III culled from back issues of Byte and PC Magazine 25

9 The CPU vs. DRAM Latency Gap (ns) 1.E+03 1.E+02 SRAM DRAM CPU cycle 1.E+01 1.E Memory Technology Summary Cost and Density Improving at Enormous Rates Speed Lagging Processor Performance Memory Hierarchies Help Narrow the Gap: Small fast SRAMS (cache) at upper levels Large slow DRAMS (main memory) at lower levels Incredibly large & slow disks to back it all up Locality of Reference Makes It All Work Keep most frequently accessed data in fastest memory 27