Memory Hierarchy Recall the von Neumann bottleneck - single, relatively slow path between the CPU and main memory.

Transcription

1 Memory Hierarchy Goal: Fast, unlimited storage at a reasonable cost per bit. Recall the von Neumann bottleneck - single, relatively slow path between the CPU and main memory. Cache - 1

2 Typical system view of the memory hierarchy Figure 4.3 Cache and Main Memory Cache -

3 Table 4.3 Cache Sizes of Some Processors Processor Type Year of Introduction L1 L L3 IBM 360/85 Mainframe 1968 to 3 KB PDP-11/70 Minicomputer KB VAX 11/780 Minicomputer 1978 KB IBM 3033 Mainframe KB IBM 3090 Mainframe to 56 KB Intel PC KB Pentium PC KB/8 KB 56 to 51 KB PowerPC 601 PC KB PowerPC 60 PC KB/3 KB PowerPC G4 PC/server KB/3 KB 56 KB to 1 MB MB IBM S/390 G4 Mainframe KB 56 KB MB IBM S/390 G6 Mainframe KB 8 MB Pentium 4 PC/server KB/8 KB 56 KB IBM SP High-end server/ supercomputer KB/3 KB 8 MB CRAY MTAb Supercomputer KB MB Itanium PC/server 001 KB/ KB 96 KB 4 MB SGI Origin 001 High-end server KB/3 KB 4 MB Itanium PC/server 00 3 KB 56 KB 6 MB IBM POWER5 High-end server KB 1.9 MB 36 MB CRAY XD-1 Supercomputer KB/64 KB 1MB Cache - 3

4 Main Idea of a Cache - keep a copy of frequently used information as close (w.r.t access time) to the processor as possible. CPU Memory System Bus Steps when the CPU generates a memory request: 1) check the (faster) first ) If the addressed memory value is in the (called a hit), then no need to access memory 3) If the addressed memory value is NOT in the (called a miss), then transfer the block of memory containing the reference to. (The CPU is stalled waiting while this occurs) 4) The supplies the memory value from the. Effective Memory Access Time Suppose that the hit time is 5 ns, the miss penalty is 0 ns, and the hit rate is 99%. Effective Access Time l (hit time * hit probability) + (miss penalty * miss probability) Effective Access Time = 5 * * (1-0.99) = = 6.55 ns Cache - 4

5 One way to reduce the miss penalty is to not have the wait for the whole block to be read from memory before supplying the accessed memory word. Figure 4.5 Cache Read Operation Cache - 5

6 Fortunately, programs exhibit locality of reference that helps achieve high hit-rates: 1) spatial locality - if a (logical) memory address is referenced, nearby memory addresses will tend to be referenced soon. ) temporal locality - if a memory address is referenced, it will tend to be referenced again soon. Typical Flow of Control in a Program block boundaries "Text" segment "Data" segment a locality of reference a locality of reference for i := end for block 5 block 6 block 7 block 8 Data references within the loop i: block 103 block 10 block 101 block 100 Run-Time Stack Global Data Cache - 6

7 Cache - Small fast memory between the CPU and RAM/Main memory. Example: 3-bit address 51 KB ( 19 ) 8 byte per block/line byte-addressable memory Number of Cache Line = size of size of line = 19 3 = Three Types of Cache: 1) Direct-mapped - a memory block maps to a single line Line # Block # block bit address: 13 line # 3 offset Cache - 7

8 Cache - Small fast memory between the CPU and RAM/Main memory. Example: 3-bit address, byte-addressable memory 51 KB ( 19 ) 8 byte per block/line Number of Cache Line = size of size of line = 19 3 = ) Fully-Associative Cache - a memory block can map to any line Line # Block # block bit address: 9 3 offset Advane: Flexibility on what s in the Disadvane: Complex circuit to compare all s of the with the in the target address Therefore, they are expensive and slower so use only for small s (say 8-64 lines) Replacement algorithms - on a miss of a full, we must select a block in the to replace LRU - replace the block that has not been used for the longest time (need additional bits) Random - select a block randomly (only slightly worse that LRU) FIFO - select the block that has been in the for the longest time (slightly worse that LRU) Cache - 8

9 3) Set-Associative Cache - a memory block can map to a small (, 4, or 8) set of lines Common Possibilities: -way set associative - each memory block can map to either of two lines in the 4-way set associative - each memory block can map to either of four lines in the Number of Sets = number of lines size of each set = 4 = = 14 Other Bits 4-way Set Associative Cache way 0 way 1 way way Set # Block # 0 1 block block block block bit address: set # offset Cache - 9

10 Figure 4. Varying Associativity over Cache Size tio ra it H k direct -way 4-way 8-way -way k 4k 8k k Cache size(bytes) 3k 64k 18k 56k 51k 1M Cache - 10

11 Block/Line Size The larger the line size: fewer line for the same size improves hit rate since larger blocks are read when a miss occurs larger miss penalty since more words are read from memory when a miss occurs Number of Caches: Issues: Number of levels CPU Memory L1 64KB L 51KB unified vs. split s split s - separate smaller s for data and instructions unified - data and instructions in the same Advanes of each: split s - reduces contention for memory between instruction and data accesses unified s - balances the load between instructions and data automatically (e.g., a tight loop might need more data blocks than instruction blocks) Cache - 11

12 Types of Cache Misses: Compulsory Misses: misses due to the first access to a block Capacity Misses: misses on blocks that were in the, but were forced out due to the capacity of the. Conflict/Collision Misses: misses due to conflict caused by the direct or set-associated mapping that are eliminated by using fully-associative mapping Studying the performance of a vs. characteristics of the : Cache - 1

13 Write Policy - do we keep the and memory copy of a block identical??? CPU CPU Memory I/O 5 :X 5 :X 5 :X (can read and write memory) Just reading a shared variable causes no problems - all s have the same value Writing can cause a -coherency problem CPU 0 CPU 1 Memory X:=X +; X:=X +1; 5 7 :X 5 6 :X 5 :X I/O (can read and write memory) Write Policies write back - CPU only changes local copy until that block is replaced, then it is written back to memory (a UPDATE/DIRTY bit is associated with each line to indicate if it has been modified). If we assume that CPU 0 writes the block back to memory before CPU 1, then X s resulting value will be 6. Thereby, discarding the effect of X:=X+. Disadvane(s) of writeback? Advane(s) of writeback? write through - on a write to a block, write to the main memory copy to keep it up to date To avoid stalling the CPU on a write, a write buffer can be used to allow the CPU to continue execution without stalling to wait for the write. write miss options: write allocate - the block written to is read into the before updating no-write allocate - no block is allocated in the and only the lower-level memory is modified Cache - 13

14 Cache Coherency Solutions a) bus watching with write through / Snoopy s - s eavesdrop on the bus for other s write requests. If the contains a block written by another, it take some action such as invalidating it s copy. CPU CPU Memory I/O 5 :X 5 :X 5 :X (can read and write memory) The MESA protocol is a common -coherency protocol. b) noncachable memory - part of memory is designated as noncachable, so the memory copy is the only copy. Access to this part of memory always generate a miss. CPU CPU Memory noncachable part of memory 5 :X I/O (can read and write memory) c) Hardware transparency - additional hardware is added to update all s and memory at once on a write. Cache - 14

15 Figure 4.18 Pentium 4 Block Diagram Cache - 15