P160 Prototype Module User s Guide

Transcription

1 P60 Prototype Module User s Guide Version.0 February 2002

2 WARRANTY AND LIABILITY DISLAIMER Notwithstanding any additional, different or conflicting terms or conditions contained in the purchaser s ordering document or other document, to the maximum extent permitted by applicable law, Memec, LL and its subsidiaries ( Insight and Impact ) expressly disclaim all warranties, conditions, or representations, express, implied, statutory or otherwise, regarding this product or any other services provided by Memec in connection with this product, all of which are provided as is, and this disclaimer shall apply to any implied warranties or conditions of merchantability, satisfactory or merchantable quality and fitness for a particular purpose, or those arising from a course of dealing or usage of trade. Under no circumstances (to the maximum extent permitted by applicable law), shall Memec be liable to the purchaser or to any third party, for a claim of any kind arising as a result of, or related to the product, whether in contract, in tort (including negligence or strict liability), under any warranty, or otherwise. This limitation of liability shall apply notwithstanding the fact that a claim brought by the purchaser or any third party is for indirect, special or consequential damages (including lost profits), even if Memec has been advised of the possibility of such damages, or for warranties granted by the purchaser to any third party. The purchaser acknowledges and agrees that the price for this product is based in part upon these limitations, and further agrees that these limitations shall apply notwithstanding any failure of essential purpose of any limited remedy.

3 Table of ontents OVERVIEW... 2 P60 PROTOTYPE MODULE... 3 USER HEADERS...2 REVISION HISTORY...5 APPENDIX A - P60 PROTOTYPE MODULE SHEMATIS...6 February 3, 2002 i

4 Figures FIGURE P60 PROTOTYPE MODULE BOARD... FIGURE 2 P60 PROTOTYPE MODULE BLOK DIAGRAM...2 February 3, 2002 ii

5 Tables TABLE J3 PIN ASSIGNMENTS...2 TABLE 2 J4 PIN ASSIGNMENTS...3 TABLE 3 J5 PIN ASSIGNMENTS...3 TABLE 4 J6 PIN ASSIGNMENTS...4 February 3, 2002 iii

6 Overview The P60 Prototype Module provides a useful expansion, probe, and prototype feature in a small, low cost daughter card form-factor, compatible with any main system board containing the P60 expansion interface. The Spartan-II, Spartan-IIE, and Virtex-II system boards from Memec all include the P60 interface and can support the P60 ommunications Module. Proper user configuration of the main system board is required to enable the P60 interface and the corresponding expansion module test points. This user guide helps provide the necessary details to develop such a configuration. omplete board schematics are provided in Appendix A for your reference. 2 P60 Prototype Module The Insight MicroBlaze Development kit includes a P60 Prototype module, which connects to the main system development board via the I/O module connectors. This board can be used to prototype various user I/O interfaces. A high-level block diagram of this module is given below followed by tables that show the connector pin assignments. Figure P60 Prototype Module Board February 3, 2002

7 2 2 P60 Prototype Board 2 2 J3 onnector J4 onnector Prototype Area J5 onnector J6 onnector Vin 2.5V user led led led led Figure 2 P60 Prototype Module Block Diagram 3 User Headers The P60 Prototype module provides four 2 x 20 headers for connection to the P60 Expansion signals. These signals are driven from the main system board and are defined by the FPGA design implemented. Tables through 4 define the connections between the headers and the P60 connectors. orresponding connections between the P60 connectors and the system board FPGA can be found in the related system board User Guide. Table J3 Pin Assignments FPGA Pin # J3 Pin # FPGA Pin # Vin 2 2.5V 3 4 RIOA 5 6 N RIOA2 7 8 LIOB8 LIOB9 9 0 LIOB0 LIOB 2 LIOB2 LIOB3 3 4 LIOB4 LIOB5 5 6 LIOB6 LIO7 7 8 LIOB8 LIOB LIOB20 LIOB LIOB22 LIOB LIOB24 LIOB LIOB26 LIOB LIOB28 LIOB LIOB30 LIOB LIOB32 LIOB LIOB34 LIOB LIOB36 LIOB LIOB38 LIOB LIOB40 February 3,

8 Table 2 J4 Pin Assignments FPGA Pin # J4 Pin # FPGA Pin # Vin 2 2.5V 3 4 RIOB2 TK 5 6 LIOA9 TDO 7 8 LIOA TDI 9 0 LIOA3 TMS 2 LIOA5 FPGA.BITSTREAM 3 4 LIOA7 SM.DOUT/BUSY 5 6 LIOA9 FPGA.LK 7 8 LIOA2 DONE 9 20 LIOA23 INITn 2 22 LIOA25 PROGRAMn LIOA LIOA LIOA LIOA LIOA LIOA LIOA RIOA RIOA40 Table 3 J5 Pin Assignments FPGA Pin # J5 Pin # FPGA Pin # Vin 2 2.5V 3 4 RIOB4 N 5 6 RIOB6 JTAG_LOOPBAK 7 8 RIOB8 JTAG_LOOPBAK 9 0 RIOB0 N 2 RIOB2 N 3 4 RIOB4 N 5 6 RIOB6 N 7 8 RIOB8 N 9 20 RIOB20 N 2 22 RIOB22 N RIOB RIOB RIOB RIOB RIOB RIOB RIOB RIOB RIOB40 February 3,

9 Table 4 J6 Pin Assignments FPGA Pin # J6 Pin # FPGA Pin # Vin 2 2.5V 3 4 RIOA4 5 6 RIOA3/USERLED RIOA6 7 8 RIOA5 RIOA8 9 0 RIOA7 RIOA0 2 RIOA9 RIOA2 3 4 RIOA RIOA4 5 6 RIOA3 RIOA6 7 8 RIOA5 RIOA RIOA7 RIOA RIOA9 RIOA RIOA2 RIOA RIOA23 RIOA RIOA25 RIOA RIOA27 RIOA RIOA29 RIOA RIOA3 RIOA RIOA33 RIOA RIOA35 RIOA RIOA37 February 3,

10 Revision History V.0 Initial Release 2/3/02 February 3,

11 Appendix A - P60 Prototype Module Schematics February 3,

12 NAME LED TEST LOOP H R 750R DS LST670-HK JP2 Test Point Loop - Red H G G R2 330R DS2 LST670-HK JP4 Test Point Loop - Red F F 2.5V 2.5V R3 30 DS3 LST670-HK 2.5V JP6 Test Point Loop - Red E E JP7 Test Point Loop - Black D JP8 Test Point Loop - Black D RIO.A3/USERLED USER R4 30 DS4 LST670-HK B B A V2MB Test module LEDS A MemecBoard <OrgAddr> <OrgAddr2> <OrgAddr3> <OrgAddr4> 2 Last Modified Friday, October 05, 200 Size Rev Designer Sheet Jim Elliott of 3

13 D D B B A A T2E 7S8 V2MB Test module MemecBoard Friday, October 05, Suite 540, 22 3st Ave. NE algary, Alberta anada Jim Elliott EXPANSION ONNETORS Size Rev Sheet of Last Modified Designer RIO.A RIO.A2 RIO.A3/USERLED RIO.A4 RIO.A7 RIO.A5 RIO.A6 RIO.A8 RIO.A3 RIO.A RIO.A9 RIO.A0 RIO.A2 RIO.A6 RIO.A4 RIO.A5 RIO.A2 RIO.A9 RIO.A7 RIO.A8 RIO.A20 RIO.A24 RIO.A22 RIO.A23 RIO.A29 RIO.A27 RIO.A25 RIO.A26 RIO.A28 RIO.A32 RIO.A30 RIO.A3 RIO.A37 RIO.A35 RIO.A33 RIO.A34 RIO.A36 RIO.A40 RIO.A38 RIO.A39 RIO.B2 RIO.B4 RIO.B6 RIO.B8 RIO.B4 RIO.B2 RIO.B6 RIO.B0 RIO.B30 RIO.B28 RIO.B22 RIO.B26 RIO.B20 RIO.B24 RIO.B32 RIO.B8 RIO.B38 RIO.B36 RIO.B40 RIO.B34 LIO.B30 LIO.B27 LIO.A33 LIO.A3 LIO.B28 LIO.A25 LIO.A2 LIO.B5 LIO.B25 LIO.B7 LIO.B26 LIO.B36 LIO.A29 LIO.B37 LIO.A23 LIO.A9 LIO.B35 LIO.B20 LIO.B6 LIO.B3 LIO.B29 LIO.B9 LIO.A7 TMS LIO.A37 LIO.B32 LIO.B2 TK LIO.B33 LIO.B40 LIO.A39 LIO.B24 LIO.B23 LIO.B22 LIO.B38 LIO.A35 LIO.B8 LIO.B3 LIO.B2 LIO.B39 LIO.B34 LIO.A27 LIO.B4 FPGA.BITSTREAM SM.DOUT/BUSY FPGA.LK PROGRAMn INITn DONE LIO.B LIO.B0 LIO.B8 LIO.B9 LIO.A5 LIO.A3 LIO.A LIO.A9 TDI TDO 2.5V 2.5V JX2 X5 Socket JX3 B A B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B0 A0 B A B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B20 A20 B2 A2 B22 A22 B23 A23 B24 A24 B25 A25 B26 A26 B27 A27 B28 A28 B29 A29 B30 A30 B3 A3 B32 A32 B33 A33 B34 A34 B35 A35 B36 A36 B37 A37 B38 A38 B39 A39 B40 A40 DISPLAY.F TK IO DISPLAY.G IO2 TMS IO3 DISPLAY.E IO4 TDI IO5 DISPLAY.D IO6 TDO IO7 SS.DONE IO8 DISPLAY.DP IO9 SS.INITn IO0 DISPLAY. IO SS.DATA DISPLAY.B IO2 SS.PROGRAMn IO3 DISPLAY.A IO4 SS.LK IO5 DIP IO6 LED IO7 DIP2 IO8 LED2 IO9 PUSH IO20 DIP3 IO2 PUSH2 IO22 DIP4 IO23 DIP5 IO24 PUSH3 IO25 DIP6 IO26 PUSH4 IO27 IO28 RXD IO29 DIP7 IO30 TXD IO3 DIP8 JX X5 Socket JX4 B A B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B0 A0 B A B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B20 A20 B2 A2 B22 A22 B23 A23 B24 A24 B25 A25 B26 A26 B27 A27 B28 A28 B29 A29 B30 A30 B3 A3 B32 A32 B33 A33 B34 A34 B35 A35 B36 A36 B37 A37 B38 A38 B39 A39 B40 A40 AIO AIO6 BIO2 AIO7 AIO3 AIO8 AIO4 AIO9 AIO5 AIO20 AIO6 AIO2 AIO7 AIO22 AIO8 AIO23 AIO9 AIO24 AIO0 AIO25 AIO AIO26 AIO2 AIO27 AIO3 AIO28 AIO4 AIO29 AIO5 AIO30 AIO3 AIO46 AIO32 AIO47 AIO33 AIO48 AIO34 AIO49 AIO35 AIO50 AIO36 AIO5 AIO37 AIO52 AIO38 AIO53 AIO39 AIO54 AIO40 AIO55 AIO4 AIO56 AIO42 AIO57 AIO43 AIO58 AIO44 AIO59 AIO45 AIO60

14 V 2.5V 2.5V 2.5V J3 J4 J5 J6 D RIO.A RIO.A2 LIO.B9 LIO.B LIO.B3 LIO.B5 LIO.B7 LIO.B9 LIO.B2 LIO.B23 LIO.B25 LIO.B27 LIO.B29 LIO.B3 LIO.B33 LIO.B35 LIO.B37 LIO.B ON2X20 LIO.B8 LIO.B0 LIO.B2 LIO.B4 LIO.B6 LIO.B8 LIO.B20 LIO.B22 LIO.B24 LIO.B26 LIO.B28 LIO.B30 LIO.B32 LIO.B34 LIO.B36 LIO.B38 LIO.B40 TK TDO TDI TMS FPGA.BITSTREAM SM.DOUT/BUSY FPGA.LK DONE INITn PROGRAMn ON2X20 RIO.B2 LIO.A9 LIO.A LIO.A3 LIO.A5 LIO.A7 LIO.A9 LIO.A2 LIO.A23 LIO.A25 LIO.A27 LIO.A29 LIO.A3 LIO.A33 LIO.A35 LIO.A37 LIO.A39 RIO.A39 RIO.A40 ompletes JTAG chain in loopback mode ON2X20 RIO.B4 RIO.B6 RIO.B8 RIO.B0 RIO.B2 RIO.B4 RIO.B6 RIO.B8 RIO.B20 RIO.B22 RIO.B24 RIO.B26 RIO.B28 RIO.B30 RIO.B32 RIO.B34 RIO.B36 RIO.B38 RIO.B40 RIO.A4 RIO.A6 RIO.A8 RIO.A0 RIO.A2 RIO.A4 RIO.A6 RIO.A8 RIO.A20 RIO.A22 RIO.A24 RIO.A26 RIO.A28 RIO.A30 RIO.A32 RIO.A34 RIO.A36 RIO.A ON2X20 RIO.A3/USERLED RIO.A5 RIO.A7 RIO.A9 RIO.A RIO.A3 RIO.A5 RIO.A7 RIO.A9 RIO.A2 RIO.A23 RIO.A25 RIO.A27 RIO.A29 RIO.A3 RIO.A33 RIO.A35 RIO.A37 D B J7 J8 J9 J0 J J2 J3 J4 J5 ON ON ON ON ON ON ON ON ON J9 J20 J2 J22 J23 J24 J25 J26 J27 ON ON ON ON ON ON ON ON ON J3 J32 J33 J34 J35 J36 J37 J38 J39 ON ON ON ON ON ON ON ON ON J43 J44 J45 J46 J47 J48 J49 J50 J5 ON ON ON ON ON ON ON ON ON J55 J56 J57 J58 J59 J60 J6 J62 J63 ON ON ON ON ON ON ON ON ON J67 J68 J69 J70 J7 J72 J73 J74 J75 ON ON ON ON ON ON ON ON ON J79 J80 J8 J82 J83 J84 J85 J86 J87 ON ON ON ON ON ON ON ON ON J9 J92 J93 J94 J95 J96 J97 J98 J99 ON ON ON ON ON ON ON ON ON J03 J04 J05 J06 J07 J08 J09 J0 J ON ON ON ON ON ON ON ON ON J5 J6 J7 J8 J9 J20 J2 J22 J23 ON ON ON ON ON ON ON ON ON J6 ON J28 ON J40 ON J52 ON J64 ON J76 ON J88 ON J00 ON J2 ON J24 ON J7 ON J29 ON J4 ON J53 ON J65 ON J77 ON J89 ON J0 ON J3 ON J25 ON J8 ON J30 ON J42 ON J54 ON J66 ON J78 ON J90 ON J02 ON J4 ON J26 ON B A J27 ON J39 ON J5 ON J63 ON J75 ON J87 ON J99 ON J2 ON J223 ON J235 ON 5 J28 ON J40 ON J52 ON J64 ON J76 ON J88 ON J200 ON J22 ON J224 ON J236 ON J29 ON J4 ON J53 ON J65 ON J77 ON J89 ON J20 ON J23 ON J225 ON J237 ON J30 ON J42 ON J54 ON J66 ON J78 ON J90 ON J202 ON J24 ON J226 ON J238 ON J3 ON J43 ON J55 ON J67 ON J79 ON J9 ON J203 ON J25 ON J227 ON J239 ON 4 J32 ON J44 ON J56 ON J68 ON J80 ON J92 ON J204 ON J26 ON J228 ON J240 ON J33 ON J45 ON J57 ON J69 ON J8 ON J93 ON J205 ON J27 ON J229 ON J24 ON J34 ON J46 ON J58 ON J70 ON J82 ON J94 ON J206 ON J28 ON J230 ON J242 ON 3 J35 ON J47 ON J59 ON J7 ON J83 ON J95 ON J207 ON J29 ON J23 ON J243 ON J36 ON J48 ON J60 ON J72 ON J84 ON J96 ON J208 ON J220 ON J232 ON J244 ON J37 ON J49 ON J6 ON J73 ON J85 ON J97 ON J209 ON J22 ON J233 ON J245 ON 2 J38 ON J50 ON J62 ON J74 ON J86 ON J98 ON J20 ON J222 ON J234 ON J246 ON V2MB Test Module HEADERS MemecBoard Suite 540, 22 3st Ave. NE algary, Alberta anada T2E 7S8 Last Modified Friday, October 05, 200 Size Rev Designer Sheet Jim Elliott 3 of 3 A