An Instruction Set Extension for Fast and Memory- Efficient AES Implementation. Stefan Tillich, Johann Großschädl, Alexander Szekely
|
|
|
- William Eaton
- 5 years ago
- Views:
Transcription
1 Institute for Applied Information Processing and Communications () GRAZ UNIVERSITY OF TECHNOLOGY An Instruction Set Extension for Fast and Memory- Efficient AES Implementation Stefan Tillich, Johann Großschädl, Alexander Szekely Conference on Communications and Multimedia Security (CMS '05) Institute for Applied Information Processing and Communications () Group Faculty of Computer Science Graz University of Technology
2 Introduction NIST's Advanced Encryption Standard (AES) defines a symmetric-key cipher Lot of focus on efficient implementations (both software and hardware) Pure software vs. pure hardware implementations Our work deals with optimizing AES software implementations on 32-bit platforms with cryptographic extensions (HW/SW co-design) ISE for Fast and Memory-Efficient AES 2
3 AES Overview AES_encrypt(byte in[4*4], byte out[4*4], word w[4*(nr+1)]) byte state[4,4]; state = in; AddRoundKey(state, w[0, 3]); // Initial AddRoundKey for round = 1 step 1 to Nr 1 // (Nr-1) rounds SubBytes(state); ShiftRows(state); MixColumns(state); AddRoundKey(state, w[round*4, (round+1)*4-1]); end for // Last round (no MixColumns) SubBytes(state); ShiftRows(state); AddRoundKey(state, w[nr*4, (Nr+1)*4-1]); out = state; end s 0,0 s 1,0 s 2,0 s 3,0 s 0,1 s 1,1 s 2,1 s 3,1 s 0,2 s 1,2 s 2,2 s 3,2 s 0,3 s 1,3 s 2,3 s 3,3 State matrix ISE for Fast and Memory-Efficient AES 3
4 AES Overview (cont'd) Each round consists of four transformations: SubBytes, ShiftRows, MixColumns, AddRoundKey ShiftRows, AddRoundKey simple to implement in software SubBytes requires an affine transformation and inversion in GF(2 8 ). Not efficient to calculate on general-purpose processors (normally implemented with a 256-byte lookup table: SBOX lookup) MixColumns multiplies two polynomials with coefficients in GF(2 8 ) ISE for Fast and Memory-Efficient AES 4
5 AES Optimization Whole round (SubBytes, ShiftRows, MixColumns) as lookup (T lookup). Requires a lookup table of at least 1 kb for encryption and decryption each. May be slow on systems with slow memory and no or small cache Facilitate calculation of transformations with instruction set extensions ISE for Fast and Memory-Efficient AES 5
6 AES with Lookup Tables Possible table sizes (AES encryption): 256 bytes, 1280 bytes, 4352 bytes, 5 kb, 8 kb) Same options for decryption Tradeoff between table size and performance (instruction count) But larger tables put higher strain on cache subsystem -> possible performance degradation ISE for Fast and Memory-Efficient AES 6
7 AES: Just SBOX lookup AES_encrypt() AddRoundKey(); S-table (256 bytes) end for round = 1 step 1 to Nr 1 SubBytes(); ShiftRows(); MixColumns(); AddRoundKey(); end for // Last round SubBytes(); ShiftRows(); AddRoundKey(); ISE for Fast and Memory-Efficient AES 7
8 AES: T lookup (1 kb) AES_encrypt() T-table (1 kb) AddRoundKey(); for round = 1 step 1 to Nr 1 SubBytes(); ShiftRows(); MixColumns(); AddRoundKey(); end for // Last round SubBytes(); ShiftRows(); AddRoundKey(); S-table (256 bytes) end ISE for Fast and Memory-Efficient AES 8
9 AES: T lookup (4 kb) AES_encrypt() 4 x T-table (4 kb) AddRoundKey(); for round = 1 step 1 to Nr 1 SubBytes(); ShiftRows(); MixColumns(); AddRoundKey(); end for // Last round SubBytes(); ShiftRows(); AddRoundKey(); S-table (256 bytes) end ISE for Fast and Memory-Efficient AES 9
10 AES: T lookup (8 kb) AES_encrypt() end AddRoundKey(); for round = 1 step 1 to Nr 1 SubBytes(); ShiftRows(); MixColumns(); AddRoundKey(); end for // Last round SubBytes(); ShiftRows(); AddRoundKey(); 4 x T-table (4 kb) 4 x T-table (4 kb) ISE for Fast and Memory-Efficient AES 10
11 Proposed Extension: sbox Instruction Perform SBOX lookup in a dedicated functional unit Operate on 8-bit subwords Source and destination byte are selectable -> ShiftRows included for free Useable for SubBytes, InvSubBytes and key expansion ISE for Fast and Memory-Efficient AES 11
12 Our Implementation (SPARC v8) Instruction format: sbox %rs1, imm, %rd Transform a byte from rs1 and write the result to a byte in rd Operation (SubBytes, InvSubBytes), source byte and destination byte controlled by immediate data (imm) rs1 imm destination byte source byte AES [Inv]SBOX encr/decr rd rd ISE for Fast and Memory-Efficient AES 12
13 SubBytes & ShiftRows (single column of State) Plain SPARCv8 ISA Use of Proposed AES Extenstion srl %c0, 24, %tmp0 ldub [%sbox + %tmp0], %tmp1 sll %tmp1, 24, %c0' srl %c1, 16, %tmp0 and %tmp0, 0xff, %tmp0 ldub [%sbox + %tmp0], %tmp1 sll %tmp1, 16, %tmp1 or %tmp1, %c0', %c0' srl %c2, 8, %tmp0 and %tmp0, 0xff, %tmp0 ldub [%sbox + %tmp0], %tmp1 sll %tmp1, 8, %tmp1 or %tmp1, %c0', %c0' sbox %c0, 0x100, %c0'! s0,0 -> s0,0' sbox %c1, 0x111, %c0'! s1,1 -> s1,0' sbox %c2, 0x122, %c0'! s2,2 -> s2,0' sbox %c3, 0x133, %c0'! s3,3 -> s3,0' and %c3, 0xff, %tmp0 ldub [%sbox + %tmp0], %tmp1 or %tmp1, %c0', %c0' ISE for Fast and Memory-Efficient AES 13
14 Advantages of sbox Instruction Small, easy to implement Flexible: Allows numerous implementation variants Removes dependency on memory/cache performance; minimizes cache pollution Minimize memory usage -> less energy intensive instructions Improve performance/throughput -> minimize energy / block ISE for Fast and Memory-Efficient AES 14
15 Influence of Cache Size on Performance Frequent lookups require data fetches from main memory If lookup tables are too big for the cache, values have to be overwritten and require re-loading Omission of lookup tables minimizes dependency on cache size ISE for Fast and Memory-Efficient AES 15
16 Cache Influence: AES Encryption Clock cycles T lookup 1 KB T lookup 4 KB T lookup 8 KB Only SBOX lookup SBOX instruction KB 2 KB 4 KB 8 KB 16 KB Cache size ISE for Fast and Memory-Efficient AES 16
17 Cache Influence: AES Decryption Clock cycles T lookup 1 KB T lookup 4 KB T lookup 8 KB Only SBOX lookup SBOX instruction 0 1 KB 2 KB 4 KB 8 KB 16 KB Cache size ISE for Fast and Memory-Efficient AES 17
18 Influence of Cache Size on Performance For cache sizes < 4 kb, performance of T-lookup implementations degrades significantly For AES encryption, T-lookup with 16 kb cache has same performance as AES with our proposed extension For AES decryption, performance of T-lookup becomes better at cache sizes > 4 kb Performance of AES with our extension is practically independent of cache size ISE for Fast and Memory-Efficient AES 18
19 Practical Results SPARC V8-compatible LEON-2 embedded processor implemented on FPGA board (Virtex-2) 1 additional instruction (integrated AES SBOX functional unit) Area overhead for extension < 1 kgate Critical path: Not extended in our implementation (clock speed stays > 40 Mhz on Virtex-2 FPGA) Cycle counter for exact timing measurements Two different AES-128 implementations: Columnoriented, Row-oriented ISE for Fast and Memory-Efficient AES 19
20 Precomputed Key Schedule AES-128 with precomputed key schedule (Execution time in clock cycles) Key expansion Encryption Decryption C with plain ISA 738 1,636 1,954 C with sbox instruction 646 1,139 1,554 Speedup 30.3 % 20.4 % ISE for Fast and Memory-Efficient AES 20
21 On-the-fly Key Expansion AES-128 with on-the-fly key expansion (Execution time in clock cycles) Encryption Decryption* C with plain ISA 2,254 2,433 C with sbox instruction 1,576 1,866 Speedup 30.0 % 23.3 % *Last roundkey supplied by caller ISE for Fast and Memory-Efficient AES 21
22 Supplement: High-Performance AES (on-the-fly) Whole AES-128 in assembly Full use of all available registers Use of ECC extensions to accelerate AES MixColumns transformation as proposed in [17] (Execution time in clock cycles) Encryption Decryption* C with plain ISA 2,254 2,433 ASM with sbox instruction & ECC ext Speedup 72.8 % 63.7 % *Last roundkey supplied by caller [17] S. Tillich and J. Großschädl. Accelerating AES using Instruction Set Extensions for Elliptic Curve Cryptography. In Computational Science and Its Applications ICCSA 2005, vol of LNCS, pp Springer Verlag ISE for Fast and Memory-Efficient AES 22
23 Comparision with Related Work AES-128 (Execution time in clock cycles) Encryption Decryption* LEON-2 with AES co-processor [14] 1,494 N/A LEON-2 with AES co-processor [X1] 704 N/A Tensilica Xtensa with auto-ise [13] 1,400 1,400 Our work (C with sbox instruction) 1,139 1,554 Our work (ASM with sbox instruction & ECC ext.) *Last roundkey supplied by caller (where applicable) [14] P. Schaumont, K. Sakiyama, A. Hodjat, and I. Verbauwhede. Embedded software integration for coarse-grain reconfigurable systems. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), pp IEEE Computer Society Press, [X1] A. Hodjat and I. Verbauwhede. Interfacing a High Speed Crypto Accelerator to an Embedded CPU. In Proceedings of the 38th Asilomar Conference on Signals, Systems, and Computers, pp , November [13] S. Ravi, A. Raghunathan, N. Potlapally, and M. Sankaradass. System design methodologies for a wireless security processing platform. In Proceedings of the 39th Design Automation Conference (DAC 2002), pp ACM Press, ISE for Fast and Memory-Efficient AES 23
24 Practical Results (cont'd) Performance gain for AES-192 and AES- 256 should be similar to AES-128 Code size shrinks up to 42.9% (lookup tables omitted, more compact code) Cache-based timing side-channel attacks become impossible ISE for Fast and Memory-Efficient AES 24
25 Conclusions Very cheap, easy-to-integrate extensions for 32-bit processors Performance gains up to 30% for AES encryption by using the sbox instruction AES performance becomes largely independent of memory and cache performance Compares well to co-processor and auto- ISE approaches ISE for Fast and Memory-Efficient AES 25
Speeding Up AES By Extending a 32 bit Processor Instruction Set
Speeding Up AES By Extending a bit Processor Instruction Set Guido Marco Bertoni ST Microelectronics Agrate Briaznza, Italy bertoni@st.com Luca Breveglieri Politecnico di Milano Milano, Italy breveglieri@elet.polimi.it
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors Stefan Tillich and Johann Großschädl Graz University of Technology, Institute for Applied Information Processing and Communications,
Interfacing a High Speed Crypto Accelerator to an Embedded CPU
Interfacing a High Speed Crypto Accelerator to an Embedded CPU Alireza Hodjat ahodjat @ee.ucla.edu Electrical Engineering Department University of California, Los Angeles Ingrid Verbauwhede ingrid @ee.ucla.edu
Advanced Encryption Standard and Modes of Operation. Foundations of Cryptography - AES pp. 1 / 50
Advanced Encryption Standard and Modes of Operation Foundations of Cryptography - AES pp. 1 / 50 AES Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm AES has been originally requested
Implementation of Full -Parallelism AES Encryption and Decryption
Implementation of Full -Parallelism AES Encryption and Decryption M.Anto Merline M.E-Commuication Systems, ECE Department K.Ramakrishnan College of Engineering-Samayapuram, Trichy. Abstract-Advanced Encryption
The Encryption Standards
The Encryption Standards Appendix F Version 1.0 Computer Security: Art and Science, 2 nd Edition Slide F-1 Outline Data Encryption Standard Algorithm Advanced Encryption Standard Background mathematics
Optimized AES Algorithm Using FeedBack Architecture Chintan Raval 1, Maitrey Patel 2, Bhargav Tarpara 3 1, 2,
Optimized AES Algorithm Using FeedBack Architecture Chintan Raval 1, Maitrey Patel 2, Bhargav Tarpara 3 1, 2, Pursuing M.Tech., VLSI, U.V.Patel college of Engineering and Technology, Kherva, Mehsana, India
Sharing Resources Between AES and the SHA-3 Second Round Candidates Fugue and Grøstl
Sharing Resources Between AES and the SHA-3 Second Round Candidates Fugue and Grøstl Kimmo Järvinen Department of Information and Computer Science Aalto University, School of Science and Technology Espoo,
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm N. M. Kosaraju, M. Varanasi & Saraju P. Mohanty VLSI Design and CAD Laboratory Homepage: http://www.vdcl.cse.unt.edu
Cryptography and Network Security
Cryptography and Network Security Spring 2012 http://users.abo.fi/ipetre/crypto/ Lecture 6: Advanced Encryption Standard (AES) Ion Petre Department of IT, Åbo Akademi University 1 Origin of AES 1999: NIST
Efficient Hardware Design and Implementation of AES Cryptosystem
Efficient Hardware Design and Implementation of AES Cryptosystem PRAVIN B. GHEWARI 1 MRS. JAYMALA K. PATIL 1 AMIT B. CHOUGULE 2 1 Department of Electronics & Telecommunication 2 Department of Computer
Area Optimization in Masked Advanced Encryption Standard
IOSR Journal of Engineering (IOSRJEN) ISSN (e): 2250-3021, ISSN (p): 2278-8719 Vol. 04, Issue 06 (June. 2014), V1 PP 25-29 www.iosrjen.org Area Optimization in Masked Advanced Encryption Standard R.Vijayabhasker,
128 Bit ECB-AES Crypto Core Design using Rijndeal Algorithm for Secure Communication
IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 03, 2014 ISSN (online): 2321-0613 128 Bit ECB-AES Crypto Core Design using Rijndeal Algorithm for Secure Communication
FPGA CAN BE IMPLEMENTED BY USING ADVANCED ENCRYPTION STANDARD ALGORITHM
FPGA CAN BE IMPLEMENTED BY USING ADVANCED ENCRYPTION STANDARD ALGORITHM P. Aatheeswaran 1, Dr.R.Suresh Babu 2 PG Scholar, Department of ECE, Jaya Engineering College, Chennai, Tamilnadu, India 1 Associate
Fully Pipelined High Throughput Cost Effective FPGA Based Implementation of AES Algorithm
Fully Pipelined High Throughput Cost Effective FPGA Based Implementation of AES Algorithm Athira Das A J 1, Ajith Kumar B P 2 1 Student, Dept. of Electronics and Communication, Karavali Institute of Technology,
High-Performance Cryptography in Software
High-Performance Cryptography in Software Peter Schwabe Research Center for Information Technology Innovation Academia Sinica September 3, 2012 ECRYPT Summer School: Challenges in Security Engineering
AES Advanced Encryption Standard
AES Advanced Encryption Standard AES is iterated block cipher that supports block sizes of 128-bits and key sizes of 128, 192, and 256 bits. The AES finalist candidate algorithms were MARS, RC6, Rijndael,
AES as A Stream Cipher
> AES as A Stream Cipher < AES as A Stream Cipher Bin ZHOU, Kris Gaj, Department of ECE, George Mason University Abstract This paper presents implementation of advanced encryption standard (AES) as a stream
PARALLEL ANALYSIS OF THE RIJNDAEL BLOCK CIPHER
PARALLEL ANALYSIS OF THE RIJNDAEL BLOCK CIPHER Philip Brisk, Adam Kaplan, Majid Sarrafzadeh Computer Science Department, University of California Los Angeles 3532C Boelter Hall, Los Angeles, CA 90095-1596
Cryptography and Network Security. Sixth Edition by William Stallings
Cryptography and Network Security Sixth Edition by William Stallings Chapter 5 Advanced Encryption Standard Advance Encryption Standard Topics Origin of AES Basic AES Inside Algorithm Final Notes Origins
FAULT DETECTION IN THE ADVANCED ENCRYPTION STANDARD. G. Bertoni, L. Breveglieri, I. Koren and V. Piuri
FAULT DETECTION IN THE ADVANCED ENCRYPTION STANDARD G. Bertoni, L. Breveglieri, I. Koren and V. Piuri Abstract. The AES (Advanced Encryption Standard) is an emerging private-key cryptographic system. Performance
Using Error Detection Codes to detect fault attacks on Symmetric Key Ciphers
Using Error Detection Codes to detect fault attacks on Symmetric Key Ciphers Israel Koren Department of Electrical and Computer Engineering Univ. of Massachusetts, Amherst, MA collaborating with Luca Breveglieri,
AES ALGORITHM FOR ENCRYPTION
Volume 02 - Issue 05 May 2016 PP. 63-68 AES ALGORITHM FOR ENCRYPTION Radhika D.Bajaj M.Tech VLSI G.H. Raisoni Institute of Engineering And Technology For Women, Nagpur. Dr. U.M. Gokhale Electronics and
Chapter 7 Advanced Encryption Standard (AES) 7.1
Chapter 7 Advanced Encryption Standard (AES) 7.1 Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Chapter 7 Objectives To review a short history of AES To define
Dr. Jinyuan (Stella) Sun Dept. of Electrical Engineering and Computer Science University of Tennessee Fall 2010
CS 494/594 Computer and Network Security Dr. Jinyuan (Stella) Sun Dept. of Electrical Engineering and Computer Science University of Tennessee Fall 2010 1 Secret Key Cryptography Block cipher DES 3DES
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, and Nader Bagherzadeh Department of Electrical Engineering and Computer Science
Implementation and Comparative Analysis of AES as a Stream Cipher
Implementation and Comparative Analysis of AES as a Stream Cipher Bin ZHOU, Yingning Peng Dept. of Electronic Engineering, Tsinghua University, Beijing, China, 100084 e-mail: zhoubin06@mails.tsinghua.edu.cn
FPGA BASED CRYPTOGRAPHY FOR INTERNET SECURITY
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 10, October 2015,
Hardware/Software Co-Design of Elliptic Curve Cryptography on an 8051 Microcontroller
Hardware/Software Co-Design of Elliptic Curve Cryptography on an 8051 Microcontroller Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, and Johannes
Implementing AES : performance and security challenges
Implementing AES 2000-2010: performance and security challenges Emilia Käsper Katholieke Universiteit Leuven SPEED-CC Berlin, October 2009 Emilia Käsper Implementing AES 2000-2010 1/ 31 1 The AES Performance
Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures
Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures 1 Suresh Sharma, 2 T S B Sudarshan 1 Student, Computer Science & Engineering, IIT, Khragpur 2 Assistant
A Novel Approach of Area Optimized and pipelined FPGA Implementation of AES Encryption and Decryption
International Journal of Scientific and Research Publications, Volume 3, Issue 9, September 2013 1 A Novel Approach of Area Optimized and pipelined FPGA Implementation of AES Encryption and Decryption
Comparison of Performance of AES Standards Based Upon Encryption /Decryption Time and Throughput
Comparison of Performance of AES Standards Based Upon Encryption /Decryption Time and Throughput Miss Navraj Khatri Mr Jagtar Singh Mr Rajeev dhanda NCCE,Israna,K.U Senior lecturer,ncce,israna,k.u Assistant
FPGA Can be Implemented Using Advanced Encryption Standard Algorithm
FPGA Can be Implemented Using Advanced Encryption Standard Algorithm Shahin Shafei Young Researchers and Elite Club, Mahabad Branch, Islamic Azad University, Mahabad, Iran Email:Shahin_shafei@yahoo.com
FPGA Based Design of AES with Masked S-Box for Enhanced Security
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 3 Issue 5ǁ May 2014 ǁ PP.01-07 FPGA Based Design of AES with Masked S-Box for Enhanced Security
CPSC 467b: Cryptography and Computer Security
CPSC 467b: Cryptography and Computer Security Instructor: Michael Fischer Lecture by Ewa Syta Lecture 5 January 23, 2012 CPSC 467b, Lecture 5 1/35 Advanced Encryption Standard AES Alternatives CPSC 467b,
Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES
Hardware-ocused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES Akashi Satoh and Sumio Morioka Tokyo Research Laboratory IBM Japan Ltd. Contents Compact and High-Speed
Countermeasures against EM Analysis
Countermeasures against EM Analysis Paolo Maistri 1, SebastienTiran 2, Amine Dehbaoui 3, Philippe Maurine 2, Jean-Max Dutertre 4 (1) (2) (3) (4) Context Side channel analysis is a major threat against
CPSC 467b: Cryptography and Computer Security
CPSC 467b: Cryptography and Computer Security Instructor: Michael Fischer Lecture by Ewa Syta Lecture 5a January 29, 2013 CPSC 467b, Lecture 5a 1/37 Advanced Encryption Standard AES Alternatives CPSC 467b,
A Structure-Independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard
A Structure-Independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard Presented by: Mehran Mozaffari Kermani Department of Electrical and Computer Engineering
Hardware Implementation of Cryptosystem by AES Algorithm Using FPGA
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 6.017 IJCSMC,
Low area implementation of AES ECB on FPGA
Total AddRoundkey_3 MixCollumns AddRoundkey_ ShiftRows SubBytes 1 Low area implementation of AES ECB on FPGA Abstract This project aimed to create a low area implementation of the Rajindael cipher (AES)
ECE596C: Handout #7. Analysis of DES and the AES Standard. Electrical and Computer Engineering, University of Arizona, Loukas Lazos
ECE596C: Handout #7 Analysis of DES and the AES Standard Electrical and Computer Engineering, University of Arizona, Loukas Lazos Abstract. In this lecture we analyze the security properties of DES and
Implementation of the block cipher Rijndael using Altera FPGA
Regular paper Implementation of the block cipher Rijndael using Altera FPGA Piotr Mroczkowski Abstract A short description of the block cipher Rijndael is presented. Hardware implementation by means of
CPSC 467: Cryptography and Computer Security
CPSC 467: Cryptography and Computer Security Instructor: Michael Fischer Lecture by Ewa Syta Lecture 7 September 23, 2015 CPSC 467, Lecture 7 1/1 Advanced Encryption Standard AES Alternatives CPSC 467,
On-Line Self-Test of AES Hardware Implementations
On-Line Self-Test of AES Hardware Implementations G. Di Natale, M. L. Flottes, B. Rouzeyre Laboratoire d Informatique, de Robotique et de Microélectronique de Montpellier Université Montpellier II / CNRS
Application Specific Scalable Architectures for Advanced Encryption Standard (AES) Algorithm
Application Specific Scalable Architectures for Advanced Encryption Standard (AES) Algorithm S.S.Naqvi, S.R.Naqvi, S.A Khan, S.A. Malik Department of Electrical Engineering COMSATS Institute of Information
Run-time reconfiguration for automatic hardware/software partitioning
Run-time reconfiguration for automatic hardware/software partitioning Tom Davidson ELIS department, Ghent University Sint-pietersnieuwstraat, 41 9000, Ghent, Belgium Email: tom.davidson@ugent.be Karel
Introduction to Cryptology. Lecture 17
Introduction to Cryptology Lecture 17 Announcements HW7 due Thursday 4/7 Looking ahead: Practical constructions of CRHF Start Number Theory background Agenda Last time SPN (6.2) This time Feistel Networks
in a 4 4 matrix of bytes. Every round except for the last consists of 4 transformations: 1. ByteSubstitution - a single non-linear transformation is a
Cryptanalysis of Reduced Variants of Rijndael Eli Biham Λ Nathan Keller y Abstract Rijndael was submitted to the AES selection process, and was later selected as one of the five finalists from which one
Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA
IJCSNS International Journal of Computer Science and Network Security, VOL.9 No.9, September 2009 59 Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA Muhammad
Chap. 3. Symmetric Key Crypto (Block Ciphers)
Introduction to SW Security Chap. 3. Symmetric Key Crypto (Block Ciphers) Spring, 28 Cho, Seong-je ( 조성제 ) sjcho at dankook.ac.kr Many slides taken from Textbook (Its site), and Web sites Textbook M. T.
Block Ciphers. Secure Software Systems
1 Block Ciphers 2 Block Cipher Encryption function E C = E(k, P) Decryption function D P = D(k, C) Symmetric-key encryption Same key is used for both encryption and decryption Operates not bit-by-bit but
@ 2014 SEMAR GROUPS TECHNICAL SOCIETY.
www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.02, February-2014, Pages:0350-0355 Performance Improvement in Fault Detection Schemes for the Advanced Encryption Standard Using Composite
Secret Key Systems (block encoding) Encrypting a small block of text (say 64 bits) General considerations for cipher design:
Secret Key Systems (block encoding) Encrypting a small block of text (say 64 bits) General considerations for cipher design: Secret Key Systems (block encoding) Encrypting a small block of text (say 64
On the Simplicity of Converting Leakages from Multivariate to Univariate
On the Simplicity of Converting Leakages from Multivariate to Univariate 21. Aug. 2013, Oliver Mischke Embedded Security Group + Hardware Security Group Ruhr University Bochum, Germany Outline Definitions,
Cryptographic algorithm acceleration using CUDA enabled GPUs in typical system configurations
Rochester Institute of Technology RIT Scholar Works Theses Thesis/Dissertation Collections 8-1-2010 Cryptographic algorithm acceleration using CUDA enabled GPUs in typical system configurations Maksim
Encryption Details COMP620
Encryption Details COMP620 Encryption is a powerful defensive weapon for free people. It offers a technical guarantee of privacy, regardless of who is running the government It s hard to think of a more
A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
IJCSNS International Journal of Computer Science and Network Security, VOL.9 No.9, September 2009 305 A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box Muhammad
3 Symmetric Key Cryptography 3.1 Block Ciphers Symmetric key strength analysis Electronic Code Book Mode (ECB) Cipher Block Chaining Mode (CBC) Some
3 Symmetric Key Cryptography 3.1 Block Ciphers Symmetric key strength analysis Electronic Code Book Mode (ECB) Cipher Block Chaining Mode (CBC) Some popular block ciphers Triple DES Advanced Encryption
IMPLEMENTATION OF EFFICIENT AND HIGH SPEED AES ALGORITHM FOR SECURED DATA TRANSMISSION
International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol.2, Issue 3 (Spl.) Sep 2012 22-29 TJPRC Pvt. Ltd., IMPLEMENTATION
Content of this part
UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Introduction to Cryptography ECE 597XX/697XX Part 4 The Advanced Encryption Standard (AES) Israel Koren ECE597/697 Koren Part.4.1
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
Journal of Universal Computer Science, vol. 13, no. 3 (2007), 349-362 submitted: 30/11/06, accepted: 16/2/07, appeared: 28/3/07 J.UCS The Use of Runtime Reconfiguration on FPGA Circuits to Increase the
An Implementation of the AES cipher using HLS
2013 III Brazilian Symposium on Computing Systems Engineering An Implementation of the AES cipher using HLS Rodrigo Schmitt Meurer Tiago Rogério Mück Antônio Augusto Fröhlich Software/Hardware Integration
Compact Dual Block AES core on FPGA for CCM Protocol
Compact Dual Block AES core on FPGA for CCM Protocol João Carlos Resende and Ricardo Chaves Instituto Superior Técnico, Universidade de Lisboa / INESC-ID Rua Alves Redol 9, 1000-029 Lisbon, Portugal joaocresende@tecnico.ulisboa.pt,
Design and Implementation of Rijndael Encryption Algorithm Based on FPGA
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 2, Issue. 9, September 2013,
Piret and Quisquater s DFA on AES Revisited
Piret and Quisquater s DFA on AES Revisited Christophe Giraud 1 and Adrian Thillard 1,2 1 Oberthur Technologies, 4, allée du doyen Georges Brus, 33 600 Pessac, France. c.giraud@oberthur.com 2 Université
VLSI Implementation of Advanced Encryption Standard using Rijndael Algorithm
VLSI Implementation of Advanced Encryption Standard using Rijndael Algorithm Aditya Agarwal Assistant Professor, Electronics and Communication Engineering SRM University, NCR Campus, Ghaziabad, India ABSTRACT
Few Other Cryptanalytic Techniques
Few Other Cryptanalytic Techniques Debdeep Mukhopadhyay Assistant Professor Department of Computer Science and Engineering Indian Institute of Technology Kharagpur INDIA -721302 Objectives Boomerang Attack
CHAPTER 1 INTRODUCTION
1 CHAPTER 1 INTRODUCTION 1.1 Advance Encryption Standard (AES) Rijndael algorithm is symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256
Security against Timing Analysis Attack
International Journal of Electrical and Computer Engineering (IJECE) Vol. 5, No. 4, August 2015, pp. 759~764 ISSN: 2088-8708 759 Security against Timing Analysis Attack Deevi Radha Rani 1, S. Venkateswarlu
OPTICAL networks require secure data transmission at
366 IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 4, APRIL 2006 Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors Alireza Hodjat, Student Member, IEEE, and Ingrid Verbauwhede,
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor
Minimum Area Cost for a 30 to 70 Gbits/s AE Processor Alireza Hodjat and Ingrid Verbauwhede Electrical Engineering Department University of California, Los Angeles {ahodjat, ingrid} @ ee.ucla.edu Abstract
Design of S-box and IN V S -box using Composite Field Arithmetic for AES Algorithm
Design of S-box and IN V S -box using Composite Field Arithmetic for AES Algorithm Sushma D K Department of Electronics and Communication The Oxford College of Engineering Bangalore, India Dr. Manju Devi
Compact Dual Block AES core on FPGA for CCM Protocol
Compact Dual Block AES core on FPGA for CCM Protocol João Carlos C. Resende Ricardo Chaves 1 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves Outline Introduction &
Implementation of Stronger S-Box for Advanced Encryption Standard
The International Journal Of Engineering And Science (IJES) Volume 3 Issue 12 December - 2014 Pages 39-47 ISSN (e): 2319 1813 ISSN (p): 2319 1805 Implementation of Stronger S-Box for Advanced Encryption
Encryption and Decryption by AES algorithm using FPGA
Encryption and Decryption by AES algorithm using FPGA Sayali S. Kshirsagar Department of Electronics SPPU MITAOE, Alandi(D), Pune, India sayali.kshirsagar17@gmail.com Savita Pawar Department of Electronics
Symmetric encryption algorithm image for wireless multimedia sensor network
Symmetric encryption algorithm image for wireless multimedia sensor network Amina Msolli, Abdelhamid Helali, Laboratory of Micro-Optoelectronics and Nanostructures (LMON), Faculty of Sciences Monastir
Cryptography and Network Security
Cryptography and Network Security CRYPTOGRAPHY AND NETWORK SECURITY PRAKASH C. GUPTA Former Head Department of Information Technology Maharashtra Institute of Technology Pune Delhi-110092 2015 CRYPTOGRAPHY
Cryptographic Algorithms - AES
Areas for Discussion Cryptographic Algorithms - AES CNPA - Network Security Joseph Spring Department of Computer Science Advanced Encryption Standard 1 Motivation Contenders Finalists AES Design Feistel
Understanding Cryptography by Christof Paar and Jan Pelzl. Chapter 4 The Advanced Encryption Standard (AES) ver. October 28, 2009
Understanding Cryptography by Christof Paar and Jan Pelzl www.crypto-textbook.com Chapter 4 The Advanced Encryption Standard (AES) ver. October 28, 29 These slides were prepared by Daehyun Strobel, Christof
Performance Analysis of AES Algorithm on MPC Processor
Send Orders for Reprints to reprints@benthamscience.ae 2248 The Open Cybernetics & Systemics Journal, 2015, 9, 2248-2253 Performance Analysis of AES Algorithm on MPC Processor Open Access Gao Haifeng 1,
AES Implementation for RFID Tags: The Hardware and Software Approaches
AES Implementation for RFID Tags: The Hardware and Software Approaches Thanapol Hongsongkiat ew Product Research Department Silicon Craft Technology Co., Ltd. Bangkok, Thailand thanapol@sic.co.th Abstract
ASIC Performance Comparison for the ISO Standard Block Ciphers
ASIC Performance Comparison for the ISO Standard Block Ciphers Takeshi Sugawara 1, Naofumi Homma 1, Takafumi Aoki 1, and Akashi Satoh 2 1 Graduate School of Information Sciences, Tohoku University Aoba
Block Ciphers. Lucifer, DES, RC5, AES. CS 470 Introduction to Applied Cryptography. Ali Aydın Selçuk. CS470, A.A.Selçuk Block Ciphers 1
Block Ciphers Lucifer, DES, RC5, AES CS 470 Introduction to Applied Cryptography Ali Aydın Selçuk CS470, A.A.Selçuk Block Ciphers 1 ... Block Ciphers & S-P Networks Block Ciphers: Substitution ciphers
Advanced Encryption Standard and Modes of Operation
Advanced Encryption Standard and Mode of Operation G. Bertoni L. Breveglieri Foundation of Cryptography - AES pp. 1 / 50 AES Advanced Encryption Standard (AES) i a ymmetric cryptographic algorithm AES
Implementation of the AES-128 on Virtex-5 FPGAs
Implementation of the AES-128 on Virtex-5 FPGAs Philippe Bulens 1, François-Xavier Standaert 1, Jean-Jacques Quisquater 1, Pascal Pellegrin 2, Gaël Rouvroy 2 1 UCL Crypto Group, Place du Levant, 3, B-1348
FPGA Implementation of High Speed AES Algorithm for Improving The System Computing Speed
FPGA Implementation of High Speed AES Algorithm for Improving The System Computing Speed Vijaya Kumar. B.1 #1, T. Thammi Reddy.2 #2 #1. Dept of Electronics and Communication, G.P.R.Engineering College,
Efficient Software Implementation of AES on 32-Bit Platforms
Efficient Software Implementation of AES on 32-Bit Platforms Guido Bertoni 1, Luca Breveglieri 1, Pasqualina Fragneto 2, Marco Macchetti 3, and Stefano Marchesin 3 1 Politecnico di Milano, Milano, Italy
ryptograi "ГС for Tom St Denis, Elliptic Semiconductor Inc. Simon Johnson and Author of the LibTom Project
for ryptograi "ГС V6 е Tom St Denis, Elliptic Semiconductor Inc. and Author of the LibTom Project Simon Johnson Contents Preface Chapter 1 Introduction 1 Introduction 2 Threat Models 3 What Is Cryptography?
Designing a High-End Cryptographic Engine for Multi-Core Processor Arrays of FPGA
Designing a High-End Cryptographic Engine for Multi-Core Processor Arrays of FPGA S.Neelima Research Scholar, Department of Electronics and Communication Engineering, Avinashilingam institute for home
Week 5: Advanced Encryption Standard. Click
Week 5: Advanced Encryption Standard Click http://www.nist.gov/aes 1 History of AES Calendar 1997 : Call For AES Candidate Algorithms by NIST 128-bit Block cipher 128/192/256-bit keys Worldwide-royalty
Modified Advanced Encryption Standard For Text And Images
Computer Science Journal Volume 1, Issue 3, December 211 Modified Advanced Encryption Standard For Text And Images Sumira Hameed 1, Faisal Riaz 2,Riaz Moghal 3, Gulraiz Akhtar 4, Anil Ahmed 5, Abdul Ghafoor
Hybrid Key Encryption using Cryptography for Wireless Sensor Networks V-Algorithm
ISSN : 0974 5572 International Science Press Volume 9 Number 40 2016 Hybrid Key Encryption using Cryptography for Wireless Sensor Networks V-Algorithm D. Anitha a S. Aruna a Mathew a K. Mathew a and Devilal
Efficient Area and High Speed Advanced Encryption Standard Algorithm
International Journal of Emerging Engineering Research and Technology Volume 3, Issue 7, July 2015, PP 140-146 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) Efficient Area and High Speed Advanced Encryption
ENHANCED AES ALGORITHM FOR STRONG ENCRYPTION
ENHANCED AES ALGORITHM FOR STRONG ENCRYPTION V. Sumathy & C. Navaneethan Assistant Professor, Department of CSE, Kingston Engineering College, Vellore, Tamil Nadu, India ABSTRACT In this paper we present
Symmetric Key Cryptography
Symmetric Key Cryptography Michael Huth M.Huth@doc.ic.ac.uk www.doc.ic.ac.uk/~mrh/430/ Symmetric Key Cryptography (3.1) Introduction Also known as SECRET KEY, SINGLE KEY, PRIVATE KEY Sender and Receiver
Symmetric Key Encryption. Symmetric Key Encryption. Advanced Encryption Standard ( AES ) DES DES DES 08/01/2015. DES and 3-DES.
Symmetric Key Encryption Symmetric Key Encryption and 3- Tom Chothia Computer Security: Lecture 2 Padding Block cipher modes Advanced Encryption Standard ( AES ) AES is a state-of-the-art block cipher.
A New hybrid method in watermarking using DCT and AES
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 10, Issue 11 (November 2014), PP.64-69 A New hybrid method in watermarking using
Goals of Modern Cryptography
Goals of Modern Cryptography Providing information security: Data Privacy Data Integrity and Authenticity in various computational settings. Data Privacy M Alice Bob The goal is to ensure that the adversary