EXTERNAL BUSINTERFACE

Transcription

1 Fujitsu Microelectronics Europe Application Note FMEMCU-AN F²MC-16LX FAMILY 16-BIT MICROCONTROLLER ALL SERIES EXTERNAL BUSINTERFACE APPLICATION NOTE

2 Revision History Revision History Date Issue 25 th April 00 V1.0 (TKa/MEn) started 26 th April 00 V1.1 (TKa/MEn) Data line Timing with additional 22pF load capacitance added 10 th Mai 00 V1.2 (TKa) Some comments added at the end of chapter 1. Usage of upper address lines A16-A23 as IO ports explained. 27 th June 00 V1.3 (TKa) Some minor comments modified 18 th Sept. 00 V1.4 (MSt) Schematics improved 18 th Mai. 01 V1.5 (HWe) Software added 11 th April. 02 V1.6 (HWe) Bus-Access-table added 19 th March 03 V1.7 (HWe) new format, Type errors corrected 10 th June 2003 V1.8 (MSt) Ressource overview added 4 th June 2004 V1.9 (HWe) chapter 2.5, chapter 3.1 and Appendix D updated This document contains 30 pages. AN Fujitsu Microelectronics Europe GmbH

3 Warranty and Disclaimer Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for all products delivered free of charge (eg. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these products are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. 2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH s entire liability and the customer s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH. 3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated. 4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH s and its suppliers liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect Fujitsu Microelectronics Europe GmbH AN

4 Contents Contents REVISION HISTORY... 2 WARRANTY AND DISCLAIMER... 3 CONTENTS INTRODUCTION USING THE EXTERNAL BUS INTERFACE THE HARDWARE Introduction Connecting a SRAM directly to the external bus interface Schematic Bus-Timing Increasing Bus Load Using pull up resistors for the data lines Input High level Summary Connecting a SRAM to the external bus interface using a bus transceiver Schematic Using x16 organised SRAMs Schematic Using A16-A23 as general I/O ports USING THE EXTERNAL BUS INTERFACE THE SOFTWARE Introduction Bit Memory-Access Bit Memory-Access Bus-Access-Modes and Bus-Control-Signals: 8 Bit mode Bus-Access-Modes and Bus-Control-Signals: 16 Bit mode APPENDIX A: METHOD APPENDIX B: METHOD APPENDIX C: TIMING-DIAGRAMS APPENDIX D: RESOURCE OVERVIEW AN Fujitsu Microelectronics Europe GmbH

5 Chapter 1 Introduction 1 Introduction This application note reflects the external businterface that can be found on some devices of the Fujitsu 16LX-series, e.g. MB90495, MB90540 etc. Both hardware and software hints are given. Fujitsu Microelectronics Europe GmbH AN

6 Chapter 2 Using the external bus interface The Hardware 2 Using the external bus interface The Hardware In the following description, the external bus interface of Fujitsu microcontrollers will be discussed. It describes how external devices can be connected to the external bus interface (e.g. SRAM) and offers some suggestions. Timing calculations and estimations are made as well to have a better understanding of the design. The data measured in the following described tests are just example measurements, the measured timings are no data which are specified in the DS of the microcontroller series. 2.1 Introduction The external bus interface of the Fujitsu 16LX microcontroller series, is mostly a multiplexed 8/16 bit address/data bus. The address/data lines are AD00 to AD15, the upper 8Bit addresses are A16-A24. The used control signals of the external bus are RDY, WRL, WRH, HRQ, HAK, CLK, RD and ALE. During internal access cycles, the AD00 - AD15 are tristate, the control signals are switched to inactive state. The upper address lines A16-A23 are driven with the value used for the last external bus cycle (so it can happen, that if a higher address line is used for CE of the SRAM, the SRAM is still enabled after the last cycle). In general, all signals of the microcontroller are specified for CMOS level. This means that the minimum input high voltage is 0.8Vcc, the maximum input low voltage is 0.2Vcc. These restrictions must be considered if an external device is connected to the bus. The following description is based on the MB90F549, but the same situation exist for all current series of the 16LX family, with an external bus interface. 2.2 Connecting a SRAM directly to the external bus interface If e.g. an additional SRAM is connected to the external bus interface, the easiest method can be found in Figure 1.1 on the next page. An address latch is used to latch the address of the multiplexed address data bus. The latch used in this example is CD74ACT573 from Texas Instruments, which has a max. propagation delay time of 9.4ns. The output enable propagation delay time of the latch must not be considered, because the latch is always enabled (OE connected to GND). AN Fujitsu Microelectronics Europe GmbH

7 Chapter 2 Using the external bus interface The Hardware Schematic Figure 2-1: Example schematic how to connect directly a SRAM to the external bus interface Fujitsu Microelectronics Europe GmbH AN

8 Chapter 2 Using the external bus interface The Hardware Bus-Timing Figure 1.2 reflects the timing diagram of a read-cylcle of the MB90F549. This diagram shows the timing in case of 0 wait states. To guarantee that the CPU is reading correct data, it must be ensured that the data on the bus are valid after t RLDV ( (3*tcp/2-60) ns ) after RD becoming Low. Assuming that the internal operating frequency is 16MHz, t RLDV = 33,75ns. This means e.g., that during the time t RLDV, the data signals must rise up to the level 0.8Vcc, to read a logic 1 if a read cycle from the SRAM is performed. This time depends on t OE - output enable time of the SRAM data bus-, the capacitive load of the data bus and the output drive capability of the SRAM. Normally also SRAMs supply CMOS compatible output level, but high bus load will influence the rise time of the data signals and so the total access time. Additionally, most SRAM suppliers specify TTL output level only (e.g. 2.5V@1mA.). Some SRAM suppliers specify also higher output levels (e.g. 4.5V@ 100MA). So the datasheet of the corresponding device must be checked in detail. Additional wait states can be inserted here Figure 2-2: Bus Timing of external bus interface, 0 Wait states AN Fujitsu Microelectronics Europe GmbH

9 Chapter 2 Using the external bus interface The Hardware Increasing Bus Load Some test have been done using the DevKit16 starterkit to examine the behaviour of the bus interface in more detail.. On the DevKit16, SRAMs of HY628100A-LG55 are used, which are connected directly to the external bus interface. The maximum t OE of the SRAM is specified to 25ns On the starterkit, the final measured high level on all data lines AD00-AD15 was >4.8V. The following table shows the measured rise time (0.2Vcc to 0.8Vcc) of the different data lines and the total access time t RLDV.(RD = 0.2Vcc to data line = 0.8Vcc) for an SRAM read cycle. The table shows an average rise time of ns and a total average access time t RLDV of ns. In the DS of the MB90F549, less than is requested for read cycles with 0 wait states. The measured signal waveforms and access times have shown, that on the DevKit16 all signals meet the requirements, and no heavy bus load exist. For further detailed tests, the capacitive load of the data bus has been increased. The results are shown in the next table. It can be seen, that the rise time increases with increasing load capacitance. The table shows that an additional capacitive bus load of about 22pF increases the rise time for about 10ns. The total data access time is increased by about 15ns. data rise time (0.2Vcc to 0.8Vcc) in ns Total data access time t RLDV (RD=0.2Vcc to ADXX=0.8Vcc) in ns AD AD AD AD AD AD AD AD Average With 22pF capacitive Load: data rise time (0.2Vcc to 0.8Vcc) in ns Total data access time t RLDV (RD=0.2Vcc to ADXX=0.8Vcc) in ns AD AD AD Average With 48pF capacitive Load: data rise time (0.2Vcc to 0.8Vcc) in ns Total data access time t RLDV (RD=0.2Vcc to ADXX=0.8Vcc) in ns AD AD AD Average Table 1: Example measurements for signal rise time and data access time Fujitsu Microelectronics Europe GmbH AN

10 Chapter 2 Using the external bus interface The Hardware The maximum specified input capacitance of the Fujitsu microcontroller is 80pF, the typical value is specified to 10pF. Due to the specified maximum input capacitance of the microcontroller and regarding a worst case scenario, additional wait state for external bus accesses would be necessary. During the test no errors occurred using 0 wait states up to 22pF additional bus load. Errors occured with 48pF bus load, which could be removed by the insertion of one wait state. The following figures 1-3 to 1-6 show the rise time of AD03 and AD13 as an example of the measured timing. The figure 3, 4 show the normal timing. The figures 5, 6 show the timing with an additional bus load of 22pF. Figure 2-3: AD03 via RD timing diagram Figure 2-4: AD13 via RD timing diagram AN Fujitsu Microelectronics Europe GmbH

11 Chapter 2 Using the external bus interface The Hardware Figure 2-5: AD03 via RD timing diagram with additional capacitive load of 22pF Figure 2-6: AD13 via RD timing diagram with additional capacitive load of 22pF Fujitsu Microelectronics Europe GmbH AN

12 Chapter 2 Using the external bus interface The Hardware Using pull up resistors for the data lines The tests have also been performed using additional pull up resistors. But even 1K Ohm pull up resistors had no impact on the timing itself. The output level of the SRAM was always > 0.8Vcc even without pullups, as shown in the two figures for ASD03 and AD13 above. This may be due to the low output resistance of the SRAM output, so the pull up resistor did not influence the bus timing. So additional pull up resistors can only help to increase the output level, if the supplied output level of the SRAM is not sufficient (<0.8Vcc). The following calculations try to make an approximation of the pull up resistance which should be used. The specified output level of the used SRAM is Assuming a worst case, the pull up resistance must pull the output voltage level to at least 0.8Vcc starting from 2.4V. The time needed to rise from 2.4V to 0.8Vcc can be calculated by: V(t) = Vcc - [ (Vcc-Vi) e -t/rc ] V(t) - voltage at specified time Vi - voltage at t=0 (initial voltage) R - active resistance for capacitive load mechanism C capacitive load (bus load) Therefore the pull-up resistance can be calculated with Vi = 2.4V, V(t) = 0.8Vcc by: R = -t RC /[ C*ln{(Vcc - 0.8Vcc)/(Vcc -2.4V)} ]; t RC - rise time from 2.4V to 0.8Vcc Now t RC must be approximated. This can be done via the equation: t RLDV < t OE + t RC t OE is the SRAM output enable time, specified in the Datasheet of the SRAM, assumed, that this time is needed to achieve at least TTL level (2.4V). So R can be calculated with: R = -(t RLDV - t OE )/[ C*ln{(Vcc - 0.8Vcc)/(Vcc -2.4V)} ] To achieve a 0 Wait state data access, the following calculation is done. A t OE time of about 25ns is assumed, for C a value of 30pF was assumed. With t RLDV.= 33.75ns this leads to R = 279Ohm. This resistance would be necessary to have an output voltage of 0.8Vcc available 33.75ns after RD Low. With this low resistance it is critical to achieve an accurate low level, additionally this will increase the power consumption. So a higher pull up resistance must be used, with the disadvantage that the access time will increase. So additional wait states can not be avoided in that case. AN Fujitsu Microelectronics Europe GmbH

13 Chapter 2 Using the external bus interface The Hardware Input High level Additional tests have been performed to measure the input high level of some microcontrollers. The following table 1-2 and 1-3 shows the results of these example measurements. Nevertheless, the specified min. input high level is 0.8Vcc. Device 1 Device 2 Device 3 Device 4 Device 5 Average Input High level in V Input Low level in V Table 2: MB90F543 voltage = 5V, at about 25 degree Device 1 Device 2 Device 3 Device 4 Device 5 Average Input High level in V Input Low level in V Table 3: MB90F543 voltage = 5V, at about 60 degree The table shows that the measured average minimum input high level is about 3V, which would improve the above timing considerations. The DS specifies worst case 0.8Vcc! Summary The approximations above show that the capacitive load has an influence on the bus timing which is on the other side quite hard to estimate. Assuming worst case scenarios will lead to additional wait states, and/or using faster SRAMs. For calculations for the external bus interface at least the following electrical specifications of the used SRAM and microcontroller are important: Output Drive Level of the SRAM at a specified output current (must be >0.8*Vcc to meet the requirements of the microcontroller). The input leakage current of the controller and the additional input current of other devices connected to the external businterface must be considered for this calculation. Access time at a specified capacitive load (must be internal operating frequency of the microcontroller, to achieve 0 wait states). The input capacitance of all devices connected to the businterface must be considered for this calculation. The following data can be found in the corresponding SRAM Datasheets: M5M5256DP-45, -0.1mA@Vcc-0.5V, t OE =25ns@30pF M5M5256DP-70, -0.1mA@Vcc-0.5V, t OE =35ns@30pF K6R1016C1C-C20, -0.1mA@3.95V, t OE =9ns@30pF K6E0808C1E-C15, -0.1mA@3.95V, t OE =7ns@30pF Fujitsu Microelectronics Europe GmbH AN

14 Chapter 2 Using the external bus interface The Hardware Using e.g. M5M5256DP-45 will lead to 0 wait states, if the typical input capacity of the microcontroller is assumed of 10pF and the total capacitive bus load is below 30pF. For worst case calculations, the max. specified input capacity of 80pF of the microcontroller must be considered, so 0 wait states could not be used in this case, except the SRAM can be specified for higher busloads. In this case, the usage of faster SRAMs can help to workaraound this problem. Pull-up resistors for the data lines can bring the data lines to the requested input voltage of 0.8Vcc, but the value of the resistor must be approximated, but it is quite likely that in this case additional wait states are necessary. So for heavy bus loads, an additional external bus transceiver should be considered for fast access cycles, which will be discussed in the next chapter. 2.3 Connecting a SRAM to the external bus interface using a bus transceiver A further method to connect a SRAM to the external bus interface is to use an additional bus line transceivers. In the example shown in figure 1-7 a Texas Instruments driver SN74ACT16245 has been used. Also an address latch is necessary to latch the address of the multiplexed address/data bus. The pull-ups on the data bus are assigned to avoid floating inputs for the bus transceiver. The latch used in this example is CD74ACT573 from Texas instruments, which has a max. propagation delay time of 9.4ns. The output enable propagation delay time of the latch must not be considered, because the latch is always enabled (OE connected to GND). The valid time of the ALE signal must fit to the timing requirements of the latch. Example measurements have shown, that the ALE signal is active for about 25ns. Based on this and the read timing of the CPU, the following calculation can be done: t RLDV < t OE + t pd t RLDV - Read low to data valid time, after this time data must be valid at data inputs of the CPU t OE - output enable time of the SRAM t pd - propagation delay of SN74ACT16245 The propagation delay time of the SN74ACT16245 is about max 10ns. This results in a required t OE time for the used SRAM of about max. 23ns. The advantage of using a bus transceiver in ACT technology is that this device have CMOS output level and TTL compatible input levels. On the other hand an additional transceiver increases costs and needs more PCB layout space. Instead of ACT bus transceivers, also HCT logic can be used. But due to the higher propagation delay of this technology, additional wait states or faster SRAMs could be necessary. For worst case calculations, it can also happen that the line transceiver and the SRAM are driving the same data lines. This is because the transceiver needs some time to switch the data direction and the SRAM to disable its outputs, at the end of each read cycle. On the other hand, at the end of a cycle, new data can be present on the bus t cp /2-10ns after RD high. This time should be sufficient for the transceiver to switch the direction, so that the CPU and the transceiver are not driving the same bus. AN Fujitsu Microelectronics Europe GmbH

15 Chapter 2 Using the external bus interface The Hardware Schematic Figure 2-7 : Example schematic how to connect a SRAM to the external bus interface using bus drivers Fujitsu Microelectronics Europe GmbH AN

16 Chapter 2 Using the external bus interface The Hardware 2.4 Using x16 organised SRAMs If a x16 organised SRAM is used, like it is shown in figure 1-8, the timing calculations must consider additional propagation delays.. This delay is due to additional logic for the RD, WR control signals for the SRAM. Due to the bus transceiver and the additional logic, also the hold time of the data for the SRAM is influenced. In this example a Toshiba SRAM TC has been used. Due to the propagation delay of the AND logic gates, the required access time for 0 wait states read cycles, can be calculated by t RLDV < t OE + t RC + t pd gate, if no bus transceiver is used. If a bus transceiver is used, the read access time can be calculated with: t RLDV < t OE + t pd gate + t pd transceiver So the usage of x16 organised SRAMs lead to higher timing restrictions, especially if 0 wait states are required. So very fast SRAMs should be used to meet these requirements. The following schematic shows an example. AN Fujitsu Microelectronics Europe GmbH

17 Chapter 2 Using the external bus interface The Hardware Schematic Figure 2-8 : Example schematic how to connect a SRAM to the external bus interface using bus drivers Fujitsu Microelectronics Europe GmbH AN

18 Chapter 2 Using the external bus interface The Hardware 2.5 Using A16-A23 as general I/O ports The upper address lines A16-A23 of the external bus interface can also be used as general I/O ports. For that reason the register HACR is used. By default, if an external bus interface is used, after power-on reset, these lines are used as address lines! For that reason, care must be taken, if these port lines are intended to be used as I/O ports. After power-on, these port lines are used as address lines if the Internal ROM / External bus mode is used or if the External ROM / External bus mode is used. So the port lines will drive high or low level, which level cannot be predicted. If some of these port lines should be used as I/O ports, it must be considered that a high or low pulse is output on these lines, until the lines are set to I/O ports by initialising the HACR register. If e.g. a 4MHz crystal is used, and the HACR register is initialised right at the beginning in the startup code, this pulse will take about 1Ms High or Low. There is no workaround without using additional external logic around, because of the default setting of the HACR register after power-on. Take care that some 16LX microcontroller will not allow using the output of peripheral resources other than simple I/O for A16-A23, if BUSMODE INTROM_EXTBUS is selected. See also Appendix D. AN Fujitsu Microelectronics Europe GmbH

19 Chapter 3 Using the external bus interface The Software 3 Using the external bus interface The Software 3.1 Introduction The following description will investigate the external bus interface from the software side. Although there are many different methods to access to external addresses, some major methods will be discussed to see advantages and disadvantages. In addition, some tips will be given. Note: All examples are based on FFMC-16 Family Softune Workbench V30L26 and the MB90F540, but the same situation exists for all current series of the 16LX family, with an external bus interface. In order to use the external bus interface some settings has to be done within the start.asm - file: ;==================================================================== ; 4.8 External Bus Interface ;==================================================================== #set SINGLE_CHIP 0 ; all internal #set INTROM_EXTBUS 1 ; mask ROM, FLASH, or OTP ROM used #set EXTROM_EXTBUS 2 ; full external bus (INROM not used) #set BUSMODE INTROM_EXTBUS ; <<< set bus mode (see mode pins) ; If BUSMODE is "SINGLE_CHIP", ignore remaining bus settings. #set AUTOWAIT_IO 0 ; <<< 0..3 waitstates for IO area #set AUTOWAIT_LO 0 ; <<< 0..3 for lower external area #set AUTOWAIT_HI 0 ; <<< 0..3 for higher external area #set ADDR_PINS B' ; <<< select used address lines ; A23..A16 to be output. ; This is the value to be set in HACR-register. "1" means: pin used as ; IO-port. (B' => A23 not used, B' => A16 not used) #set BUS_SIGNAL B' ; <<< enable bus control signals ; +-- ignored ; +--- bus width lower memory (0:16, 1:8Bit) ; output WR signal(s) (1: enabled ) ; bus width upper memory (0:16, 1:8Bit) ; bus width ext IO area (0:16, 1:8Bit) ; enable HRQ input (1: enabled ) ; enable RDY input (1: enabled ) ; output CLK signal (1:enabled ) #set iarsr ((AUTOWAIT_IO<<6) ((AUTOWAIT_HI&3)<<4) (AUTOWAIT_LO&3)) #set MODEBYTE ( ((BUSMODE&3)<<6) ((~BUS_SIGNAL)&8) ) Please refer to the start.asm - file where more remarks are given! Fujitsu Microelectronics Europe GmbH AN

20 Chapter 3 Using the external bus interface The Software BUS_SIGNAL defines the value that will be written to register ECSR (sometimes also called EPCR). Contradictory to the MODEBYTE this value can be changed also at all time in the application program. The MODEBYTE is part of the Reset-Vector and will only be read once. When at least one external bus area will use 16Bit transfer, then bit 3 (S0) of the MODEBYTE should be set to indicate 16Bit-datatransfer. As mentioned before the actual bus-width will be controlled by ECSR (BUS_SIGNAL). Please refer always to chapter Memory Access Modes of the Hardware-Manual. ADDR_PINS allows defining which of the higher address-lines shall participate the businterface. In case that the corresponding bit is set to 0 the address-line is active, otherwise, in case of 1, the pin can be used as simple I/O-pin. Note: Some 16LX microcontroller might share some pins of the external bus-interface with peripheral resources other than simple I/O. In this case the resource output pins shared on the external bus cannot be used even if the corresponding pin is configured to be a outputport pin not participating the external bus. This concerns only to the output of resources shared with the external bus-interface. The input of resources shared with the external businterface will operate, if the corresponding pin is configured to be an input-port pin. See also Appendix D for detailed information. For the following examples the total 16MB-address-space (A23 16 = ) will be used with 16Bit Bus-width (MODEBYTE, S0 = 1). AN Fujitsu Microelectronics Europe GmbH

21 Chapter 3 Using the external bus interface The Software Bit Memory-Access The five following examples will show an 8-Bit Memory-Write. The value 0x81 will be written to Memory-Adress 0x10000 respective 0x Of course all examples will work the other way round for read-operation! In case of Memory-Address is Even: /WRH = 1 /WRL = 0 ALE = 0x10000 AD07..AD00 = 0x81 Odd : /WRH = 0 /WRL = 1 ALE = 0x10001 AD15..AD08 = 0x81 Please see Appendix C for timing charts. Method 1: far unsigned char *ptr_char = ( far unsigned char*)0x10000; *ptr_char = 0x81; Assembler-result: 719F0A01 MOVL A,010A 71A0 MOVL RL0,A 4281 MOV A,#81 6F3000 Method 2: CTRL_BASE = 0x10000; *(volatile unsigned char far*)(ctrl_base + 0x00L) = 0x81; Assembler-result: 4B MOVL A,# A0 MOVL RL0,A 4281 MOV A,#81 6F3000 Method 3: unsigned long adress_var; adress_var = 0x10000; *(volatile unsigned char far*)adress_var = 0x81; Assembler-result: 719F0A01 MOVL A,010A 71A0 MOVL RL0,A 4281 MOV A,#81 6F3000 Method 4: (see appendix A) and Method 5: far volatile extern char ext_var_char; // variable located method.reg.reg0 = 0x81; // in other c-module // e.g. method4.c Assembler-result: // (see appendix A and B) 4B MOVL A,# A0 MOVL RL0,A 4281 MOV A,#81 6F3000 Fujitsu Microelectronics Europe GmbH AN

22 Bit Memory-Access External Businterface Chapter 3 Using the external bus interface The Software The five following examples will show a 16-Bit Memory-Write. The value 0x8421 will be written to Memory-Adress 0x10000 respective 0x Of course all examples will work the other way round for read-operation! In case of Memory-Adress is Even (e.g. 0x10000) : /WRH = 0 /WRL = 0 ALE = 0x10001 AD15..AD00 = 0x8421; Odd (e.g. 0x10001) : two memory-accesses will be done: /WRH = 0 /WRL = 1 ALE = 0x10001 AD15..AD00 = 0x2184; /WRH = 1 /WRL = 0 ALE = 0x10002 AD15..AD00 = 0x2184; Method 1: far unsigned int *ptr_int = ( far unsigned int*)0x10000; *ptr_int = 0x8421; Assembler-result: 719F0601 MOVL A, A0 MOVL RL0,A 4A2184 MOVW A,#8421 6F3800 Method 2: CTRL_BASE = 0x10000; *(volatile unsigned int far*)(ctrl_base + 0x00L) = 0x8421; Assembler-result: 4B MOVL A,# A0 MOVL RL0,A 4A2184 MOVW A,#8421 6F3800 Method 3: unsigned long adress_var; adress_var = 0x10000; *(volatile unsigned int far*)adress_var = 0x8421; Assembler-result: 4B MOVL A,# BF0201 MOVL 0102,A 719F0201 MOVL A, A0 MOVL RL0,A 4A2184 MOVW A,#8421 6F3800 Method 4: (see appendix A) and Method 5 (see appendix B) far volatile extern int ext_var_int; // variable located ext_var_int = 0x81; // in other c-module // e.g. ext_bus_var.c Assembler-result: // (see appendix A and B) 4201 MOV A,#01 6F11 MOV ADB,A 06 ADB 73DF MOVW 0000,#8421 AN Fujitsu Microelectronics Europe GmbH

23 Chapter 3 Using the external bus interface The Software 3.4 Bus-Access-Modes and Bus-Control-Signals: 8 Bit mode Reflection of which Bus-Control-Signal is active while 8-Bit Bus-access: 8-Bit Mode: byte-access to even address Write: (volatile unsigned char far) even_address = 0xFF; Read: char_var = (volatile unsigned char far) even_address; Buscontroll (write): Buscontroll (read): ALE(even address), WRL(D0..D7=0xFF) ALE(even address), RD(D0..D7) 8-Bit Mode: byte-access to odd address Write: (volatile unsigned char far) odd_address = 0xFF; Read: char_var = (volatile unsigned char far) odd_address; Buscontroll (write): Buscontroll (read): ALE(odd address), WRL(D0..D7=0xFF) ALE(odd address), RD(D0..D7) 8-Bit Mode: word-access to even address Write: (volatile unsigned int far) even_address = 0x8421; Read: int_var = (volatile unsigned int far) even_address; Buscontroll (write): Buscontroll (read): 1. ALE(even address), WRL(D0..D7=0x21) 2. ALE(even address+1), WRL(D0..D7=0x84) 1. ALE(even address),rd(d0..d7) 2. ALE(even address+1), RD(D0..D7) 8-Bit Mode: word-access to odd address Write: (volatile unsigned int far) odd_address = 0x8421; Read: int_var = (volatile unsigned int far) odd_address; Buscontroll (write): Buscontroll (read): 1. ALE(odd address), WRL(D0..D7=0x21) 2. ALE(odd address+1), WRL(D0..D7=0x84) 1. ALE(odd address),rd(d0..d7) 2. ALE(odd address+1), RD(D0..D7) Fujitsu Microelectronics Europe GmbH AN

24 Chapter 3 Using the external bus interface The Software 3.5 Bus-Access-Modes and Bus-Control-Signals: 16 Bit mode Reflection of which Bus-Control-Signal is active while 16-Bit Bus-access: 16-Bit Mode: byte-access to even address Write: (volatile unsigned char far) even_address = 0xFF; Read: char_var = (volatile unsigned char far) even_address Buscontroll (write): Buscontroll (read): ALE(even address), WRL(D0..D7=0xFF) ALE(even address), RD(D0..D7) 16-Bit Mode: byte-access to odd address Write: (volatile unsigned char far) odd_address = 0xFF; Read: char_var = (volatile unsigned char far) odd_address Buscontroll (write): Buscontroll (read): ALE(odd address), WRH(D8..D15=0xFF) ALE(odd address), RD(D8..D15) 16-Bit Mode: word-access to even address Write: (volatile unsigned int far) even_address = 0x8421; Read: int_var = (volatile unsigned int far) even_address; Buscontroll (write): Buscontroll (read): ALE(even address), WRL(D0..D7=0x21), WRH(D8..D15=0x84) ALE(even address),rd(d0..d15) 16-Bit Mode: word-access to odd address Write: (volatile unsigned int far) odd_address = 0x8421; Read: int_var = (volatile unsigned int far) odd_address; Buscontroll (write): Buscontroll (read): 1. ALE(odd address), WRH(D8..D15=0x21) 2. ALE(odd address+1), WRL(D0..D7=0x84) 1. ALE(odd address),rd(d8..d15) 2. ALE(odd address+1), RD(D0..D7) AN Fujitsu Microelectronics Europe GmbH

25 Appendix A: Method 4 Appendix A: Method 4 When using method 4 some hints have to be known to define the external variables. Possibly, those variables will be registers of an external device. Therefore, they have to be located at a fixed address. For example: method4.c // Definition of external Memory-Addresses, // e.g. to define some registers of an external device // starting at adress 0x10000 #pragma section FAR_DATA=Ext_Bus_data,attr=DATA,locate=0x10000 far volatile union { unsigned int word0; struct { char reg0; char reg1; }reg; }method4; // Address-offset +0 => e.g. 0x10000 // Address-offset +0 => e.g. 0x10000 // Address-offset +1 => e.g. 0x10001 far volatile unsigned int method4_word1; // Address 0x10002 far volatile unsigned char method4_reg4; // Address 0x10004 far volatile unsigned char method4_reg5; // Address 0x10005 far volatile unsigned int method4_word3; // Address 0x10006 Hint Generally the Compiler will make an optimisation with a reorder of variables of different sizes. In order to prevent this reordering an individual Setup option has to added: - varorder NORMAL (right mouse-click at filename within sourcewindow, Setup-Tool-Option) Caution: Unfortunately all project-setup-settings will not be valid anymore for modules with individual settings like it was done in this module. This disadvantage will be covered by defining the external-registers as a struct/unionexpression like shown in Appendix B. Fujitsu Microelectronics Europe GmbH AN

26 Appendix B: Method 5 Appendix B: Method 5 Method 5 uses the possibility to define a structure that will not be reordered by the compiler. For example: method5.h struct ext_device0_struct { union { unsigned int word; struct { char reg0; char reg1; }reg; }word0; // Address-offset +0 => e.g. 0x20000 // Address-offset +0 => e.g. 0x20000 // Address-offset +1 => e.g. 0x20001 union { unsigned int word; struct { char reg2; char reg3; }reg; }word1; // Address-offset +2 => e.g. 0x20002 // Address-offset +2 => e.g. 0x20002 // Address-offset +3 => e.g. 0x20003 unsigned int word3; // Address-offset +4 => e.g. 0x20004 unsigned char reg4; // Address-offset +5 => e.g. 0x20005 unsigned char reg5; // Address-offset +6 => e.g. 0x20006 }; For example: method5.c // Definition of external Memory-Addresses, // e.g. to define some registers of an external device // starting at adress 0x20000 #pragma section FAR_DATA=Ext_Bus_data2,attr=DATA,locate=0x20000 #include "method5.h" far volatile struct ext_device0_struct method5; AN Fujitsu Microelectronics Europe GmbH

27 Appendix C: Timing-Diagrams Appendix C: Timing-Diagrams external 16-Bit Bus Mode: 8-Bit Write-access Address Addres Addres undefined 8 Bit-data 8-Bit Memory-Write-Access to even address, e.g. 0x10000 Address Address Address 8 Bit-data undefined 8-Bit Memory-Write-Access to odd address, e.g. 0x10001 Fujitsu Microelectronics Europe GmbH AN

28 Appendix C: Timing-Diagrams external 16-Bit Bus Mode: 16-Bit Write-access Address Address Address Data (Highbyte) Data (Lowbyte) 16-Bit Memory-Write-Access to even address, e.g. 0x10000 Addres Address + 1 Address Data (Highbyte) Addr + 1 undefined Address undefined Addr + 1 Data (Lowbyte) 16-Bit Memory-Write-Access to odd address, e.g. 0x10001 Please refer to the Hardware-Manual chapter Memory-Access-Modes and to the Datasheet for more informations! AN Fujitsu Microelectronics Europe GmbH

29 Appendix D: Resource Overview Appendix D: Resource Overview Following table shows the resources using same pins as external Bus interface. Note: Address lines AD00-15 cannot be used at all neither for simple I/O- nor other peripheral resource functionality, when the bus-interface is in use. All other Pins (A16-23, ALE; RDX, WRLX/WRX, WRHX, HRQ, HAKX, RDY; CLK) and be used individually as simple I/O, when not be used as external Bus interface pin. Take care that some 16LX microcontroller will not allow using the output of peripheral resources other than simple I/O, in this case. The following tables will give an overview about the pin-sharing for some microcontrollers with external bus-interface: MB90340series, MB90860series MB90350series MB90495series MB90540series, MB90435series, MB90440series Note: Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is selected in start.asm. Fujitsu Microelectronics Europe GmbH AN

30 Appendix D: Resource Overview MB90340series, MB90860series: Pin No. External Bus Interface Ressource QFP LQFP I/O Port Resource pin AD00 P01 INT AD01 P02 INT AD02 P03 INT AD03 P04 INT AD04 P05 INT AD05 P06 INT AD06 P07 INT AD07 P08 INT AD08 P10 TIN AD09 P11 TOT1 (*) AD10 P12 SIN3; INT11R AD11 P13 SOT3 (*) AD12 P14 SCK3 (*) AD13 P15 SIN AD14 P16 SOT AD15 P17 SCK A16 P20 PPG9 (*) A17 P21 PPGB (*) A18 P22 PPBD (*) A19 P23 PPGF (*) 1 99 A20 P24 IN A21 P25 IN1 3 1 A22 P26 IN2 4 2 A23 P27 IN3 5 3 ALE P30 IN4 6 4 RDX P31 IN5 7 5 WRLX/WRX P32 RX2; INT10R 8 6 WRHX P33 TX2 9 7 HRQ P34 OUT4 (*) 10 8 HAKX P35 OUT5 (*) 11 9 RDY P36 OUT6 (*) CLK P37 OUT7 (*) Note: Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is selected in start.asm. AN Fujitsu Microelectronics Europe GmbH

31 Appendix D: Resource Overview MB90350 series: Pin No. External Bus Interface Ressource QFP (M09) I/O Port Resource pin 24 AD00 P01 INT8 25 AD01 P02 INT9 26 AD02 P03 INT10 27 AD03 P04 INT11 28 AD04 P05 INT12 29 AD05 P06 INT13 30 AD06 P07 INT14 31 AD07 P08 INT15 32 AD08 P10 TIN1 33 AD09 P11 TOT1 (*) 34 AD10 P12 SIN3; INT11R 35 AD11 P13 SOT3 (*) 36 AD12 P14 SCK3 (*) 37 AD13 P AD14 P AD15 P A16 P20 PPG9 (*) 41 A17 P21 PPGB (*) 42 A18 P22 PPBD (*) 43 A19 P23 PPGF (*) 44 A20 P24 IN0 51 A21 P25 IN1; ADTG -- A22 P A23 P ALE P30 IN4 55 RDX P31 IN5 56 WRLX/WRX P32 INT10R 57 WRHX P HRQ P34 OUT4 (*) 59 HAKX P35 OUT5 (*) 60 RDY P36 OUT6 (*) 61 CLK P37 OUT7 (*) Note: Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is selected in start.asm. Fujitsu Microelectronics Europe GmbH AN

32 Appendix D: Resource Overview MB90495 series: Pin No. External Bus Interface Ressource M06 M09 I/O Port Resource pin AD00 P AD01 P AD02 P AD03 P AD04 P AD05 P AD06 P AD07 P AD08 P10 IN AD09 P11 IN AD10 P12 IN AD11 P13 IN AD12 P14 PPG0 (*) AD13 P15 PPG1 (*) AD14 P16 PPG2 (*) AD15 P17 PPG3 (*) A16 P20 TIN A17 P21 TOUT0 (*) A18 P22 TIN A19 P23 TOUT1 (*) A20 P24 INT A21 P25 INT A22 P26 INT A23 P27 INT ALE P30 SOT0 (*) RDX P31 SCK0 (*) WRLX/WRX P WRHX P HRQ P HAKX P RDY P36 FRCK CLK P37 ADTG Note: Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is selected in start.asm. AN Fujitsu Microelectronics Europe GmbH

33 Appendix D: Resource Overview MB90540/545series, MB90435series, MB90440series: Pin No. External Bus Interface Ressource QFP LQFP I/O Port Resource pin AD00 P AD01 P AD02 P AD03 P AD04 P AD05 P AD06 P AD07 P AD08 P AD09 P AD10 P AD11 P AD12 P AD13 P AD14 P AD15 P A16 P A17 P A18 P A19 P A20 P A21 P A22 P A23 P ALE P RD P WRL/WR P WRH P HRQ P HAK P RDY P CLK P37 -- Fujitsu Microelectronics Europe GmbH AN