Advanced Computer Architecture Week 1: Introduction. ECE 154B Dmitri Strukov

Transcription

1 Advanced Computer Architecture Week 1: Introduction ECE 154B Dmitri Strukov 1

2 Outline Course information Trends (in technology, cost, performance) and issues 2

3 Course organization Class website : 7/home.htm Instructor office hours: by appointment Teacher Assistant: Ms. Nan Wu location: Trailer 699, Room 104 office hours: Wed 2:00 pm 3:00 pm, Fri 3:00 pm to 4:00 pm nanwu@umail.ucsb.edu 3

4 Textbook Computer Architecture: A Quantitative Approach, John L. Hennessy and David A. Patterson, Fifth Edition, Morgan Kaufmann, 2012, ISBN: Modern Processor Design: Fundamentals of Superscalar Processors, John Paul Shen and Mikko H. Lipasti, Waveland Press, 2013, ISBN: Digital Design and Computer Architecture, David Harris and Sarah Harris, 2 nd Ed.,

5 Class topics and tentative schedule Computer fundamentals (historical trends, performance metrics) 1 week Memory hierarchy design 2 weeks Instruction level parallelism (static and dynamic scheduling, speculation) 2 weeks Data level parallelism (vector, SIMD and GPUs) 2 weeks Thread level parallelism (shared memory architectures, synchronization and cache coherence) 2 weeks Warehouse scale computers (1 week) time permitted 5

6 Ultimate goal of the class To get intuition behind main techniques for improving performance To understand advanced microprocessors such as This is what you supposed to know! ARM Cortex A8 5 STAGE MIPS PIPELINE Intel Core i7 Tesla GPU 6

7 This is what we (hopefully) learn in this class! 7

8 Grading Projects: 100 % (done in pairs find lab partner ASAP) Verilog design of toy ARM microprocessor 4 projects total (2 weeks each starting this week) 5 stage pipelined MIPS Simple cache Branch predictor Multi issue + more advanced cache Assignment for this/next week: Review 5 stage MIPS Review Verilog (see Ch 4 from Harrison & Harrison and labs in ECE154A) ECE 154A or equivalent Course prerequisites 8

9 Trends in Computing Technology (with Brief Intro on Chip Economics) 9

10 A bit of history: ENIAC Electronic Numerical Integrator And Computer,

11 Historical Progress 1946: ENIAC electronic numerical integrator and computer Area: 140 m 2 floor area (30 tons) ~17,000 vacuum tubes, 7200 crystal diodes, 1500 relays, 70,000 resistors, 10,000 capacitors, 5M hand soldered joints Performance multiplication of two 10 digit numbers in 2 ms 2011: High Performance microprocessor Chip area mm 2 (for multi core) Board area 200 cm 2 ; improvement of 10 4 Performance: 64 bit multiply in few ns; improvement of

12 Crossroads: Conventional Wisdom in Computer Architecture 12 Credit: SBU, M. Dorojevets

13 Computer trends: Performance of a (single) processor The next series of question is centered around understanding this important graph 13

14 Question Q1: what is performance shown on the figure and how do we define it? 14

15 Question Q1: what is performance shown on the figure and how do we define it? A1a: Performance is typically related to how fast a certain task can be executed, i.e. reciprocal of execution time Performance = 1/ ExecTime Wall clock time: includes all system overheads CPU time: only computation time ExecTime = IC * CCT * <CPI> A1b: Many different metrics of performance today because of different applications of ups What kind of metrics? 15

16 Measuring Performance Typical performance metrics: Execution Time (or latency) Throughput Q2: How is throughput related to latency? Energy Q3: Is energy metric the same as power consumption one? Typical way to measure performance is to run benchmark (i.e. collection of representative for the tested hardware application) Kernels (e.g. matrix multiply) Toy programs (e.g. sorting) Synthetic benchmarks (e.g. Dhrystone) Benchmark suites (e.g. SPEC06fp, TPC C) Speedup of X relative to Y Execution time Y / Execution time X 16

17 Measuring Performance Typical performance metrics: Execution Time (or latency) Throughput Q2: How is throughput related to latency? A2: In general these are two different concepts. Throughput can be improved by providing more parallelism, but also be improved by reducing latency. For example, with no parallelism throughput is reversely proportional to latency Energy Q3: Is energy metric the same as power consumption one? A3: Power = energy / time, so in general, it is the same metric only when execution time is the same. Typical way to measure performance is to run benchmark (i.e. collection of representative for the tested hardware application) Kernels (e.g. matrix multiply) Toy programs (e.g. sorting) Synthetic benchmarks (e.g. Dhrystone) Benchmark suites (e.g. SPEC06fp, TPC C) Speedup of X relative to Y Execution time Y / Execution time X 17

18 Bandwidth vs. Latency Bandwidth or throughput Total work done in a given time 10,000 25,000X improvement for processors X improvement for memory and disks Latency or response time Time between start and completion of an event 30 80X improvement for processors 6 8X improvement for memory and disks 18

19 Computer trends: Performance of a (single) processor 19

20 Questions: Reasons behind performance improvement? Q4: Why it was improving originally (from ~1978 ~1984 on the figure)? 20

21 Questions: Reasons behind performance improvement? Q4: Why it was improving originally (from ~1978 ~1984 on the figure)? A4: Moore s law and the resulting increase in clock frequency 21

22 CMOS improvements: Transistor density: 4x / 3 yrs Die size: 10-25% / yr 22

23 Scaling with Feature Size (Dennard scaling) Let s 1) scale all the dimensions of the transistors and wires down by factor of s and 2) supply voltage V down by factor of s (together with threshold voltage Vth) Then Density: ~ s 2 Logic gate capacitance Cgate (traditionally dominating parasitics): ~ 1/s Saturation current I ON : ~ 1/s Gate delay Tgate: ~ CgateV/I ON = 1/s Clock frequency: s, i.e. it is reversely proportional to gate delay. Clock cycle time is typically around ten or more of logic gate delays See, e.g. page 124 of Digital Integrated Circuits by Jan Rabaey et al, 2 nd edition 23

24 Frequency Scaling with Feature Size If s is scaling factor, then density scale as s 2 Voltage V: 1/s Logic gate capacitance C (traditionally dominating): ~ 1/s Saturation current I ON : ~ 1/s Gate delay: ~ CV/I ON = 1/s 24

25 Computer trends: Performance of a (single) processor 25

26 Question: Q5: Reasons behind further performance improvement? What happened in 1986? 26

27 Question: Q5: Reasons behind further performance improvement? What happened in 1986? A5: CISC to RISC which enabled additional architectural improvements (see next slide) Review: Dimensions of ISA (1) Class of ISA: register memory vs load store (2) Memory addressing: byte addressable (3) Addressing modes (what are operands and addressing modes of memory): registers, immediate, displacement, indirect, indexed, absolute) (4) Types and sizes of operands: byte, half word, word (5) Operations: data transfer, arithmetic logical, control and fp (6) Control flow instructions: conditional branches, unconditional jumps, returns (7) Encoding an ISA: variable versus fixed length 27

28 Question: Reasons behind performance improvement? What happened in 1986? CISC to RISC ExecTime = IC * CCT * <CPI> Q6: How are these terms affected by this move and in particular what terms in the performance equation are affected by pipelining? 28

29 Question: Reasons behind performance improvement? What happened in 1986? CISC to RISC ExecTime = IC * CCT * <CPI> Q6: How are these terms affected by this move and in particular what terms in the performance equation are affected by pipelining? A6: Design Inst count CPI CCT Single Cycle (SC) Multi cycle (MC) 1 N CPI > 1 (closer to N than 1) >1/N Multi cycle pipelined (MCP) 1 > 1 >1/N 29

30 Question: Pipelining improves performance (reduces instruction per cycle with respect to multi cycle processor without pipelining) by overlapping instructions One kind of instruction level parallelism (ILP) Q7: Problems with improving ILP? What are the problems in pipelines? 30

31 Question: Pipelining improves performance (reduces instruction per cycle with respect to multi cycle processor without pipelining) by overlapping instructions One kind of instruction level parallelism (ILP) Q7: Problems with improving ILP? What are the problems in pipelines? A7: Clock cycle is determined by slowest component» What is typically the slowest component? memory A7: Data and control hazards (pipeline stalls and flushes) Further improvement in ILP? A7: Limited parallelism in ILP 31

32 Memory Wall problem DRAM access (main memory) could take hundreds of cycles Memory hierarchy to rescue to alleviate the problem Will spend much time later in class reviewing advanced techniques for reducing effective access time to main memory 32

33 CPU high, Memory low ( Memory Wall ) Bandwidth and Latency Performance Milestones Processor: 286, 386, 486, Pentium, Pentium Pro, Pentium 4 (21x,2250x) Ethernet: 10Mb, 100Mb, 1000Mb, Mb/s (16x,1000x) Memory Module: 16bit plain DRAM, Page Mode DRAM, 32b, 64b, SDRAM, DDR SDRAM (4x,120x) Disk : 3600, 5400, 7200, 10000, RPM (8x, 143x) Log-log plot of bandwidth and latency milestones Bandwidth is much easier to improve why?

34 Question: Pipelining improve performance (instruction per cycle with respect to multi cycle processor with non pipelining, by overlapping instructions) One kind of instruction level parallelism (ILP) Q7: Problems with improving ILP? What are the problems in pipelines? A7: Clock cycle is determined by slowest component» What is typically the slowest component? memory A7: Data and control hazards (pipeline stalls and flushes) Further improvement in ILP? A7: Limited parallelism in ILP 34

35 ILP techniques

36 Summary of Trends in Technology (so far) Integrated circuit technology (slowing to a halt) Transistor density: 35%/year Die size: 10 20%/year Integration overall: 40 55%/year DRAM capacity: 25 40%/year (slowing to a halt) Flash capacity: 50 60%/year (some life with 3D NAND) 15 20X cheaper/bit than DRAM Magnetic disk technology: 40%/year (slowing) 15 25X cheaper/bit then Flash X cheaper/bit than DRAM 36

37 Computer Trends: Performance of a (Single) Processor The area of high performance chip has been always close to ~ cm^2, why? 37

38 Question: Q8: Why did the die size only grew by 10% / year? Performance of single processor could be improved by using more hardware (larger cache, more sophisticated branch prediction etc.) Drawing single crystal Si ingot from furnace. Then, slice into wafers and pattern it 8 MIPS64 R20K wafer (564 dies) 38

39 Trends in Cost Cost driven down by learning curve Yield DRAM: price closely tracks cost Microprocessors: price depends on volume 10% less for each doubling of volume 39

40 Integrated Circuits Costs IC cost = Die cost + Testing cost + Packaging cost Final test yield Die cost = Wafer cost Dies per Wafer * Die yield Final test yield: fraction of packaged dies which pass the final testing state Die yield: fraction of good dies on a wafer Defects per unit area = defects per square cm (2010) N = process complexity factor = (40 nm, 2010) 40

41 Die yield / wafer yield Die cost (arbitrary units) N = 11.5 Defects per unit area = Defects per unit area = Die area (cm^2) Answer to Q Die area (cm^2) 41

42 ASIC vs. up Total cost $ this is just an example of NRE cost. It may vary by much in in general total cost for up > that of ASIC 10 6 $1 M NRE (non recurrent engineering cost) Total cost = NRE/volume + IC cost IC cost = $100 IC cost = $ Q9: What is typically denser ASIC or up for the same task? What is typically more energy efficient and faster? What cost less to produce ASIC or up? up ASIC Volume 42

43 ASIC vs. up Total cost $ this is just an example of NRE cost. It may vary by much in in general total cost for up > that of ASIC 10 6 $1 M NRE (non recurrent engineering cost) Total cost = NRE/volume + IC cost IC cost = $100 IC cost = $ up ASIC Volume Q9: What is typically denser ASIC or up for the same task? ASIC What is typically more energy efficient and faster? ASIC What cost less to produce ASIC or up? depends on volume (see graph above) 43

44 Major Computing Platforms Application Specific Integrated Circuit Field Programmable Gate Array Microprocessor Density, speed Flexibility In this class, the focus is on the microprocessors only

45 The Twilight of Moore s Law: Economics 45

46 The Twilight of Moore s Law: Economics 46

47 Computer Trends: Performance of a (Single) Processor 47

48 Questions: Reasons behind performance improvement? Q10: What happened after > 2002 on the performance figure? 48

49 Questions: Reasons behind performance improvement? Q10: What happened after > 2002 on the performance figure? A10a: Power wall A10b: End of ILP Limits to pipelining Limits to superscalar 49

50 Power Consumption Problem: Get power in, get power out Thermal Design Power (TDP) Characterizes sustained power consumption, used as target for power supply and cooling system, Lower than peak power, higher than average power consumption Intel consumed ~ 2 W 3.3 GHz Intel Core i7 consumes 130 W Typical max temperatures: ~70 C Maximum power density for fan based cooling: 200W/cm^2 water based cooling: 1000W/cm^2 50

51 Water Cooling in a Google Data Center 51

52 Heating as a Function of Power Ambient temperature (Tlow) Fourier Law in 1D : Similar to Ohms law when replacing thermal conductance with electrical conductance heat source (total generated power) with current source temperature with voltage Heat flux (Q) Thermal conductance K Chip temperature (Thigh) Tlow K Q Vlow I 1/R Thigh Vhigh Thigh = Tlow + Q/K Vhigh = Vlow + IR Temperature is roughly (in 1D lumped model) linearly proportional to the Q or total dissipated power 52

53 Scaling with Feature Size (Dennard scaling) Let s 1) scale all the dimensions of the transistors and wires down by factor of s and 2) supply voltage V down by factor of s (together with threshold voltage Vth) Then Density: ~ s 2 Logic gate capacitance Cgate (traditionally dominating parasitics): ~ 1/s Saturation current I ON : ~ 1/s Gate delay Tgate: ~ CgateV/I ON = 1/s Clock frequency f : s, i.e. it is reversely proportional to gate delay. Clock cycle time is typically around ten or more of logic gate delays Power (dynamic component only): ~1/2 Ctotal*V 2 *f ~ 1 If chip area remain the same, power scales is the same as power density but (a) f scaled faster than s, and (b) end of Dennard scaling 53

54 Technique for Reducing Power Consumption Do nothing well Low power state for DRAM, disks Energy proportionality concept (don t consume energy when no work is done) very important for data center for which power is huge portion of running cost Power gating to reduce static component Dynamic Voltage Frequency Scaling Since saturation current I ON ~ V 2 f ~ 1/Tgate I ON /(CgateV)~ V Lowering voltage reduces the dynamic power consumption and energy per operation but decrease performance because of increased CCT Q11: Any benefits for multiprocessors? Overclocking, turning off cores Race to halt Thermal capacitance/ turbo mode 54

55 Technique for Reducing Power Consumption Do nothing well Low power state for DRAM, disks Energy proportionality concept (don t consume energy when no work is done) very important for data center for which power is huge portion of running cost Power gating to reduce static component Dynamic Voltage Frequency Scaling Since saturation current I ON ~ V 2 f ~ 1/Tgate I ON /(CgateV)~ V Lowering voltage reduces the dynamic power consumption and energy per operation but decrease performance because of increased CCT Q11: Any benefits for multiprocessors? A11: If task is easily parallelizable, then running this task on p processors in parallel at lower V (say V/p) and slower f (say f/p) can lead to the same execution time but much lower dynamic power CtotalV^2f ~ 1/p^3 (not accounting for static power) Overclocking, turning off cores Race to halt Thermal capacitance/ turbo mode 55

56 Static vs. dynamic power Static power Ron Dynamic power Roff Static power is permanent Dynamic power only when switching Leakage (static power) increases exponentially when lowering V! Cannot be neglected anymore Leakage power ~ V^2/Roff Roff/Ron ~ Exp(V)

57 The End of Voltage (Dennard) Scaling 57

58 Other Problems with Scaling: Transistors and Wires Feature size Minimum size of transistor or wire in x or y dimension 10 microns in 1971 to.032 microns in 2011 Transistor performance scales linearly Integration density scales quadratically Wire delay does not improve with feature size! There is always need in long wires Problem related to Rent Rule (number of pins versus number of gates) 58

59 59

60 Questions: Reasons behind performance improvement? Q10: What happened after > 2002 on the performance figure? A10a: Power wall A10b: End of ILP Limits to pipelining Limits to superscalar» Will discuss it in detail after covering advanced ILP topics 60

61 Computer Trends: Performance of a (Single) Processor 61

62 Summary of Trends in up 62

63 What is Next: Current Trends in Architecture Cannot continue to leverage Instruction Level parallelism (ILP) Single processor performance improvement ended in 2003 New ways of improving performance: Data level parallelism (DLP) Thread level parallelism (TLP) Request level parallelism (RLP) These require explicit restructuring of the application 63

64 Transition to Multicore 64

65 Dark Silicon Only some parts of a chip are active at a time Q12: Specialized cores make sense now in general purpose microprocessor Qualcomm Zeroth chip 65

66 New Applications Appear: Classes of Computers Now Personal Mobile Device (PMD) e.g. start phones, tablet computers Emphasis on energy efficiency and real time Desktop Computing Emphasis on price performance Servers Emphasis on availability, scalability, throughput Clusters / Warehouse Scale Computers Used for Software as a Service (SaaS) Emphasis on availability and price performance Sub class: Supercomputers, emphasis: floating point performance and fast internal networks Embedded Computers Emphasis: price 66

67 Motivation for Neuromorphic Computing Biology beats computers at many emerging tasks Image/audio/signal processing for Robotics Sensor networks Human brain simulations are very demanding 67

68 Artificial Neural Networks Complexity ~ neurons ~ synapses Connectivity ~ 1 : steps long rule: few to several hundred hertz; face recognition in ~100 ms 2 3 mm think, 2200 cm 2

69 Nvidia s Pascal STATE-OF-THE-ART HARDWARE FOR DEEP LEARNING: CUSTOM DIGITAL CIRCUITS 21 TFLOPS for deep learning performance Google s Tensor Processing Unit Movidius s fanthom 15 inferences 16 bit FP precision for <2W