Designing High-Performance MPI Libraries for Multi-/Many-core Era

Transcription

1 Designing High-Performance MPI Libraries for Multi-/Many-core Era Talk at IXPUG-Fall Conference (September 18) J. Hashmi, S. Chakraborty, M. Bayatpour, H. Subramoni and D. K Panda The Ohio State University {Hashmi.29,chakraborty.52,bayatpour.1,subramoni.1,panda.2}@osu.edu

2 IXPUG (Sept 18) 2 Increasing Usage of HPC, Big Data and Deep Learning HPC (MPI, RDMA, Lustre, etc.) Big Data (Hadoop, Spark, HBase, Memcached, etc.) Convergence of HPC, Big Data, and Deep Learning! Deep Learning (Caffe, TensorFlow, BigDL, etc.) Increasing Need to Run these applications on the Cloud!!

3 Parallel Programming Models Overview P1 P2 P3 P1 P2 P3 P1 P2 P3 Shared Memory Memory Memory Memory Logical shared memory Memory Memory Memory Shared Memory Model Distributed Memory Model Partitioned Global Address Space (PGAS) SHMEM, DSM MPI (Message Passing Interface) Global Arrays, UPC, Chapel, X1, CAF, Programming models provide abstract machine models Models can be mapped on different types of systems e.g. Distributed Shared Memory (DSM), MPI within a node, etc. PGAS models and Hybrid MPI+PGAS models are gradually receiving importance IXPUG (Sept 18) 3

4 Supporting Programming Models for Multi-Petaflop and Exaflop Systems: Challenges Application Kernels/Applications Point-to-point Communication Programming Models MPI, PGAS (UPC, Global Arrays, OpenSHMEM), CUDA, OpenMP, OpenACC, Cilk, Hadoop (MapReduce), Spark (RDD, DAG), etc. Networking Technologies (InfiniBand, 4/1GigE, Aries, and Omni-Path) Middleware Communication Library or Runtime for Programming Models Collective Communication Energy- Awareness Synchronization and Locks Multi-/Many-core Architectures I/O and File Systems Fault Tolerance Accelerators (GPU and FPGA) Co-Design Opportunities and Challenges across Various Layers Performance Scalability Resilience IXPUG (Sept 18) 4

5 Broad Challenges in Designing Runtimes for (MPI+X) at Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided) Scalable job start-up Low memory footprint Scalable Collective communication Offload Non-blocking Topology-aware Balancing intra-node and inter-node communication for next generation nodes ( cores) Multiple end-points per node Support for efficient multi-threading Integrated Support for Accelerators (GPGPUs and FPGAs) Fault-tolerance/resiliency QoS support for communication and I/O Support for Hybrid MPI+PGAS programming (MPI + OpenMP, MPI + UPC, MPI + OpenSHMEM, MPI+UPC++, CAF, ) Virtualization Energy-Awareness IXPUG (Sept 18) 5

6 IXPUG (Sept 18) 6 Additional Challenges for Designing Exascale Software Libraries Extreme Low Memory Footprint Memory per core continues to decrease D-L-A Framework Discover Overall network topology (fat-tree, 3D, ), Network topology for processes for a given job Node architecture, Health of network and node Learn Impact on performance and scalability Potential for failure Adapt Internal protocols and algorithms Process mapping Fault-tolerance solutions Low overhead techniques while delivering performance, scalability and fault-tolerance

7 Overview of the MVAPICH2 Project High Performance open-source MPI Library for InfiniBand, Omni-Path, Ethernet/iWARP, and RDMA over Converged Ethernet (RoCE) MVAPICH (MPI-1), MVAPICH2 (MPI-2.2 and MPI-3.1), Started in 21, First version available in 22 MVAPICH2-X (MPI + PGAS), Available since 211 Support for GPGPUs (MVAPICH2-GDR) and MIC (MVAPICH2-MIC), Available since 214 Support for Virtualization (MVAPICH2-Virt), Available since 215 Support for Energy-Awareness (MVAPICH2-EA), Available since 215 Support for InfiniBand Network Analysis and Monitoring (OSU INAM) since 215 Used by more than 2,95 organizations in 86 countries More than 494, (>.49 million) downloads from the OSU site directly Empowering many TOP5 clusters (Jul 18 ranking) 2 nd ranked 1,649,64-core cluster (Sunway TaihuLight) at NSC, Wuxi, China 12 th, 556,14 cores (Oakforest-PACS) in Japan 15 th, 367,24 cores (Stampede2) at TACC 24 th, 241,18-core (Pleiades) at NASA and many others Available with software stacks of many vendors and Linux Distros (RedHat and SuSE) Partner in the upcoming Frontera System Empowering Top5 systems for over a decade IXPUG (Sept 18) 7

8 Architecture of MVAPICH2 Software Family High Performance Parallel Programming Models Message Passing Interface (MPI) PGAS (UPC, OpenSHMEM, CAF, UPC++) Hybrid --- MPI + X (MPI + PGAS + OpenMP/Cilk) High Performance and Scalable Communication Runtime Diverse APIs and Mechanisms Point-topoint Primitives Collectives Algorithms Job Startup Energy- Awareness Remote Memory Access I/O and File Systems Fault Tolerance Virtualization Active Messages Introspection & Analysis Support for Modern Networking Technology (InfiniBand, iwarp, RoCE, Omni-Path) Support for Modern Multi-/Many-core Architectures (Intel-Xeon, OpenPower, Xeon-Phi, ARM, NVIDIA GPGPU) Transport Protocols RC XRC UD DC UMR ODP Modern Features SR- IOV Multi Rail Shared Memory Transport Mechanisms CMA IVSHMEM XPMEM Modern Features MCDRAM * NVLink * CAPI * * Upcoming IXPUG (Sept 18) 8

9 IXPUG (Sept 18) 9 MVAPICH2 Software Family Requirements MPI with IB, iwarp, Omni-Path, and RoCE Advanced MPI Features/Support, OSU INAM, PGAS and MPI+PGAS with IB, Omni-Path, and RoCE MPI with IB, RoCE & GPU and Support for Deep Learning HPC Cloud with MPI & IB Energy-aware MPI with IB, iwarp and RoCE MPI Energy Monitoring Tool InfiniBand Network Analysis and Monitoring Microbenchmarks for Measuring MPI and PGAS Performance Library MVAPICH2 MVAPICH2-X MVAPICH2-GDR MVAPICH2-Virt MVAPICH2-EA OEMT OSU INAM OMB

10 IXPUG (Sept 18) 1 Overview of A Few Challenges being Addressed by the MVAPICH2 Project for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication Scalable Start-up Optimized Collectives using SHArP and Multi-Leaders Optimized CMA-based Collectives Optimized XPMEM-based Collectives SALaR: Scalable and Adaptive Designs for Large Message Reduction Collectives Asynchronous Progress MPI-T support Integrated Support for GPGPUs and Deep Learning Optimized MVAPICH2 for OpenPower (with/ NVLink) and ARM Application Scalability and Best Practices High-Performance MPI Library for Cloud

11 One-way Latency: MPI over IB with MVAPICH2 Latency (us) 2 Small Message Latency Latency (us) Large Message Latency TrueScale-QDR ConnectX-3-FDR ConnectIB-DualFDR ConnectX-5-EDR Omni-Path Message Size (bytes) Message Size (bytes) TrueScale-QDR GHz Deca-core (Haswell) Intel PCI Gen3 with IB switch ConnectX-3-FDR GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch ConnectIB-Dual FDR GHz Deca-core (Haswell) Intel PCI Gen3 with IB switch ConnectX-5-EDR GHz Deca-core (Haswell) Intel PCI Gen3 with IB Switch Omni-Path GHz Deca-core (Haswell) Intel PCI Gen3 with Omni-Path switch IXPUG (Sept 18) 11

12 Bandwidth (MBytes/sec) Bandwidth: MPI over IB with MVAPICH2 14 Unidirectional Bandwidth 12, , , ,356 3,373 Bandwidth (MBytes/sec) Bidirectional Bandwidth TrueScale-QDR ConnectX-3-FDR ConnectIB-DualFDR ConnectX-5-EDR Omni-Path 24,136 22,564 21,983 12,161 6,228 Message Size (bytes) Message Size (bytes) TrueScale-QDR GHz Deca-core (Haswell) Intel PCI Gen3 with IB switch ConnectX-3-FDR GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch ConnectIB-Dual FDR GHz Deca-core (Haswell) Intel PCI Gen3 with IB switch ConnectX-5-EDR GHz Deca-core (Haswell) Intel PCI Gen3 IB switch Omni-Path GHz Deca-core (Haswell) Intel PCI Gen3 with Omni-Path switch IXPUG (Sept 18) 12

13 IXPUG (Sept 18) 13 Startup Performance on KNL + Omni-Path Time (seconds) TACC Stampede2 MPI_Init Hello World K 2K 4K 8K 16K 32K 64K 128K 18K 23K Number of Processes 57s 22s Time (seconds) Oakforest-PACS MPI_Init Hello World 21s 5.8s K 2K 4K 8K 16K 32K 64K Number of Processes MPI_Init takes 22 seconds on 231,936 processes on 3,624 KNL nodes (Stampede2 Full scale) At 64K processes, MPI_Init and Hello World takes 5.8s and 21s respectively (Oakforest- PACS) All numbers reported with 64 processes per node, MVAPICH2-2.3a Designs integrated with mpirun_rsh, available for srun (SLURM launcher) as well

14 Benefits of SHARP at Application Level Latency (seconds) Avg DDOT Allreduce time of HPCG.4 12% MVAPICH (4,28) (8,28) (16,28) (Number of Nodes, PPN) SHARP support available since MVAPICH2 2.3a Parameter Description Default MV2_ENABLE_SHARP=1 Enables SHARP-based collectives Disabled --enable-sharp Configure flag to enable SHARP Disabled Refer to Running Collectives with Hardware based SHARP support section of MVAPICH2 user guide for more information IXPUG (Sept 18) 14

15 MPI_Allreduce on KNL + Omni-Path (1,24 Processes) Latency (us) Message Size MVAPICH2 MVAPICH2-OPT IMPI OSU Micro Benchmark 64 PPN 8K 16K 32K 64K 128K 256K Message Size MVAPICH2 MVAPICH2-OPT IMPI For MPI_Allreduce latency with 32K bytes, MVAPICH2-OPT can reduce the latency by 2.4X 2.4X M. Bayatpour, S. Chakraborty, H. Subramoni, X. Lu, and D. K. Panda, Scalable Reduction Collectives with Data Partitioning-based Multi-Leader Design, SuperComputing '17. Available since MVAPICH2-X 2.3b IXPUG (Sept 18) 15

16 Latency (us) Optimized CMA-based Collectives for Large Messages KNL (2 Nodes, 128 Procs) 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M 2M 4M Message Size ~ 2.5x Better MVAPICH2-2.3a Intel MPI 217 OpenMPI 2.1. Tuned CMA KNL (4 Nodes, 256 Procs) MVAPICH2-2.3a Intel MPI 217 OpenMPI 2.1. Tuned CMA 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M 2M Message Size Performance of MPI_Gather on KNL nodes (64PPN) 1 1 KNL (8 Nodes, 512 Procs) 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M Message Size Significant improvement over existing implementation for Scatter/Gather with 1MB messages (up to 4x on KNL, 2x on Broadwell, 14x on OpenPower) New two-level algorithms for better scalability Improved performance for other collectives (Bcast, Allgather, and Alltoall) S. Chakraborty, H. Subramoni, and D. K. Panda, Contention Aware Kernel-Assisted MPI Collectives for Multi/Many-core Systems, IEEE Cluster 17, BEST Paper Finalist ~ 3.2x Better ~ 17x Better ~ 4x Better MVAPICH2-2.3a Intel MPI 217 OpenMPI 2.1. Tuned CMA Available since MVAPICH2-X 2.3b IXPUG (Sept 18) 16

17 Shared Address Space (XPMEM)-based Collectives Design 1 1 OSU_Allreduce (Broadwell 256 procs) MVAPICH2-2.3b IMPI-217v X MVAPICH2-X-2.3rc1 1 1 OSU_Reduce (Broadwell 256 procs) MVAPICH2-2.3b IMPI-217v1.132 MVAPICH2-2.3rc1 4X Latency (us) K 32K 64K 128K 256K 512K 1M 2M 4M Message Size Message Size Shared Address Space -based true zero-copy Reduction collective designs in MVAPICH2 Offloaded computation/communication to peers ranks in reduction collective operation Up to 4X improvement for 4MB Reduce and up to 1.8X improvement for 4M AllReduce J. Hashmi, S. Chakraborty, M. Bayatpour, H. Subramoni, and D. Panda, Designing Efficient Shared Address Space Reduction Available in MVAPICH2-X 2.3rc1 Collectives for Multi-/Many-cores, International Parallel & Distributed Processing Symposium (IPDPS '18), May 218. IXPUG (Sept 18) K 32K 64K 128K 256K 512K 1M 2M 4M

18 Application-Level Benefits of XPMEM-Based Collectives CNTK AlexNet Training (Broadwell, B.S=default, iteration=5, ppn=28) Execution Time (s) Intel MPI MVAPICH2 MVAPICH2-XPMEM 2% No. of Processes MiniAMR (Broadwell, ppn=16) Up to 2% benefits over IMPI for CNTK DNN training using AllReduce 9% Up to 27% benefits over IMPI and up to 15% improvement over MVAPICH2 for MiniAMR application kernel Execution Time (s) Intel MPI MVAPICH2 MVAPICH2-XPMEM 27% 15% No. of Processes IXPUG (Sept 18) 18

19 Impact of SALaR (Scalable Large Message Collectives) Designs on CNTK CPU-based training of AlexNet neural network using ImageNet ILSVRC212 dataset 46% SALaR designs show up to 46% improved performance over MVAPICH2 at 896 processes The proposed designs show good scalability with increasing system size CNTK Samples per Second (higher is better) M. Bayatpour, J. Hashmi, S. Chakraborty, P. Kousha, H. Subramoni, and D. K. Panda, SALaR: Scalable and Adaptive Designs for Large Message Reduction Collectives, IEEE Cluster 18 (BEST Paper, Architecture) Will be available in future MVAPICH2 Release IXPUG (Sept 18) 19

20 Benefits of A New Asynchronous Progress Design: SPEC MPI 28 IXPUG (Sept 18) 2 18% 38% 25% 1% 29% 13% Available in MVAPICH2-X 2.3rc1 384 Processes ( 6 Nodes : 64 PPN ) 384 Processes ( 8 Nodes : 48 PPN ) SPEC MPI : KNL + Omni-Path SPEC MPI : Skylake + Omni-Path Up to 25 % performance improvement for SPECMPI applications on 384 processes with KNL + Omni-Path Up to 38 % performance improvement for SPECMPI applications on 384 processes with Skylake + Omni-Path A. Ruhela, H. Subramoni, S. Chakraborty, M. Bayatpour, P. Kousha, and D. K. Panda, Efficient Asynchronous Communication Progress for MPI without Dedicated Resources, EuroMPI 18

21 IXPUG (Sept 18) 21 Benefits of the New Asynchronous Progress Design: P3DFFT 44% 33% 12% 6% ( 28 PPN ) Broadwell + InfiniBand Up to 44% performance improvement with the P3DFFT application with 448 processes

22 IXPUG (Sept 18) 22 Performance Engineering Applications using MVAPICH2 and TAU Enhance existing support for MPI_T in MVAPICH2 to expose a richer set of performance and control variables Get and display MPI Performance Variables (PVARs) made available by the runtime in TAU Control the runtime s behavior via MPI Control Variables (CVARs) Introduced support for new MPI_T based CVARs to MVAPICH2 MPIR_CVAR_MAX_INLINE_MSG_SZ, MPIR_CVAR_VBUF_POOL_SIZE, MPIR_CVAR_VBUF_SECONDARY_POOL_SIZE TAU enhanced with support for setting MPI_T CVARs in a non-interactive mode for uninstrumented applications S. Ramesh, A. Maheo, S. Shende, A. Malony, H. Subramoni, and D. K. Panda, MPI Performance Engineering with the MPI Tool Interface: the Integration of MVAPICH and TAU, EuroMPI/USA 17, Best Paper Finalist VBUF usage without CVAR based tuning as displayed by ParaProf VBUF usage with CVAR based tuning as displayed by ParaProf

23 IXPUG (Sept 18) 23 Overview of A Few Challenges being Addressed by the MVAPICH2 Project for Exascale Scalability for million to billion processors Integrated Support for GPGPUs and Deep Learning Optimized MVAPICH2 for OpenPower (with/ NVLink) and ARM Application Scalability and Best Practices High-Performance MPI Library for Cloud

24 GPU-Aware (CUDA-Aware) MPI Library: MVAPICH2-GPU Standard MPI interfaces used for unified data movement Takes advantage of Unified Virtual Addressing (>= CUDA 4.) Overlaps data movement from GPU with RDMA transfers At Sender: MPI_Send(s_devbuf, size, ); inside MVAPICH2 At Receiver: MPI_Recv(r_devbuf, size, ); High Performance and High Productivity IXPUG (Sept 18) 24

25 CUDA-Aware MPI: MVAPICH2-GDR Releases Support for MPI communication from NVIDIA GPU device memory High performance RDMA-based inter-node point-to-point communication (GPU-GPU, GPU-Host and Host-GPU) High performance intra-node point-to-point communication for multi-gpu adapters/node (GPU-GPU, GPU-Host and Host-GPU) Taking advantage of CUDA IPC (available since CUDA 4.1) in intra-node communication for multiple GPU adapters/node Optimized and tuned collectives for GPU device buffers MPI datatype support for point-to-point and collective communication from GPU device buffers Unified memory IXPUG (Sept 18) 25

26 IXPUG (Sept 18) 26 Latency (us) Bandwidth (MB/s) Optimized MVAPICH2-GDR Design GPU-GPU Inter-node Latency 1.88us 1x K 2K 4K 8K Message Size (Bytes) MV2-(NO-GDR) MV2-GDR 2.3rc1 GPU-GPU Inter-node Bandwidth K 2K 4K Message Size (Bytes) 9x Bandwidth (MB/s) GPU-GPU Inter-node Bi-Bandwidth K 2K 4K Message Size (Bytes) MV2-(NO-GDR) MV2-GDR-2.3rc1 11X MVAPICH2-GDR-2.3 Intel Haswell 3.1 GHz) node - 2 cores NVIDIA Volta V1 GPU Mellanox Connect-X4 EDR HCA CUDA 9. Mellanox OFED 4. with GPU-Direct-RDMA MV2-(NO-GDR) MV2-GDR-2.3rc1

27 Average Time Steps per second (TPS) Application-Level Evaluation (HOOMD-blue) K Particles Platform: Wilkes (Intel Ivy Bridge + NVIDIA Tesla K2c + Mellanox Connect-IB) HoomdBlue Version 1..5 GDRCOPY enabled: MV2_USE_CUDA=1 MV2_IBA_HCA=mlx5_ MV2_IBA_EAGER_THRESHOLD=32768 MV2_VBUF_TOTAL_SIZE=32768 MV2_USE_GPUDIRECT_LOOPBACK_LIMIT=32768 MV2_USE_GPUDIRECT_GDRCOPY=1 MV2_USE_GPUDIRECT_GDRCOPY_LIMIT= X Number of Processes Average Time Steps per second (TPS) K Particles MV2 MV2+GDR Number of Processes IXPUG (Sept 18) 27 2X

28 Application-Level Evaluation (Cosmo) and Weather Forecasting in Switzerland Normalized Execution Time Wilkes GPU Cluster Default Callback-based Event-based Number of GPUs CSCS GPU cluster Default Callback-based Event-based Normalized Execution Time Number of GPUs 2X improvement on 32 GPUs nodes 3% improvement on 96 GPU nodes (8 GPUs/node) Cosmo model: /tasks/operational/meteoswiss/ On-going collaboration with CSCS and MeteoSwiss (Switzerland) in co-designing MV2-GDR and Cosmo Application C. Chu, K. Hamidouche, A. Venkatesh, D. Banerjee, H. Subramoni, and D. K. Panda, Exploiting Maximal Overlap for Non-Contiguous Data Movement Processing on Modern GPU-enabled Systems, IPDPS 16 IXPUG (Sept 18) 28

29 Exploiting CUDA-Aware MPI for TensorFlow (Horovod) 35 MVAPICH2-GDR offers excellent performance via advanced designs for MPI_Allreduce. Up to 22% better performance on Wilkes2 cluster (16 GPUs) Images/sec (higher is better) MVAPICH2-GDR is up to 22% faster than MVAPICH No. of GPUs (4GPUs/node) MVAPICH2 MVAPICH2-GDR IXPUG (Sept 18) 29

30 MVAPICH2-GDR: Allreduce Comparison with Baidu and OpenMPI 16 GPUs (4 nodes) MVAPICH2-GDR vs. Baidu-Allreduce and OpenMPI 3. Latency (us) ~3X better Message Size (Bytes) MVAPICH2 BAIDU OPENMPI Latency (us) ~4X better 512K 1M 2M 4M Message Size (Bytes) MVAPICH2 BAIDU OPENMPI Latency (us) 6 ~1X better OpenMPI is ~5X slower 5 than Baidu 4 MV2 is ~2X better 3 than Baidu Message Size (Bytes) MVAPICH2 BAIDU OPENMPI *Available since MVAPICH2-GDR 2.3a IXPUG (Sept 18) 3

31 MVAPICH2-GDR vs. NCCL2 Allreduce Operation Optimized designs in MVAPICH2-GDR 2.3rc1 offer better/comparable performance for most cases MPI_Allreduce (MVAPICH2-GDR) vs. ncclallreduce (NCCL2) on 16 GPUs 1 1 Latency (us) 1 1 ~3X better Latency (us) ~1.2X better K 2K 4K 8K 16K 32K 64K Message Size (Bytes) Message Size (Bytes) MVAPICH2-GDR NCCL2 MVAPICH2-GDR NCCL2 Platform: Intel Xeon (Broadwell) nodes equipped with a dual-socket CPU, 1 K-8 GPUs, and EDR InfiniBand Inter-connect IXPUG (Sept 18) 31

32 OSU-Caffe: Proposed Co-Design Overview To address the limitations of Caffe and existing MPI runtimes, we propose the OSU-Caffe (S-Caffe) framework At the application (DL framework) level Develop a fine-grain workflow i.e. layer-wise communication instead of communicating the entire model At the runtime (MPI) level Develop support to perform reduction of very-large GPU buffers Perform reduction using GPU kernels OSU-Caffe is available from the HiDL project page IXPUG (Sept 18) 32

33 S-Caffe vs. Inspur-Caffe and Microsoft CNTK AlexNet: Notoriously hard to scale-out on multiple nodes due to comm. overhead! Large number of parameters ~ 64 Million (comm. buffer size = 256 MB) GoogLeNet is a popular DNN 13 million parameters (comm. buffer size = ~5 MB) Up to 14% improvement (Scale-up) S-Caffe delivers better or comparable performance with other multi-node capable DL frameworks Impact of HR IXPUG (Sept 18) 33

34 IXPUG (Sept 18) 34 Overview of A Few Challenges being Addressed by the MVAPICH2 Project for Exascale Scalability for million to billion processors Integrated Support for GPGPUs and Deep Learning Optimized MVAPICH2 for OpenPower (with/ NVLink) and ARM Application Scalability and Best Practices High-Performance MPI Library for Cloud

35 Intra-node Point-to-Point Performance on OpenPower Bandwidth (MB/s) Latency (us) Intra-Socket Small Message Latency.3us MVAPICH2-2.3 SpectrumMPI OpenMPI K 2K Intra-Socket Bandwidth MVAPICH2-2.3 SpectrumMPI OpenMPI K 32K 256K 2M Intra-Socket Large Message Latency Intra-Socket Bi-directional Bandwidth Platform: Two nodes of OpenPOWER (Power8-ppc64le) CPU using Mellanox EDR (MT4115) HCA IXPUG (Sept 18) 35 Latency (us) Bandwidth (MB/s) MVAPICH2-2.3 SpectrumMPI OpenMPI-3.. 4K 8K 16K 32K 64K 128K 256K 512K 1M 2M MVAPICH2-2.3 SpectrumMPI OpenMPI K 32K 256K 2M

36 Inter-node Point-to-Point Performance on OpenPower Latency (us) Small Message Latency MVAPICH2-2.3 SpectrumMPI OpenMPI-3.. Latency (us) Large Message Latency MVAPICH2-2.3 SpectrumMPI OpenMPI-3.. Bandwidth (MB/s) K 2K Bandwidth MVAPICH2-2.3 SpectrumMPI OpenMPI K 32K 256K 2M Bi-directional Bandwidth Platform: Two nodes of OpenPOWER (Power8-ppc64le) CPU using Mellanox EDR (MT4115) HCA IXPUG (Sept 18) 36 Bandwidth (MB/s) K 8K 16K 32K 64K 128K 256K 512K 1M 2M MVAPICH2-2.3 SpectrumMPI OpenMPI K 32K 256K 2M

37 Latency (us) MVAPICH2-GDR: Performance on OpenPOWER (NVLink + Pascal) INTRA-NODE LATENCY (SMALL) K 2K 4K 8K Message Size (Bytes) Latency (us) 4 2 INTRA-NODE LATENCY (LARGE) 16K 32K 64K 128K256K512K 1M 2M 4M Message Size (Bytes) Bandwidth (GB/sec) INTRA-NODE BANDWIDTH K 4K 16K 64K 256K 1M 4M Message Size (Bytes) INTRA-SOCKET(NVLINK) INTER-SOCKET INTRA-SOCKET(NVLINK) INTER-SOCKET INTRA-SOCKET(NVLINK) INTER-SOCKET Intra-node Latency: 13.8 us (without GPUDirectRDMA) Intra-node Bandwidth: 33.2 GB/sec (NVLINK) Latency (us) INTER-NODE LATENCY (SMALL) K 2K 4K 8K Latency (us) INTER-NODE LATENCY (LARGE) Message Size (Bytes) Message Size (Bytes) Message Size (Bytes) Inter-node Latency: 23 us (without GPUDirectRDMA) Inter-node Bandwidth: 6 GB/sec (FDR) Available since MVAPICH2-GDR 2.3a Platform: OpenPOWER (ppc64le) nodes equipped with a dual-socket CPU, 4 Pascal P1-SXM GPUs, and 4X-FDR InfiniBand Inter-connect IXPUG (Sept 18) 37 Bandwidth (GB/sec) INTER-NODE BANDWIDTH K 4K 16K 64K 256K 1M 4M

38 (Nodes=1, PPN=2) (Nodes=1, PPN=2) Scalable Host-based Collectives with CMA on OpenPOWER (Intra-node Reduce & AlltoAll) Reduce Latency (us) Latency (us) MVAPICH2-X-2.3rc1 SpectrumMPI OpenMPI K 2K 4K MVAPICH2-X-2.3rc1 SpectrumMPI OpenMPI X 3.2X 3.3X 5.2X Alltoall K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M Up to 5X and 3x performance improvement by MVAPICH2 for small and large messages respectively IXPUG (Sept 18) 38 Latency (us) Latency (us) MVAPICH2-X-2.3rc1 SpectrumMPI OpenMPI-3.. 8K 16K 32K 64K 128K 256K 512K 1M MVAPICH2-X-2.3rc1 SpectrumMPI OpenMPI X 3.2X 1.3X 1.2X (Nodes=1, PPN=2) (Nodes=1, PPN=2)

39 Optimized All-Reduce with XPMEM on OpenPOWER (Nodes=1, PPN=2) Latency (us) (Nodes=2, PPN=2) Latency (us) MVAPICH2-X-2.3rc1 Latency (us) 2 MVAPICH2-X-2.3rc1 SpectrumMPI-1.1. SpectrumMPI-1.1. OpenMPI OpenMPI-3.. 2X 16K 32K 64K 128K 256K 512K 1M 2M 16K 32K 64K 128K 256K 512K 1M 2M MVAPICH2-X-2.3rc1 3.3X 4 MVAPICH2-X-2.3rc1 SpectrumMPI SpectrumMPI-1.1. OpenMPI OpenMPI-3.. 3X 1 2X 16K 32K 64K 128K 256K 512K 1M 2M 16K 32K 64K 128K 256K 512K 1M 2M Message Size Message Size Optimized MPI All-Reduce Design in MVAPICH2 Up to 2X performance improvement over Spectrum MPI and 4X over OpenMPI for intra-node 4X Latency (us) 34% 48% 2X Optimized Runtime Parameters: MV2_CPU_BINDING_POLICY=hybrid MV2_HYBRID_BINDING_POLICY=bunch IXPUG (Sept 18) 39

40 Intra-node Point-to-point Performance on ARM Cortex-A72 Latency (us) Small Message Latency MVAPICH micro-second (1 bytes) Latency (us) Large Message Latency MVAPICH2-2.3 Bandwidth (MB/s) K 2K 4K 1 Bandwidth 8 MVAPICH Bidirectional Bandwidth 8K 16K 32K 64K 128K 256K 512K 1M 2M 4M 2 Bi-directional Bandwidth 15 MVAPICH Platform: ARM Cortex A72 (aarch64) MIPS processor with 64 cores dual-socket CPU. Each socket contains 32 cores. IXPUG (Sept 18) 4

41 IXPUG (Sept 18) 41 Overview of A Few Challenges being Addressed by the MVAPICH2 Project for Exascale Scalability for million to billion processors Integrated Support for GPGPUs and Deep Learning Optimized MVAPICH2 for OpenPower (with/ NVLink) and ARM Application Scalability and Best Practices High-Performance MPI Library for Cloud

42 SPEC MPI 27 Benchmarks: Broadwell + InfiniBand Execution Time in (s) Intel MPI MVAPICH2-X-2.3rc1 29% 5% -12% 1% 31% 11% MILC Leslie3D POP2 LAMMPS WRF2 LU MVAPICH2-X outperforms Intel MPI by up to 31% Configuration: 448 processes on 16 Intel E5-268v4 (Broadwell) nodes having 28 PPN and interconnected with 1Gbps Mellanox MT4115 EDR ConnectX-4 HCA IXPUG (Sept 18) 42

43 SPEC MPI 27 Benchmarks: KNL + Omni-Path Execution Time in (s) % 22% 1% 1% -2% Intel MVAPICH2-X-2.3rc1 15% MILC Leslie3D POP2 LAMMPS WRF2 GAP Lu MVAPICH2-X outperforms Intel MPI by up to 22% 4% Configuration : 384 processes on 8 nodes of Intel Xeon Phi 725(KNL) with 48 processes per node. KNL contains 68 cores on a single socket and interconnects with 1Gb/sec Intel Omni-Path network. IXPUG (Sept 18) 43

44 Application Scalability on Skylake and KNL (Stamepede2) Execution Time (s) Execution Time (s) MiniFE (13x13x13 ~ 91 GB) MVAPICH No. of Processes (Skylake: 48ppn) MVAPICH No. of Processes (KNL: 64ppn) NEURON (YuEtAl212) MVAPICH No. of Processes (Skylake: 48ppn) MVAPICH No. of Processes (KNL: 64ppn) Courtesy: Mahidhar Dong Ju (DJ) Choi@SDSC, and Samuel Khuvis@OSC ---- Testbed: TACC Stampede2 using MVAPICH2-2.3b Runtime parameters: MV2_SMPI_LENGTH_QUEUE= PSM2_MQ_RNDV_SHM_THRESH=128K PSM2_MQ_RNDV_HFI_THRESH=128K IXPUG (Sept 18) Cloverleaf (bm64) MPI+OpenMP, NUM_OMP_THREADS = 2 MVAPICH No. of Processes (Skylake: 48ppn) MVAPICH No. of Processes (KNL: 68ppn)

45 IXPUG (Sept 18) 45 Applications-Level Tuning: Compilation of Best Practices MPI runtime has many parameters Tuning a set of parameters can help you to extract higher performance Compiled a list of such contributions through the MVAPICH Website Initial list of applications Amber HoomDBlue HPCG Lulesh MILC Neuron SMG2 Cloverleaf SPEC (LAMMPS, POP2, TERA_TF, WRF2) Soliciting additional contributions, send your results to mvapich-help at cse.ohio-state.edu. We will link these results with credits to you.

46 IXPUG (Sept 18) 46 Overview of A Few Challenges being Addressed by the MVAPICH2 Project for Exascale Scalability for million to billion processors Integrated Support for GPGPUs and Deep Learning Optimized MVAPICH2 for OpenPower (with/ NVLink) and ARM Application Scalability and Best Practices High-Performance MPI Library for Cloud

47 Can HPC and Virtualization be Combined? Virtualization has many benefits Fault-tolerance Job migration Compaction Have not been very popular in HPC due to overhead associated with Virtualization New SR-IOV (Single Root IO Virtualization) support available with Mellanox InfiniBand adapters changes the field Enhanced MVAPICH2 support for SR-IOV MVAPICH2-Virt 2.2 supports: OpenStack, Docker, and singularity J. Zhang, X. Lu, J. Jose, R. Shi and D. K. Panda, Can Inter-VM Shmem Benefit MPI Applications on SR-IOV based Virtualized InfiniBand Clusters? EuroPar'14 J. Zhang, X. Lu, J. Jose, M. Li, R. Shi and D.K. Panda, High Performance MPI Library over SR-IOV enabled InfiniBand Clusters, HiPC 14 J. Zhang, X.Lu, M. Arnold and D. K. Panda, MVAPICH2 Over OpenStack with SR-IOV: an Efficient Approach to build HPC Clouds, CCGrid 15 IXPUG (Sept 18) 47

48 IXPUG (Sept 18) 48 Execution Time (ms) Application-Level Performance on Chameleon MV2-SR-IOV-Def MV2-SR-IOV-Opt MV2-Native 2% 5% 22,2 24,1 24,16 24,2 26,1 26,16 Problem Size (Scale, Edgefactor) 32 VMs, 6 Core/VM Graph5 Compared to Native, 2-5% overhead for Graph5 with 128 Procs Execution Time (s) % A Release for Azure Coming Soon 9.5% MV2-SR-IOV-Def MV2-SR-IOV-Opt MV2-Native milc leslie3d pop2 GAPgeofem zeusmp2 lu SPEC MPI27 Compared to Native, 1-9.5% overhead for SPEC MPI27 with 128 Procs

49 Application-Level Performance on Singularity with MVAPICH2 NPB Class D Graph5 Execution Time (s) Singularity Native 7% BFS Execution Time (ms) Singularity Native 6% 5 5 CG EP FT IS LU MG 512 Processes across 32 nodes 22,16 22,2 24,16 24,2 26,16 26,2 Problem Size (Scale, Edgefactor) Less than 7% and 6% overhead for NPB and Graph5, respectively J. Zhang, X.Lu and D. K. Panda, Is Singularity-based Container Technology Ready for Running MPI Applications on HPC Clouds?, UCC 17, Best Student Paper Award IXPUG (Sept 18) 49

50 Latency (us) Bandwidth (MB/s) MVAPICH2-GDR on Container with Negligible Overhead GPU-GPU Inter-node Latency K 4K 16K 64K 256K 1M 4M Message Size (Bytes) Docker GPU-GPU Inter-node Bandwidth Message Size (Bytes) Docker Native Native Bandwidth (MB/s) GPU-GPU Inter-node Bi-Bandwidth Message Size (Bytes) Docker Native MVAPICH2-GDR-2.3a Intel Haswell 3.1 GHz) node - 2 cores NVIDIA Volta V1 GPU Mellanox Connect-X4 EDR HCA CUDA 9. Mellanox OFED 4. with GPU-Direct-RDMA Works with NVIDIA HPC Container Maker IXPUG (Sept 18) 5

51 IXPUG (Sept 18) 51 MVAPICH2 Plans for Exascale Performance and Memory scalability toward 1M-1M cores Hybrid programming (MPI + OpenSHMEM, MPI + UPC, MPI + CAF ) MPI + Task* Enhanced Optimization for GPUs and FPGAs* Taking advantage of advanced features of Mellanox InfiniBand Tag Matching* Adapter Memory* Enhanced communication schemes for upcoming architectures NVLINK* CAPI* Extended topology-aware collectives Extended Energy-aware designs and Virtualization Support Extended Support for MPI Tools Interface (as in MPI 3.) Extended FT support Support for * features will be available in future MVAPICH2 Releases

52 IXPUG (Sept 18) 52 Funding Acknowledgments Funding Support by Equipment Support by

53 Personnel Acknowledgments Current Students (Graduate) A. Awan (Ph.D.) M. Bayatpour (Ph.D.) S. Chakraborthy (Ph.D.) C.-H. Chu (Ph.D.) S. Guganani (Ph.D.) Current Students (Undergraduate) J. Hashmi (Ph.D.) V. Gangal (B.S.) H. Javed (Ph.D.) M. Haupt (B.S.) P. Kousha (Ph.D.) N. Sarkauskas (B.S.) D. Shankar (Ph.D.) H. Shi (Ph.D.) Current Research Scientists X. Lu H. Subramoni Current Post-doc A. Ruhela Current Research Specialist J. Smith M. Arnold K. Manian Past Students A. Augustine (M.S.) P. Balaji (Ph.D.) R. Biswas (M.S.) S. Bhagvat (M.S.) A. Bhat (M.S.) D. Buntinas (Ph.D.) L. Chai (Ph.D.) B. Chandrasekharan (M.S.) N. Dandapanthula (M.S.) V. Dhanraj (M.S.) T. Gangadharappa (M.S.) W. Huang (Ph.D.) W. Jiang (M.S.) J. Jose (Ph.D.) S. Kini (M.S.) M. Koop (Ph.D.) K. Kulkarni (M.S.) R. Kumar (M.S.) S. Krishnamoorthy (M.S.) K. Kandalla (Ph.D.) M. Li (Ph.D.) P. Lai (M.S.) J. Liu (Ph.D.) M. Luo (Ph.D.) A. Mamidala (Ph.D.) G. Marsh (M.S.) V. Meshram (M.S.) A. Moody (M.S.) S. Naravula (Ph.D.) R. Noronha (Ph.D.) X. Ouyang (Ph.D.) S. Pai (M.S.) S. Potluri (Ph.D.) R. Rajachandrasekar (Ph.D.) G. Santhanaraman (Ph.D.) A. Singh (Ph.D.) J. Sridhar (M.S.) S. Sur (Ph.D.) H. Subramoni (Ph.D.) K. Vaidyanathan (Ph.D.) A. Vishnu (Ph.D.) J. Wu (Ph.D.) W. Yu (Ph.D.) J. Zhang (Ph.D.) Past Research Scientist K. Hamidouche S. Sur Past Programmers D. Bureddy J. Perkins K. Gopalakrishnan (M.S.) Past Post-Docs D. Banerjee J. Lin X. Besseron M. Luo H.-W. Jin E. Mancini S. Marcarelli J. Vienne H. Wang IXPUG (Sept 18) 53

54 IXPUG (Sept 18) 54 Thank You! Network-Based Computing Laboratory The High-Performance MPI/PGAS Project The High-Performance Big Data Project The High-Performance Deep Learning Project