The device can address up to 64KB of external program memory and up to 64KB of external RAM.

Transcription

1 CW9F52/CW9F54 Flash 05 MCU DESCRIPTION The CW9F52/54 series are -bit microcontroller with /6KB on-chip flash memory and 52B on-chip RAM. The devices use the 05 instruction set and are pin-for-pin compatible with industrystandard 05 microcontroller. The CW9F52/54 also provides the following features: 32 I/O lines, Watchdog timer, two data pointers, three 6-bit timer/counters, a seven vector four-level interrupt architecture, a full duplex serial port, and clock circuitry. In addition, the CW9F5x is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. The device can address up to 64KB of external program memory and up to 64KB of external RAM. FEATURES 05-Compatible Microcontroller Software, Development Tool, Pin-to-Pin Package Compatible Operation speed: 0 to 33MHz at 5V 256 Byte Internal RAM, 256 Byte on-chip XRAM Flexible Flash CW9F54 6KB; CW9F52 KB Support Address Range up to 64 KB of Program and Data Memory ISP available Three High-Current Port Pins (6 ma each) Three 6-bit Timers/Counters Full-Duplex, Enhanced UART Framing error detection Automatic address recognition Eight Interrupt Sources at 4 Priority Levels Programmable Watchdog Timer (WDT) Four -bit I/O Ports (32 I/O Pins) Double DPTR Register Low EMI Mode (Inhibit ALE) 2 Clocks or 6 clocks Per Cycle TTL- and CMOS-Compatible Logic Levels Low Power Modes Power-down Mode with Interrupt Wake-up Idle Mode Selectable Operation Clock Divide to /4, /6, /256, or /024th Temperature Ranges: -40 C to +5 C Packages Available 40-pin PDIP 44-pin QFP 44-pin LQFP, All Pb-free

2 APPLICATIONS Industrial control Building and security Small Appliances Consumer Product CW9F52/CW9F54 ORDERING INFORMATION Temperature Range Package Orderable Device Package Qty. DIP -40 C to +5 C QFP Pb-Free LQFP CW9F52-40P CW9F54-40P CW9F52-44Q CW9F54-44Q CW9F52-44L CW9F54-44L 9 Units/Tube 96 Units/Tray 60 Units/Tray PIN CONFIGURATION (T2) P.0 40 VDD (T2 EX) P P0.0 (AD0) P P0. (AD) P P0.2 (AD2) P P0.3 (AD3) P P0.4 (AD4) P P0.5 (AD5) P.7 33 P0.6 (AD6) RST (RXD) P3.0 (TXD) P pin PDIP P0.7 (AD7) EA ALE/PROG (INT0) P PSEN (INT) P P2.7 (A5) (T0) P P2.6 (A4) (T) P P2.5 (A3) (WR) P P2.4 (A2) (RD) P P2.3 (A) XTAL2 23 P2.2 (A0) XTAL 9 22 P2. (A9) VSS 20 2 P2.0 (A) 2

3 CW9F52/CW9F54 P.4 P.3 P.2 P. (T2 P.0 (T2) NC V D D P0.0 (AD P0. (AD P0.2 (AD P0.3 (AD EX) 0) ) 2) 3) P.5 P.6 P.7 RST (RXD) P3.0 NC (TXD) P3. (INT0) P3.2 (INT) P3.3 (T0) P3.4 (T) P pin QFP 44-pin LQFP P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA NC ALE/PROG PSEN P2.7 (A5) P2.6 (A4) P2.5 (A3) V S (WR)P3.6 (WD)P3.7 XTAL2 XTAL S NC (A)P2.0 (A9)P2. ( A0)P2. 2 (A)P2.3 (A2)P2.4 PIN CONFIGURATION(CONTINUED) BLOCK DIAGRAM RAM Flash K/6K Timer 0 (6-bit) Timer (6-bit) Timer 2 (6-bit) Watchdog Timer Security Loc 05 CPU Core Interrupt Control I/O Port 0 I/O I/O Port I/O I/O Port 2 I/O I/O Port 3 I/O -bit Enhanced UART Oscillator Figure. Block Diagram 3

4 CW9F52/CW9F54 4 PIN DESCRIPTION in No. P Description Function (L)QFP DIP Type Name ain m e Alternat P Timer/Counter to input count T2: 2 from Timer/Counter out Clock or P. 4 2 capture/reload 2 Timer/Counter T2EX: control & direction trigger P P P P P P.7 3 I/O with internal pull-up Port The pull-ups. internal with I/O port bi-directional -bit pulled are pins Port inputs. LS TTL drive can buffers output them and to written are s when pullups internal the by high high have P.7 P.6, P.5, state. this in inputs as used be can ma. 6 of drive current - device. the reset will cycles machine two for pin the on high a running, is oscillator the While I RST 4 9 P I input Receive UART RXD: O P3. 7 output Transmit UART TXD: I P3.2 2 Input Interrupt INT0: I P Input Interrupt INT: I P Timer/Counter to input count T0: I P3.5 5 Timer/Counter to input count T: O P e strob Write Memory Data WR: O P Port The pull-ups. internal with I/O port bidirectional -bit pulled are pins 3 Port inputs. LS TTL drive can buffers output them and to written are s when pullups internal the by high state. this in inputs as used be can strobe Read Memory Data RD: O XTAL2 4 from the utput O amplifier. oscillator inverting clock internal the to and amplifier oscillator inverting the to Input I XTAL 5 9 V S S d Groun I.20 Rev

5 PIN DESCRIPTION(CONTINUED) P in DIP No. (L)QFP Name P2.0 P2. P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE/ PROG EA P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0. P0.0 VD 4 D Type I/O with internal pull-up I/O I/O I I/O I main -bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled high by the internal pull-ups when s are written to them and can be used as inputs in this state. Function Description CW9F52/CW9F54 Alternate Port 2 sends the high-order address during fetches from external program memory and during accesses to external Data Memory that use 6-bit address. In this application, it uses strong internal pull-ups when transiting to s. Program Store Enable: it is the Read strobe to external program. When the device is executing from internal program memory, it is inactive (High). When the device is executing code from external program memory, it is activated twice each machine cycle. Address Latch E nable: ALE is the output signal for latching the low byte of the address during an access to external mem ory. This pin is also the programming pulse input (PROG) for flash programming. Normally the A LE is emitted at a constant rate of /6 the crystal frequency. However, if AO is set to, ALE is disabled. Access Enable: EA must be connected to V internal program execution. -bit open drain bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have s written to them float, and in this state can be used as high- impedance inputs. pull-ups are required as a general purpose I/O port. Power Supply SS for external program execution, and to V D D for Port 0 is the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when transitioning to s. 5

6 PIN DESCRIPTION(CONTINUED) P in No. DIP (L)QFP Name NC Type main Function Description CW9F52/CW9F54 Alternate Note : It is not necessary to receive a 2V programming voltage during flash programming. Note 2: A LE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes normal working mode. The solution is to add a pull-up resistor of 3~50 kω to VD D for ALE pin. N ote 3: For 6 clock mode, ALE is emitted at /3 of crystal frequency. MEMORY ORGANIZATION No Internal Connect The device has separate address spaces for program and data memory. Program Flash Memory There is an internal flash memory in the device. The flash memory has /6KByte Data RAM Memory T he data RAM has 52 Bytes on-chip memory. The first 256 Bytes are on-chip RAM and available by default. The second 256 Bytes are on-chip XRAM and enabled by clearing the EXTRAM bit in the AUXR register. The RAM can be addressed up to 64KB for external data memory. other than Expanded Data RAM Addressing The CW9F5x have the capability of 52 Bytes of RAM. See Figure 2. The device has four sections of internal data memory:. The lower 2 Bytes of RAM (00H to 7FH) are directly and indirectly addressable. 2. The higher 2 Bytes of RAM (0H to FFH) are indirectly addressable. 3. The special function registers (0H to FFH) are directly addressable only. 4. The expanded RAM of 256 Bytes (00H to FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. S ince the upper 2 bytes occupy the same addresses as the SFRs, the RAM must be accessed indirectly. The RAM and SFRs space are physically separate even though they have the same addresses. 6

7 CW9F52/CW9F54 When instructions access addresses in the upper 2 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used. The extra 256 Bytes of memory is physically located on the chip and logically occupies the first 256 bytes of external memory (addresses 000H to FFH). When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R or DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7 (RD), or P2. Access to external memory higher than FFH using the MOVX instruction will access external memory (000H to FFFFH) and will perform in the same way as the standard 05, with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. When EXTRAM =, and will be similar to the standard 05. Using provides an -bit address with multiplexed data on Port 0. Other output port pins can be used to output higher order address bits. This provides external paging capabilities. Using generates a 6-bit address. This allows external addressing up the 64K. Port 2 provides the high-order eight address bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with data. Both and generates the necessary read and write signals (P3.6 - WR and P3.7 - RD) for external memory use. Data Memory RD, WR with EXTRAM bit A or MOVX A or MOVX AUXR ADDR<000H ADDR >= 000H ADDR = Any EXTRAM = 0 RD / WR not asserted RD / WR asserted RD / WR not asserted EXTRAM = RD / WR asserted RD / WR asserted RD/ WR asserted The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM (lower 2 bytes and upper 2 bytes). The stack pointer may not be located in any part of the expanded RAM. 7

8 CW9F52/CW9F54 FFH FFH (Indirect Addressing) FFH (Direct Addressing) Expanded RAM 256 Bytes 0H 7FH Upper 2 Bytes Internal RAM Lower 2 Bytes Internal RAM 0H Special Function Registers (SFRs) 000H (Indirect Addressing) 00H (Indirect & Direct Addressing) FFFFH (Indirect Addressing) FFFFH (Indirect Addressing) Data Memory Data Memory FFH 000H Expanded RAM 000H 0000H EXTRAM = 0 EXTRAM = Figure 2. Internal and Data Memory Structure FFFFH EA = 0 Exter 64 KByte 3FFFH EA = FFFH EA = 0000H 0000H 0000H CW9F54 CW9F52 Figure 3. Program Memory structure

9 CW9F52/CW9F54 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on EA Pin to V SS VEA -0.5 to +4.0 V DC Voltage on Any Pin to Ground VPIN -0.5 to VDD+0.5 V Transient Voltage (<20ns) on Any Other Pin to V SS -.0 to VDD+.0 V Maximum Current per I/O Pins P.5, P.6, P.7 IOL 20 ma Maximum Current per I/O for All Other Pins IOL 5 ma Power Dissipation (T A = 25 C).5 W Storage Temperature -65 to +50 C Through Hole Lead Soldering Temperature (0 Seconds) 300 C Surface Mount Solder Reflow Temperature (0 sec) 260 C Output Short Circuit Current 50 ma Note : Applied conditions greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2: All packages are 260 C capable in all solder versions. Note 3: Outputs shorted for no more than one second. No more than one output shorted at a time. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Oscillator Frequency Operating Ambient Temperature Symbol Min Max Unit VDD V fosc 0 33 MHz TA C RELIABILITY CHARACTERISTICS Parameter Symbol Test Method Min Unit Endurance NEND JEDEC Standard A7 0,000 Cycles Data Retention TDR JEDEC Standard A03 00 Years Latch Up ILTH JEDEC Standard IDD ma RECOMMENDED SYSTEM POWER-UP TIMINGS Parameter Symbol Min Unit Power-up to Read Operation TPU-READ 00 μs Power-up to Write Operation TPU-WRITE 00 μs PIN IMPEDANCE (TA=25 C, f= Mhz, other pins open) Parameter Symbol Test Conditions Max Unit I/O Pin Capacitance CI/O VI/O = 0V 5 pf Input Capacitance CIN VIN = 0V 2 pf Pin Inductance LPIN 20 nh 9

10 DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +5 C; VDD = 4.5 to 5.5V; VSS = 0V) CW9F52/CW9F54 Parameter Symbol Test Conditions Min Max Unit Input Low Voltage VIL VDD - 0. V Input High Voltage VIH 0.2VDD VDD V Input High Voltage (XTAL, RST) VIH 0.7VDD VDD V Output Low Voltage (Ports.5,.6,.7) VOL VDD = 4.5V, IOL=6mA.0 V IOL = 00μA Output Low Voltage VDD = 4.5V IOL =.6mA (Ports, 2, 3) VOL IOL = 3.5mA 2.0 V Output Low Voltage (Port 0, ALE, PSEN),3 Output High Voltage (Ports,2,3, ALE, PSEN) 4 Output High Voltage (Port 0 in Bus Mode) 4 Logical 0 Input Current (Ports, 2, 3) VOL VOH VOH VDD = 4.5V IOL = 200μA IOL = 3.2mA V IOH = -0μA V DD VDD = 4.5V IOH = -30μA V DD V IOH = -60μA V DD -.5 IOH = -200μA VDD IOH = -3.2mA VDD V IIL VIN = 0.4V -75 μa Logical -to-0 Transition Current (Ports, 2, 3) 5 ITL VIN = 2V -650 μa Input Leakage Current (Port 0) ILI 0.45V < VIN < VDD-0.3 ±0 μa RST Pull-down Resistor RRST KΩ Pin Capacitance 6 25 C 5 pf Power 32 ma Supply Idle MHz 26 ma Current Power-down min VDD = 2V 50 μa Note : Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 5mA; Maximum IOL per -bit port: 26mA; Maximum IOL total for all outputs: 7mA. If IOL exceeds the test condition, VOL may exceed the related specific- ation. Pins are not guaranteed to sink current greater than the listed test conditions. Note 2: Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports and 3. The noise is due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make -to-0 transitions during bus operations. In the worst cases (capacitive loading > 00pF), the noise pulse on the ALE pin may exceed 0.V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Note 3: Load capacitance for Port 0, ALE and PSEN= 00pF, load capacitance for all other outputs = 0 pf. Note 4: Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD specification when the address bits are stabilizing. Note 5: Pins of Ports, 2, and 3 source a transition current when they are being externally driven from to 0. The transition current reaches its maximum value when VIN is approximately 2V. Note 6: Pin capacitance is characterized but not tested. EA is 25pF (max). 0

11 CW9F52/CW9F54 AC ELECTRICAL CHARACTERISTICS (Load Capacitance for Port 0, ALE, and PSEN = 00pF; for All Other Outputs = 0pF. Input Rise/Fall Time = 0ns. T = -40 C to +5 C, VDD = 4.5 to 5.5V@33MHz, VSS = 0V) 25MHz(xMode) 33MHz(xMode) Variable Oscillator Parameter Symbol 2MHz(x2Mode) 6MHz(x2Mode) Unit Min Max Min Max Min Max x Mode Oscillator Freq. /T CLCL MHz x2 Mode Oscillator Freq. /2T CLCL MHz ALE Pulse Width T LHLL TCLCL- 5 ns Address Valid to ALE Low T AVLL 5 TCLCL-5 ns Address Hold After ALE Low T LLAX 5 TCLCL-5 ns ALE Low to Valid Instr. In T LLIV 66 4TCLCL 45 ns ALE Low to PSEN Low T LLPL 5 TCLCL-5 ns PSEN Pulse Width T PLPH 76 3TCLCL- 5 ns PSEN Low to Valid Instr. In T PLIV 4 3TCLCL 50 ns Input Instr. Hold After PSEN T PXIX 0 ns Input Instr. Float After PSEN T PXIZ 5 TCLCL 5 ns PSEN to Address valid T PXAV TCLCL - ns Address to Valid Instr. In T AVIV 92 5TCLCL 60 ns PSEN Low to Address Float T PLAZ ns RD Pulse Width T RLRH 52 6TCLCL 30 ns Write Pulse Width (WE) RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low T WLWH 52 6TCLCL 30 ns T RLDV 02 5TCLCL 50 ns T RHDX ns T RHDZ 49 2TCLCL 2 ns T LLDV 92 TCLCL 50 ns T AVDV 9 9TCLCL 75 ns T LLWL TCLCL 5 3TCLCL + 5 ns T AVWL 9 4TCLCL 30 ns

12 AC ELECTRICAL CHARACTERISTICS(CONTINUED) Parameter Data Valid to WR High to Low Transition Data Hold After WR Data Valid to WR High RD Low to Address Float RD or WR High to ALE High Symbol 25MHz(xMode) 2MHz(x2Mode) Note:. Calculated values are for x Mode only. CW9F52/CW9F54 Description of Symbols: Each timing symbol has 5 characters. The first character is always a T (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW or ALE P: PSEN TQVWX 20 0 TCLCL 20 ns TWHQX 0 TCLCL 20 ns T QVWH 62 7TCLCL 50 ns T RLAZ ns TWHLH 5 45 TCLCL 5 TCLCL + 5 ns For example: TAVLL = Time from Address Valid to ALE Low TLLPL = Time from ALE Low to PSEN Low 33MHz(xMode) 6MHz(x2Mode) Q: Output data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: High Impedance (Float) Variable Oscillator Min Max Min Max Min Max Unit 2

13 AC ELECTRICAL CHARACTERISTICS(CONTINUED) CW9F52/CW9F54 ALE T LHLL PSEN T AVL L T LLPL T LLIV T PLIV T PLPH T PXAV PORT 0 PORT 2 T LLAX T PLAZ T PXIZ T PXIX A0 - A7 INSTR IN T AVI V A - A5 A0 - A7 A - A5 Figure 4. Program Memory Read Cycle ALE T LHLL T WHLH PSEN T LLDV T RLRH T LLWL RD T AVLL T LLAX T RLAZ T RLDV T RHDZ T RHDX PORT 0 A0-A7 FROM RI or DPL DATA IN A0-A7 FROM PCL INSTR IN T AVWL PORT 2 T AVDV P2[7:0] or A-A5 FROM DPH A-A5 FROM PCH Figure 5. Data Memory Read Cycle ALE T LHLL T WHLH PSEN TLWLL T WLWH WR T AVLL T LLAX T QVWX TQVWH T WHQX PORT 0 A0-A7 FROM RI or DPL DATA OUT A0-A7 FROM PCL INSTR IN T AVWL PORT 2 P2[7:0] or A-A5 FROM DPH A-A5 FROM PCH Figure 6. Data Memory Write Cycle 3

14 EXTERNAL CLOCK DRIVE CW9F52/CW9F54 Parameter Symbol 2 MHz 33 MHz Variable Min Max Min Max Min Max Unit Oscillator Frequency /T CLCL 0 40 MHz Clock Period T CLCL ns High Time T CHCX T CLCL 0.65T CLCL ns Low Time T CLCX T CLCL 0.65T CLCL ns Rise Time T CLCH 20 0 ns Fall Time T CHCL 20 0 ns V DD V 0.7V DD 0.2 V DD - 0. T CHCX T CLCX T CLCH T CHCL T CLCL Figure 7. Clock Drive Waveform SERIAL PORT TIMING Parameter Symbol 2MHz 33MHz Variable Min Max Min Max Min Max Serial Port Clock Cycle Time T XLXL TCLCL μs Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge TQVXH TCLCL - 33 ns Unit 50 2TCLCL - 7 ns T XHQX 2TCLCL - 50 ns Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid T XHDX ns T XHDV TCLCL - 33 ns INSTRUCTION ALE CLOCK OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI T XLXL TQVXH TXHQX T XHDX T XHDV SET TI VALID VALID VALID VALID VALID VALID VALID VALID SET R I Figure. Shift Register Mode Timing Waveforms 4

15 TEST DIAGRAM CW9F52/CW9F54 V IHT V ILT V HT V LT V LOAD +0.V V LOAD V LOAD -0.V Timing Reference Points V OH -0.V V OL +0.V AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.) Note: VHT- VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test For timing purposes, a port pin is no longer floating when a 00 mv change from load voltage occurs, and begins to float when a 00 mv change from the loaded VOH/VOL level occurs. IOL/IOH = ± 20mA. Figure 9. AC Testing Input/Output Waveform Figure0. Float Waveform VDD IDD V DD VDD TO TESTER VDD P0 TO DUT RST EA CL CLOCK SIGNAL (NC) XTAL2 XTAL V SS All other pins disconnected Figure. A Test Load Example Figure2. I DD Test Condition, Active Mode VDD VDD IDD VDD VDD = 2V VDD IDD VDD VDD P0 P0 RST EA RST EA (NC) XTAL2 CLOCK SIGNAL XTAL VSS (NC) XTAL2 XTAL VSS All other pins disconnected All other pins disconnected Figure3. IDD Test Condition, Idle Mode Figure4. IDD Test Condition, Power-down Mode 5

16 CW9F52/CW9F54 PHYSICAL DIMENSIONS QFP44 A A E2 Ø2x E2 Øx E B2 B B E2 A3 A2 A4 θ3 D2 R θ θ3 D D X C3 C C4 DETAIL X θ2 C2 R2 Symbol Dimension(mm) Dimension(mm) Symbol Min Max Min Max Ø3 Ø2 θ θ2 θ3 6

17 C5 CW9F52/CW9F54 PDIP40 θ D2 C4 A Ø B C3 C C2 A5 A3 A A2 A4 D D θ2 A6 Symbol Dimension(mm) Dimension(mm) Symbol Min Max Min Max Ø θ θ2 7

18 LQFP44 A CW9F52/CW9F54 D A B B INDEX D2 C C A D B A B θ F E 0.50 E E2 0.5 Symbol A A B B C C D Dimension(mm) Dimension(mm) Symbol Min Max Min Max (TYP) D D E E 0.50 E2 0.5 F 0.20 θ 0