8XC51RA RB RC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Transcription

1 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C51RA 83C51RA 80C51RA 87C51RB 83C51RB 87C51RC 83C51RC See Table 1 for Proliferation Options High Performance CHMOS EPROM ROM CPU 24 MHz Operation 512 Bytes of On-Chip Data RAM Dedicated Hardware Watchdog Timer (One-Time Enabled with Reset-Out) Three 16-Bit Timer Counters Programmable Clock Out Up Down Timer Counter Three Level Program Lock System 8K 16K 32K On-Chip Program Memory Improved Quick Pulse Programming Algorithm Boolean Processor 32 Programmable I O Lines 6 Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Four-Level Interrupt Priority Extended Temperature Range (b40 C toa85 C) MEMOR ORGANIZATION ROMless ROM EPROM ROM EPROM RAM Device Device Version Bytes Bytes 80C51RA 83C51RA 87C51RA 8K C51RA 83C51RB 87C51RB 16K C51RA 83C51RC 87C51RC 32K 512 These devices can address up to 64 Kbytes of external program data memory The Intel 8XC51RA 8XC51RB 8XC51RC is a single-chip control-oriented microcontroller which is fabricated on Intel s reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC51RA 8XC51RB 8XC51RC uses the same powerful instruction set has the same architecture and is pinfor-pin compatible with the existing MCS 51 family of products The 8XC51RA 8XC51RB 8XC51RC is an enhanced version of the 8XC52 8XC54 8XC58 The added features make it an even more powerful microcontroller for applications that require 512 bytes of on-chip data RAM and dedicated hardware WatchDog Timer with reset-out features Throughout this document 8XC51RX will refer to the 8XC51RA 8XC51RB and 8XC51RC unless information applies to a specific device For a detailed description of 8XC51RA RB RC refer to the 8XC51RA RB RC Hardware Description order number Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPRIGHT INTEL CORPORATION 1995 December 1995 Order Number

2 Table 1 Proliferations Options Standard C51RA X X X X 83C51RA X X X X 87C51RA X X X X 83C51RB X X X X 87C51RB X X X X 83C51RC X X X X 87C51RC X X X X NOTES MHz to 12 MHz 5V g20% MHz to 16 MHz 5V g20% MHz to 20 MHz 5V g20% MHz to 24 MHz 5V g10% Figure 1 8XC51RX Block Diagram

3 PROCESS INFORMATION This device is manufactured on P629 5 achmos III-E process Additional process and reliability information is available in the Intel Quality System Handbook. PACKAGES Part Prefix Package Type 8XC51RX P 40-Pin Plastic DIP (OTP) 8XC51RX N 44-Pin PLCC (OTP) 8XC51RX S 44-Pin QFP (OTP) PLCC DIP Do not connect reserved pins QFP Figure 2 Pin Connections

4 PIN DESCRIPTIONS V CC Supply voltage V SS Circuit ground V SS1 Secondary ground (not on DIP) Provided to reduce ground bounce and improve power supply by-passing NOTE This pin is not a substitute for the V SS pin (pin 22) (Connection not necessary for proper operation ) Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1 s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting 1 s and can source and sink several LS TTL inputs Port 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1 s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (I IL on the data sheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the 8XC51RX Port Pin P1 0 P1 1 Alternate Function T2 (External Count Input to Timer Counter 2) Clock-Out T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) Port 1 receives the low-order address bytes during EPROM programming and verifying Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive LS TTL inputs Port 2 pins that have 1 s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (I IL on the data sheet) because of the internal pullups Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1 s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Some Port 2 pins receive the high-order address bits during EPROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1 s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (I IL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the 8051 Family as listed below Port Pin Alternate Function P3 0 RXD (serial input port) P3 1 TXD (serial output port) P3 2 INT0 (external interrupt 0) P3 3 INT1 (external interrupt 1) P3 4 T0 (Timer 0 external input) P3 5 T1 (Timer 1 external input) P3 6 WR (external data memory write strobe) P3 7 RD (external data memory read strobe) RST Reset I O A high on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum V IHI voltage is applied whether the oscillator is running or not An internal pulldown resistor permits a power-on reset with only a capacitor connected to V CC After a WatchDog Timer overflow this RST pin will drive an output high pulse at a minimum V OH2 for 96 x T OSC duration while the internal reset signal is active ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to ex- 4

5 ternal memory This pin (ALE PROG) is also the program pulse input during EPROM programming for the 87C51RX In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With this bit set the pin is weakly pulled high However the ALE disable feature will be suspended during a MOVX or MOVC instruction idle mode power down mode and ICE mode The ALE disable feature will be terminated by reset When the ALE disable feature is suspended or terminated the ALE pin will no longer be pulled up weakly Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode Throughout the remainder of this data sheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG pin PSEN Program Store Enable is the read strobe to external Program Memory When the 8XC51RX is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory EA V PP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFFH Note however that if any of the Lock bits are programmed EA will be internally latched on reset EA should be strapped to V CC for internal program executions This pin also receives the programming supply voltage (V PP ) during EPROM programming XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of a inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 3 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 Oscillators for Microcontrollers Order No C1 C2 e 30 pf g10 pf for Crystals For Ceramic Resonators contact resonator manufacturer Figure 3 Oscillator Connections To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 4 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed An external oscillator may encounter as much as a 100 pf load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the V IL and V IH specifications the capacitance will not exceed 20 pf Figure 4 External Clock Drive Configuration IDLE MODE The user s software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle 5

6 Mode Table 2 Status of the External Pins during Idle and Power Down Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data Mode will be exited if the chip is reset or if an enabled interrupt occurs POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated On the 8XC51RX either a hardware reset or an external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the on-chip RAM An external interrupt allows both the SFRs and on-chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before V CC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 and INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down DEDICATED HARDWARE WATCHDOG TIMER (One-Time Enabled with Reset-Out) The 8XC51RX contains a dedicated WatchDog Timer (WDT) to allow recovery from software or hardware upset WDT is disabled upon power-up To enable the WDT user must write 1EH and E1H in sequence to WDTRST Special Function Register Once the WDT is enabled the 14-bit counter will increment every machine cycle While the oscillator is running the WDT will be incrementing and cannot be disabled The counter is reset by writing 1EH and E1H in sequence to the WDTRST If the counter is not reset before it reaches 3FFFH (16383D) the chip will be forced into reset sequence and the WDT will be disabled as upon power-up During this reset the chip will drive an output Reset-High pulse for the duration of 96 x T OSC at the RST pin The duration of the Reset-High pulse works out to 6 00 ms 16 MHz While in the Idle mode the WDT continues to count If the user does not wish to exit the Idle mode with a reset then the processor must periodically woken up to service the WDT In Power Down mode the WDT stops counting and holds its current value DESIGN CONSIDERATION The window on the D87C51RX must be covered by an opaque label Otherwise the DC and AC characteristics may not be met and the device may be functionally impaired When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory NOTE For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors Handbook Volume I (Order No ) and Application Note AP-252 (Embedded Applications Handbook Order No ) Designing with the 80C51BH 6

7 ONCE MODE The ONCE ( On-Circuit Emulation ) Mode facilitates testing and debugging of systems using the 8XC51RX without the 8XC51RX having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins float and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the 8XC51RX is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied 8XC51RX EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the MCS 51 family of microcontrollers These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range with or without burn-in With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C toa70 C With the extended temperature range option operational characteristics are guaranteed over the range of b40 C to a85 C The optional burn-in is dynamic for a minimum time of 168 hours at 125 C with V CC e 6 9V g0 25V following guidelines in MIL-STD-883 Method 1015 Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number The prefixes are listed in Table 3 For the extended temperature range option this data sheet specifies the parameters which deviate from their commercial temperature range limits Prefix Package Type Table 3 Prefix Identification Temperature Range Burn-In P Plastic Commercial No N PLCC Commercial No S QFP Commercial No TP Plastic Extended No TN PLCC Extended No TS QFP Extended No LP Plastic Extended es LN PLCC Extended es LS QFP Extended es NOTE Contact distributor or local sales office to match EXPRESS prefix with proper device EXAMPLES P80C51RA indicates 80C51RA in a plastic package and specified for commercial temperature range without burn-in TS87C51RC indicates 87C51RC in a QFP package and specified for extended temperature range without burn-in 7

8 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias b40 C toa85 C Storage Temperature b65 C toa150 C Voltage on EA V PP Pin to V SS 0V to a13 0V Voltage on Any Other Pin to V SS b0 5V to a6 5V I OL Per I O Pin 15 ma Power Dissipation 1 5W (based on PACKAGE heat transfer limitations not device power consumption) NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability OPERATING CONDITIONS Symbol Description Min Max Units T A Ambient Temperature Under Bias Commercial 0 a70 C Express b40 a85 C V CC Supply Voltage All Others V 8XC51RX V f OSC 0scillator Frequency 8XC51RX MHz 8XC51RX MHz 8XC51RX MHz 8XC51RX MHz DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Symbol Parameter Min Typ (Note 4) V IL Input Low Voltage b V CC b0 1 V V IL1 Input Low Voltage EA V CC b0 3 V Max Unit Test Conditions V IH Input High Voltage 0 2 V CC a0 9 V CC a0 5 V (Except XTAL1 RST) V IH1 Input High Voltage 0 7 V CC V CC a0 5 V (XTAL1 RST) V OL Output Low Voltage (Note 5) 0 3 V I OL e 100 ma (Note 1) (Ports 1 2 and 3) 0 45 V I OL e 1 6 ma (Note 1) 1 0 V I OL e 3 5 ma (Note 1) V OL1 Output Low Voltage (Note 5) 0 3 V I OL e 200 ma (Note 1) (Port 0 ALE PSEN) 0 45 V I OL e 3 2 ma (Note 1) 1 0 V I OL e 7 0 ma (Note 1) V OH Output High Voltage V CC b0 3 V I OH eb10 ma (Ports 1 2 and 3 ALE PSEN) V CC b0 7 V I OH eb30 ma V CC b1 5 V I OH eb60 ma 8

9 DC CHARACTERISTICS (Over Operating Conditions) (Continued) All parameter values apply to all devices unless otherwise indicated Symbol Parameter Min Typ (Note 4) Max Unit Test Conditions V OH1 Output High Voltage V CC b0 3 V I OH eb200 ma (Port 0 in External Bus Mode) V CC b0 7 V I OH eb3 2 ma V CC b1 5 V I OH eb7 0 ma V OH2 Output High Voltage 0 5 V CC V I OH eb800 ma (RST) 0 75 V CC V I OH eb300 ma I IL 0 9 V CC V I OH eb80 ma Logical 0 Input Current (Ports 1 2 and 3) b50 ma V IN e 0 45V I LI Input leakage Current (Port 0) g10 ma V IN e V IL or V IH I TL Logical 1 to 0 Transition Current (Ports 1 2 and 3) Commercial b675 ma V IN e 2V Express b775 ma RRST RST Pulldown Resistor KX CIO Pin Capacitance 10 pf 1 MHz 25 C I CC Power Supply Current (Note 3) Active Mode at 12 MHz (Figure 5) ma at 16 MHz 38 ma at 20 MHz 47 ma at 24 MHz 56 ma Idle Mode at 12 MHz (Figure 5) ma at 16 MHz 9 5 ma at 20 MHz 11 5 ma at 24 MHz 13 5 ma Power Down Mode 5 75 ma NOTES 1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the V OL s of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0 In applications where capacitive loading exceeds 100 pf the noise pulses on these signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt Triggers or CMOS-level input logic 2 Capacitive loading on Ports 0 and 2 cause the V OH on ALE and PSEN to drop below the 0 9 V CC specification when the address lines are stabilizing 3 See Figures 6 9 for test conditions Minimum V CC for Power Down is 2V 4 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and 5V 5 Under steady state (non-transient) conditions I OL must be externally limited as follows Maximum I OL per port pin 10mA Maximum I OL per 8-bit port Port 0 26 ma Ports 1 2 and 3 15 ma Maximum total I OL for all output pins 71 ma If I OL exceeds the test condition V OL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 9

10 I CC Max at other frequencies is given by Active Mode I CC Max e 2 2 c Freq a 3 1 Idle Mode I CC Max e 0 5 c Freq a 1 5 Where Freq is in MHz I CC Max is given in ma Figure 5 I CC vs Frequency All other pins disconnected TCLCH e TCHCL e 5ns Figure 6 I CC Test Condition Active Mode All other pins disconnected TCLCH e TCHCL e 5ns Figure 7 I CC Test Condition Idle Mode All other pins disconnected Figure 8 I CC Test Condition Power Down Mode V CC e 2 0V to 6 0V Figure 9 Clock Signal Waveform for I CC Tests in Active and Idle Modes TCLCH e TCHCL e 5ns 10

11 EXPLANATION OF THE AC SMBOLS Each timing symbol has 5 characters The first character is always a T (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) L Logic level LOW or ALE P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low AC CHARACTERISTICS (Over Operating Conditions Load Capacitance for Port 0 ALE PROG and PSEN e 100 pf Load Capacitance for All Other Outputs e 80 pf) EXTERNAL MEMOR CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 8XC51RX refers to 8XC51RX and 8XC51RX-1 8XC51RX-24 refers to 8XC51RX-20 and 8XC51RX-24 Symbol Description 12 MHz 20 MHz 24 MHz Variable Oscillator Oscillator Oscillator Oscillator Min Max Min Max Min Max Min Max 1 TCLCL Oscillator Frequency 8XC51RX MHz 8XC51RX MHz 8XC51RX MHz 8XC51RX MHz TLHLL ALE Pulse Width TCLCL b 40 ns TAVLL Address Valid to TCLCL b 40 ns ALE Low TLLAX Address Hold After TCLCL b 30 ns ALE Low TLLIV ALE Low to Valid Instruction In 8XC51RX TCLCL b 100 ns 8XC51RX TCLCL b 75 ns TLLPL ALE Low to PSEN TCLCL b 30 ns Low TPLPH PSEN Pulse Width TCLCL b 45 ns TPLIV PSEN Low to Valid Instruction In 8XC51RX TCLCL b 105 ns 8XC51RX TCLCL b 90 ns TPXIX Input Instruction ns Hold After PSEN Units 11

12 EXTERNAL MEMOR CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated Symbol TPXIZ Description 12 MHz 20 MHz 24 MHz Variable Oscillator Oscillator Oscillator Oscillator Min Max Min Max Min Max Min Max Input Instruction Float After PSEN 8XC51RX 59 TCLCLb25 ns 8XC51RX TCLCLb20 ns TAVIV Address to Valid Instruction TCLCLb105 ns In TPLAZ PSEN Low to Address Float ns TRLRH RD Pulse Width TCLCLb100 ns TWLWH WR Pulse Width TCLCLb100 ns TRLDV RD Low to Valid Data In 8XC51RX TCLCLb165 ns 8XC51RX TCLCLb95 ns TRHDX Data Hold After RD ns TRHDZ Data Float After RD TCLCLb60 ns TLLDV TAVDV ALE Low to Valid Data In 8XC51RX TCLCLb150 ns 8XC51RX TCLCLb90 ns Address to Valid Data In 8XC51RX TCLCLb165 ns 8XC51RX TCLCLb90 ns TLLWL ALE Low to RD or WR Low TCLCLb50 3 TCLCLa50 ns TAVWL TQVWX TWHQX TQVWH Address Valid to WR Low 8XC51RX TCLCLb130 ns 8XC51RX TCLCLb90 ns Data Valid before WR 8XC51RX 33 TCLCLb50 ns 8XC51RX TCLCLb35 ns 8XC51RX TCLCLb30 ns Data Hold after WR 8XC51RX 33 TCLCLb50 ns 8XC51RX TCLCLb40 ns 8XC51RX-24 7 TCLCLb30 ns Data Valid to WR High 8XC51RX TCLCLb150 ns 8XC51RX TCLCLb70 ns TRLAZ RD Low to Address Float ns TWHLH RD or WR High to ALE High 8XC51RX TCLCLb40 TCLCLa40 ns 8XC51RX TCLCLb30 TCLCLa30 Units 12

13 EXTERNAL PROGRAM MEMOR READ CCLE EXTERNAL DATA MEMOR READ CCLE EXTERNAL DATA MEMOR WRITE CCLE

14 SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions Over Operating Conditions Load Capacitance e 80 pf Symbol Parameter 12 MHz 20 MHz 24 MHz Variable Oscillator Oscillator Oscillator Oscillator Min Max Min Max Min Max Min Max TXLXL Serial Port Clock TCLCL ms Cycle Time TQVXH Output Data TCLCL b 133 ns Setup to Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge 8XC51RX 50 2 TCLCL b 117 ns 8XC51RX TCLCL b 50 ns TXHDX Input Data Hold ns After Clock Rising Edge TXHDV Clock Rising TCLCL b 133 ns Edge to Input Data Valid Units SHIFT REGISTER MODE TIMING WAVEFORMS

15 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1 TCLCL Oscillator Frequency 8XC51RX XC51RX MHz 8XC51RX XC51RX TCHCX High Time 0 35 T OSC 0 65 T OSC ns TCLCX Low Time 0 35 T OSC 0 65 T OSC ns TCLCH Rise Time 8XC51RX 20 ns 8XC51RX ns TCHCL Fall Time20 ns 8XC51RX 20 ns 8XC51RX ns EXTERNAL CLOCK DRIVE WAVEFORM AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS AC Inputs during testing are driven at V CC b0 5V for a Logic 1 and 0 45V for a Logic 0 Timing measurements are made at V IH min for a Logic 1 and V IL max for a Logic For timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded V OH V OL level occurs I OL I OH e g20 ma 15

16 PROGRAMMING THE EPROM The part must be running with a 4 MHz to 6 MHz oscillator The address of an EPROM location to be programmed is applied to address lines while the code byte to be programmed in that location is applied to data lines Control and program signals must be held at the levels indicated in Table 4 Normally EA V PP is held at logic high until just before ALE PROG is to be pulsed The EA V PP is raised to V PP ALE PROG is pulsed low and then EA V PP is returned to a high (also refer to timing diagrams) DEFINITION OF TERMS ADDRESS LINES P1 0 P1 7 P2 0 P2 5 respectively for A0 A13 DATA LINES P0 0 P0 7 for D0 D7 CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3 P3 6 P3 7 PROGRAM SIGNALS ALE PROG EA V PP NOTES Exceeding the V PP maximum for any amount of time could damage the device permanently The V PP source must be well regulated and free of glitches Mode RST PSEN Table 4 EPROM Programming Modes ALE PROG EA V PP P2 6 P2 7 P3 3 P3 6 P3 7 Program Code Data H L 12 75V L H H H H Verify Code Data H L H H L L L H H Program Encryption H L 12 75V L H H L H Array Address 0 3FH Program Lock Bit 1 H L 12 75V H H H H H Bits Bit 2 H L 12 75V H H H L L Bit 3 H L 12 75V H L H H L Read Signature Byte H L H H L L L L L 16

17 See Table 4 for proper input on these pins Figure 10 Programming the EPROM PROGRAMMING ALGORITHM Refer to Table 4 and Figures 10 and 11 for address data and control signals set up To program the 87C51RX the following sequence must be exercised 1 Input the valid address on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA V PP from V CC to 12 75V g0 25V 5 Pulse ALE PROG 5 times for the EPROM array and 25 times for the encryption table and the lock bits Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached PROGRAM VERIF Program verify may be done after each byte or block of bytes is programmed In either case a complete verify of the programmed array will ensure reliable programming of the 87C51RX The lock bits cannot be directly verified Verification of the lock bits is done by observing that their features are enabled Figure 11 Programming Signal s Waveforms 17

18 ROM and EPROM Lock System The program lock system when programmed protects the onboard program against software piracy The 83C51RX has a one-level program lock system and a 64-byte encryption table See line 2 of Table 5 If program protection is desired the user submits the encryption table with their code and both the lock-bit and encryption array are programmed by the factory The encryption array is not available without the lock bit For the lock bit to be programmed the user must submit an encryption table The 87C51RX has a 3-level program lock system and a 64-byte encryption array Since this is an EPROM device all locations are user-programmable See Table 5 Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1 s) Every time that a byte is addressed during a verify 6 address lines are used to select a byte of the Encryption Array This byte is then exclusive-nor ed (XNOR) with the code byte creating an Encryption Verify byte The algorithm with the array in the unprogrammed state (all 1 s) will return the code in its original unmodified form For programming the Encryption Array refer to Table 4 (Programming the EPROM) When using the encryption array one important factor needs to be considered If a code byte has the value 0FFH verifying the byte will produce the encryption byte value If a large block (l64 bytes) of code is left unprogrammed a verification routine will display the contents of the encryption array For this reason all unused code bytes should be programmed with some value other than 0FFH and not all of them the same value This will ensure maximum program protection Program Lock Bits The 87C51RX has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data If any program lock bits were programmed erasing the EPROM will not erase the program lock bits and programming of the EPROM is disabled Reading the Signature Bytes The 8XC51RX has 3 signature bytes in locations 30H 31H and 60H To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 4 for Read Signature Byte Location Device Contents 30H All 89H 31H All 58H 60H 87C51RC C2H 87C51RB 87C51RA 83C51RC 83C51RB 83C51RA Erasure Characteristics (Windowed Packages Only) C1H C0H 42H C2H 41H C1H 40H C0H Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately Angstroms Since sunlight and fluorescent lighting have wavelengths in this range exposure to these light sources over an extended time (about 1 week in sunlight or 3 years in roomlevel fluorescent lighting) could cause inadvertent erasure If an application subjects the device to this type of exposure it is suggested that an opaque label be placed over the window The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec cm2 Exposing the EPROM to an ultraviolet lamp of mw cm2 rating for 30 minutes at a distance of about 1 inch should be sufficient Erasure leaves all the EPROM Cells in a 1 s state 18

19 Program Lock Bits LB1 LB2 LB3 Table 5 Program Lock Bits and the Features Protection Type 1 U U U No Program Lock features enabled (Code verify will still be encrypted by the Encryption Array if programmed ) 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on Reset and further programming of the EPROM is disabled 3 P P U Same as 2 also verify is disabled 4 P P P Same as 3 also external execution is disabled NOTE Any other combination of the lock bits is not defined EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (T A e 21 C to27 C V CC e 5V g20% V SS e 0V) Symbol Parameter Min Max Units V PP Programming Supply Voltage V I PP Programming Supply Current 75 ma 1 TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold after PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold after PROG 48TCLCL TEHSH (Enable) High to V PP 48TCLCL TSHGL V PP Setup to PROG Low 10 ms TGHSL V PP Hold after PROG 10 ms TGLGH PROG Width ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float after ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ms 19

20 EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 5 pulses for the EPROM array 25 pulses for the encryption table and lock bits Thermal Impedance All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and applications See the Intel Packaging Handbook (Order Number ) for a description of Intel s thermal impedance test methodology Package i JA i JC Device P 45 C W 16 C W All N 46 C W 16 C W All S 87 C W 18 C W 51RA 96 C W 24 C W 51RB 90 C W 22 C W 51RC DATA SHEET REVISION HISTOR Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following differences exist between this datasheet ( ) and the previous version ( ) 1 ADVANCE INFORMATION datasheet replaces PRODUCT PREVIEW datasheet 2 I TL (Commercial) changed from b650 ma to b675 ma 3 I TL (Express) changed from b750 ma to b775 ma 4 8XC51RX-24 V CC changed from 5V g20% to 5V g10% 5 Remove all CERDIP package types (prefix D TD LD) INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA Tel (408) INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) INTEL JAPAN k k Ibaraki-ken Tel