HMT7742 GENIE IO-Link Device PHY hardware/software orientation platform

Transcription

1 General This document is the specification for the TM96. GENIE Explorer I development and TM96. GENIE Explorer I demonstrator modules, which combine the HMT77 GENIE IOLink Device PHY with an tmel Tmega8P microcontroller running an IOLink. conformal Ministack and demonstration application from HMT microelectronic G.. Use cases HMT77 GENIE IOLink Device PHY hardware/software orientation platform The HMT IOLink protocol ministack and demo application source code demonstrate how one can control the full feature set of the HMT77 GENIE IOLink Device PHY. These include source code examples of: MultiOctet URT Mode Transparent Mode device configuration SingleOctet URT Mode interrupt handling device monitoring HMT77 development platform for sensor or actuator applications Combining the HMT77 GENIE IOLink Device PHY, a supported tmel µc and the HMT IOLink protocol ministack. The customer develops the sensor or actuator application, using the TM96. hardware together with the HMT IOLink ministack and demonstration application source code' as a base. Suitable I/O's on the µc are made available for the connection of a customer specific application. HMT77 GENIE IOLink DUL PHY demonstrator The small format TM96. running a ministack and default application from HMT demonstrates; the physical (PHY) characteristics, the ability to drive SIO loads and the handling of error conditions. EMC demonstrator platform EMC testing carried out on the small format TM96. hardware placed in a realistic sensor enclosure, demonstrates the HMT77's conformity to: surge conducted disturbance ESD burst radiated disturbance reverse polarisation tmel microcontroller demonstrator The TM96. and TM96. running the HMT IOLink ministack and default application demonstrates the capacity of the µc to support the IOLink stack and PHY, and demonstrates the availability of free resources.. References.. TM96. GENIE Explorer I [] HMT77 datasheet (Please see HMT website for latest version) [] tmel Tmega8P 8bit R Microcontroller datasheet.. HMT IOLink Ministack and Demoapplication [] DTSHEET and Source Code IOLink ministack [] DTSHEET and Source Code demoapplication TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

2 Table of Contents General.... Use cases.... References..... TM96. GENIE Explorer I..... HMT IOLink Ministack and Demoapplication.... Overview..... TM96. GENIE Explorer ariant..... TM96. GEINE Explorer ariant Descriptions HMT77 GENIE IOLink Device PHY tmel R Microcontrollers Sensors... 8 Interconnections Power connections JP Microcontroller power & JTG REF connector ariant JP7 Tmega8P external analog reference voltage REF External Connectors JP 0pin SPI Connection to othertmel microcontrollers ariant JP 0pin Development connector I to spare microcontroller pins ariant pin Development connector II to spare microcontroller pins ariant I IEC 6097 M IOLink Connector..... JP8 IOLink connector access points (L+, C/Q, L) TM PP6 Microcontroller programming TM JP Interface connector to tmel R ISP programmer ariant JP Microcontroller debug connector ariant.... Other Connections ariant.... Other Connections ariant..... J RWKE enable jumper..... Ground pins... Programming & Debug Sequence ariant.... SPI access to R.... Debug access to R... Transparent Mode.... Transparent Mode enable jumpers... pplication Examples.... TM96. IOLink Demonstrator & EMC.... TM96. IOLink sensor/actuator application development platform.... TM96. IOLink stack development platform TM96. Choice of Microcontroller Piggy back connector for other tmel microcontroller development IOLink IEC6097 M Mounting Technical Data Remarks bsolute Maximum Ratings Operating Parameters Electrical Parameters Microcontroller Part Numbers... 9 Index of Tables Table : oltagte reference selections for DC... 8 Table : JP Pin assignment... 9 Table : JP7 Pin assignment... 9 Table : JP Pin assignment... 9 Table :JP Pin assignment... 0 Table 6: JP6 pin assignment... 0 Table 7: I Pin assignment... Table 8: PP6 assignment TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

3 Table 9: PP6 coordinates... Table 0: JP Pin assignment... Table : JP Pin assignment... Table : Other connections TM96... Table : JP7 Pin assignment... Table pinstm96... Table : bsolute maximum ratings... 8 Table 6: Operating parameters... 9 Table 7: Electrical parameters... 9 Index of Figures Fig. : TM96. (GENIE Explorer I) ariant... Fig. : TM96. (GENIE Explorer I) ariant... 7 Fig. : JP Microcontroller power & R JTGICE reference voltage... 8 Fig. : JP7 External analog reference voltage for microcontroller analog I/P...9 Fig. : JP 0pin SPI Connector to othertmel microcontrollers... 9 Fig. 6: JP 0pin development connector to spare microcontroller pins... 0 Fig. 7: JP6 6pin development connector to spare microcontroller pins... 0 Fig. 8: I IEC 6097 M IOLink cable connector, front view... Fig. 9: J SPI interface supply voltage select jumper... Fig. 0: tmel microcontroller programming pads... Fig. : JP tmel R ISP programming interface... Fig. : JP Microcontroller debug... Fig. : J RWKE enable jumper for SNS startup level... Fig. : HMT77 + tmel μc + HMT IOLink Ministack and demoapplication... Fig. : HMT77 + tmel μc + Customer protocol stack... Fig. 6: HMT77 + tmel μc + Customer protocol stack and application... 6 Fig. 7: HMT77 + External μc... 6 Fig. 8: Piggyback connector dimensioning... 7 Fig. 9: IEC6097 Mounting to TM96. GENIE Explorer I RINT... 7 Fig. 0: IEC6097 Mounting to TM96. GENIE Explorer I RINT TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

4 . Overview.. TM96. GENIE Explorer ariant block diagram of the TM.0 test module can be seen in Fig. The positioning of each block is consistent with the hardware layout and contains the following: HMT77 GENIE IOLink Device PHY in a DFNL mm x mm package Tmega8P 8bit R microcontroller x LED's [ x Red, x green] push button switch (digital stimulus) rotary potentiometer (analog stimulus) connection to IOLink master over standard M Pole connector connection for microcontroller programming over SPI SPI connection to the HMT77 for further tmel microcontroller development applications expansion ports for complex sensor applications The TM96. is populated with the Tmega8P per default, but may also be populated with the pin compatible Ttiny88 (Ttiny88 MU [MLF Package]). Test module ariant is intended to allow simplified connection for developments kits. The component platform is a layer, mm, standard FR PC. Illustration : TM96. GENIE Explorer I ariant (Development) Customers using the TM96. ariant have the freedom to choose their software development platform. Onboard TMEL microcontrollers may be programmed with customer specific applications via an tmel R ISP, JTGmkII and R Dragon programmers TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

5 P M IEC6097 IOLINK Connector.mm P Footprint for further external protection elements. In addition to the HMT77's internal elements LED LED JP8 JP7 SPI HMT77 SPI + SNS TMEL R μc 6 JP JP6 JP 6 Rotary POT μc nalog Stimuli JP m m 0 JP Digital Switch μc Digital Stimuli JP J JP P P 7mm Fig. : TM96. (GENIE Explorer I) ariant TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

6 .. TM96. GEINE Explorer ariant TM96. is intended for testing in the smallest format, for demonstration and EMC testing. The component platform is a layer, mm, standard FR PC. block diagram of the TM96. test module can be seen in Fig..The positioning of each block is consistent with the hardware layout and contains the following: HMT77 GENIE IOLink Device PHY in a DFNL mm x mm package Tmega8P 8bit R microcontroller in a MLFL mm x mm package x LED's [ x Red, x green] push button switch (digital stimulus) rotary potentiometer (analog stimulus) connection to IOLink master over standard M cable probe pads for microcontroller programming and test The TM96. is populated with the Tmega8P per default, but may also be populated with the pin compatible Ttiny88 (Ttiny88 MU [MLF Package]). Illustration : TM96. GENIE Explorer I ariant (Demonstrator) TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 6/9

7 .mm M IEC6097 IOLINK Connector mm LED Programmer Positioning SPI LED HMT77 RSTN SCK MOSI MISO 0mm TMEL R μc CC Rotary POT μc nalog Stimuli Digital Switch μc Digital Stimuli 6mm.0mm Fig. : TM96. (GENIE Explorer I) ariant TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 7/9

8 . Descriptions.. HMT77 GENIE IOLink Device PHY Technical information on the HMT77 GENIE IOLink Device PHY may be found in reference []... tmel R Microcontrollers The TM96. test module can accept either the Ttiny88 (8k flash) or the Tmega8P(k flash) microcontroller. Where these pinouts are dissimilar, solder bridges are used in order to allow complete compatibility of both devices. In order to support sensor applications where accurate /D conversion is critical, filtering of the analogue supply has been implemented. For conversion, the DC voltage reference should be set to the. internal REF as shown in Table. lternatively, if the external voltage reference pin is to be used (Tmega8P & ariant only) then the capacitor C should be removed. it 7:6 REFS:0: Reference Selection its in R microcontroller REFS REFS0 oltage Reference Selection 0 0 REF, internal REF switched off 0 CC with external capacitor at REF pin 0 Reserved Internal. voltage reference with external capacitor at REF pin Table : oltagte reference selections for DC Please refer to the appropriate microcontroller data sheet for more information... Sensors oth analogue and digital stimuli have been implemented on the the TM96. test module, in the form on a simple bush button switch and rotary potentiometer. More complex sensors may be used together with TM96. ariant module via the JP and/or JP6 and JP7 connectors. Interconnections. Power connections Power to the HMT77 GENIE IOLink Device PHY is applied over the M IEC 6097 cable by an IOLink master. The internal voltage regulator output from the HMT77, SNS, then supplies both the sensor and the microcontroller. This voltage is configurable to either or.. Please refer to reference [] for further information... JP Microcontroller power & JTG REF connector ariant Where tmel microcontrollers are to be programmed using the R JTGICE mkii programming and debug tool, on the SPI interface (JP), a separate microcontroller power and ground connection is implemented. This connection functions only to supply the microcontroller when programming, and to provide a reference voltage for the JTGICE mkii programmer. Fig. : JP Microcontroller power & R JTGICE reference voltage TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 8/9

9 PIN CC μc power, JTG REF μc & JTG ground Table : JP Pin assignment Do not connect both IOLINK master supply and programming supply.. JP7 Tmega8P external analog reference voltage REF Fig. : JP7 External analog reference voltage for microcontroller analog I/P PIN REF nalog REF voltage Ground Table : JP7 Pin assignment. External Connectors.. JP 0pin SPI Connection to othertmel microcontrollers ariant Fig. : JP 0pin SPI Connector to othertmel microcontrollers Pin Pin Ground INT Interrupt Ground SCK SPI Clock Ground 6 MISO Master Input Slave Output 7 Ground 8 MOSI Master Output Slave Input 9 SNS μc and sensor supply 0 SS Slave Select Table : JP Pin assignment TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 9/9

10 .. JP 0pin Development connector I to spare microcontroller pins ariant Fig. 6: JP 0pin development connector to spare microcontroller pins Pin TM96 Ttiny88 Tmega8P Pin TM96 Ttiny88 Tmega8P SP PC(DC/PCINT9) PC(DC/PCINT9) SP0 PINP0(DC6/PCI DC6 NT) SP PC(DC/PCINT 0) PC(DC/PCINT 0) SP PC(DC/PCINT) PC(DC/PCINT SP PC(DC/SD/P CINT) PC(DC/SD/P 6 CINT) SP PC(DC/SCL/PCI NT PC(DC/SCL/PCI NT 7 SPD0 PD0(PCINT6) PD0(RXD/PCINT 8 6) SPD PD(PCINT7) PD(TXD/PCINT7) 9 SPD PD(INT/PCINT PD(PCINT9/OC 0 9) /INT) CLKI P6(CLKI/PCINT6) P6(OSC/XTL/P CINT6) Table :JP Pin assignment.. 6pin Development connector II to spare microcontroller pins ariant 6 Fig. 7: JP6 6pin development connector to spare microcontroller pins Pin TM96 Ttiny88 Tmega8P Pin TM96 Ttiny88 Tmega8P SPD PD(T0/PCINT0) PD(T0/OSC/P CINT9) SPD PD(T/PCINT) PD(T(OS0/PCIN T) SPD6 PD6(IN0/PCINT PD6(IN0/OC0/P ) CINT) SPD7 PD7(IN/PCINT) PD7((IN/PCINT) SPD8 P0(ICP/CLK0/P CINT0) SPD9 P(OC/PCINT) P(OC/PCINT) P0(ICP/CLK0/P 6 CINT0) Table 6: JP6 pin assignment TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 0/9

11 .. I IEC 6097 M IOLink Connector Fig. 8 shows the standard slave/master interface connector for IOLink. The pin assignment for this connector may be seen in Table 7. The M variant of this connector is used to keep the PC board size to a minimum. NOTE: The IOLink plug is female on the master and male on the slave Male Female Fig. 8: I IEC 6097 M IOLink cable connector, front view Pin Pin L+ Power Supply L Ground C/Q SIO/SDCI Table 7: I Pin assignment.. JP8 IOLink connector access points (L+, C/Q, L) TM96. Fig. 9: J SPI interface supply voltage select jumper PIN L+ PLUS on HMT77 C/Q Communication channel L P on HMT77..6 PP6 Microcontroller programming TM96. The TM96. ariant is not intended for customer programming, as programming will erase the preinstalled IOLink protocol stack and demo application. However, should the customer wish, the microcontroller may be reprogrammed with an alternative application via the probing pads on the PC. These probing pads are located on the underside of the PC, close to the microcontroller with approximately.7mm of separation. See Fig. 0. The pad assignments, along with their corresponding coordinates may be found in tables 8 & 9 respectively TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

12 Top side iew Locating Hole Ømm P P P TM96 GENIE Explorer TMEL R μc P y P P6 x Locating Hole Ømm Fig. 0: tmel microcontroller programming pads P RSTn μc reset P SCK SPI Clock P MOSI Master Out Slave In P MISO Master In Slave Out P CC μc power P6 μc ground Table 8: PP6 assignment Pin Name Pin Number PC Layer X_Coord. [mm] Y_Coord. [mm] RSTn P bottom.8. SCK P bottom.8.7 MOSI P bottom.8. MISO P bottom CC P bottom 6.. P6 bottom Table 9: PP6 coordinates..7 JP Interface connector to tmel R ISP programmer ariant 6 Fig. : JP tmel R ISP programming interface TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

13 MISO_uC Master Out Slave In CC Programmer REF SCK SPI Clock MOSI Master Out Slave In RESET Debug 6 Programmer Table 0: JP Pin assignment..8 JP Microcontroller debug connector ariant 6 Fig. : JP Microcontroller debug N/C Not connected CC Programmer REF N/C Not connected N/C Not connected RESET Debug 6 Programmer Table : JP Pin assignment. Other Connections ariant Location Size E ESD Ground Not Connected ottom Layer mm x mm Table : Other connections TM96.. Other Connections ariant.. J RWKE enable jumper Fig. : J RWKE enable jumper for SNS startup level PIN SS Slaveselect RWKE Connection to 0k RWKE pulldown Table : JP7 Pin assignment TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

14 Remove RWKE before programming over JTG ICE.. Ground pins Probe Probe P Oscilloscope P Oscilloscope P Oscilloscope P Oscilloscope Table pinstm96. Programming & Debug Sequence ariant. SPI access to R In order to program the microcontroller, please follow the programming procedure below. [] Remove RWKE enable jumper (J) [] Connect IOLink master via I M connector alternatively, supply the TM96. board via connector JP [] Connect microcontroller programming hardware [R JTGICE mkii], (JP) [] Program microcontroller (JP) [] Remove programming hardware (JP). Debug access to R In order to set the debug access to the R microcontroller via the reset pin, the appropriate fuses must be blown after programming of the R is complete. Further information on how to do this may be found in references ]. dedicated connector on the TM96., JP, provides direct access to the reset pin, along with the required programmer reference voltage. Note: when using the dedicated debug connector, JP, the programmer and the IOLink master may be connected simultaneously in this case. Transparent Mode The HMT77 supports a mode for transparent communication of URT frames. In this mode, the frames are received and transmitted from a URT peripheral in the microcontroller, and the function of the PHY device is reduced to that of a physical level converter. This mode is supported by dual use of the MOSI and MISO pins, maintaining the low overall pincount and a restricted use of microcontroller resources. For further information please refer to reference [].. Transparent Mode enable jumpers If transparent mode is requested, then resistors R and R6 should be present. Note: This feature is supported by the TM96. development module only TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

15 pplication Examples. TM96. IOLink Demonstrator & EMC Fig. Shows a TM96. module running the HMT IOLink Ministack and demo application on an tmel R microcontroller. TM96. ariant SNS CSNS PLUS LED LED IO Link Master CLK RWKE CQ SS MOSI CEMC MISO SCK P INT Fig. : HMT77 + tmel μc + HMT IOLink Ministack and demoapplication. TM96. IOLink sensor/actuator application development platform Fig. Illustrates how a customer hardware/software applications may be developed by introducing application specific sensors and/or further microcontrollers together with the HMT IOLink Ministack and demo application. TM96. ariant SNS LED LED CLK RWKE 6 SS IO Link Master pplication Specific Sensor/ctuator or Further Microcontroller CSNS PLUS CQ MOSI DIN CEMC MISO IN SCK INT RESET P TMEL R MKII Programmer Fig. : HMT77 + tmel μc + Customer protocol stack TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 /9

16 . TM96. IOLink stack development platform Fig. 6 Illustrates how an tmel microcontroller may be programmed with a customer specific IOLink protocol stack using an tmel R MKII programmer. TM96. ariant CSNS PLUS LED LED CLK RWKE 6 SS IO Link Master pplication Specific Sensor/ctuator or Further Microcontroller SNS CQ MOSI DIN CEMC MISO IN SCK INT RESET P TMEL R MKII Programmer Fig. 6: HMT77 + tmel μc + Customer protocol stack and application. TM96. Choice of Microcontroller Fig. 7 Illustrates how alternative tmel microcontrollers may be connected to the HMT77 by piggy back connector via the SPI interface socket. TM96. ariant Piggy ack oard SNS PLUS CSNS LED RWKE IO Link Master LED CLK CQ SS CEMC MOSI μc MISO SCK P INT Example Sensor Shown Fig. 7: HMT77 + External μc TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 6/9

17 Piggy back connector for other tmel microcontroller development.mm.mm..6mm mm.6mm.mm.mm.mm Fig. 8: Piggyback connector dimensioning 6 IOLink IEC6097 M Mounting.mm (Ø 0.mm).mm Max 0.mm mm Max 0.7mm (Ø 0.mm) 6mm 0.6mm (Ø 0.mm) Fig. 9: IEC6097 Mounting to TM96. GENIE Explorer I RINT TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 7/9

18 .mm.mm (Ø 0.mm) Max 0.mm mm Max 0.7mm (Ø 0.mm) 0.6mm (Ø 0.mm) 7mm Fig. 0: IEC6097 Mounting to TM96. GENIE Explorer I RINT 7 Technical Data 7. Remarks ll values refer to unless otherwise specified Operation of the module above the absolute maximum rating may lead to instantaneous device failure. Operation of the module between the operating rating and the absolute maximum rating leads to a reduced operating lifetime. 7. bsolute Maximum Ratings Parameter Commet Min. Typ. Max. Unit HMT77 Pin voltage PLUS 0 0 Pin voltage CQ 0 0 Pin voltage P Shorted on the board to tmel TMega8P & Ttiny88 Microcontrollers Pin voltage CC.8. Table : bsolute maximum ratings TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 8/9

19 7. Operating Parameters Min. Typ. Max. Unit HMT77 GENIE IOLink Device PHY PLUS supply voltage, SNS =., ISNS = 0m 0 PLUS supply voltage, SNS =, ISNS = 0m 7 0 locking capacitor on PLUS, CLK 00 nf Maximum load capacitor, CLOD_CQ EMC capacitor on CQ 00 nf. Max. Unit 70pF tmel Microcontroller Supply voltage (supplied externally), no IOLink master.8 Table 6: Operating parameters 7. Electrical Parameters Parameter Min. Typ. nalogue I/P [Potentiometer] Pin voltage SNS = Pin voltage SNS =.0 0. Current SNS =. 0 0 μ Current SNS =.0 00 μ Digital I/P [Push button switch] Pin voltage SNS =. 0. Pin voltage SNS =.0 0 Current SNS =. 700 μ Current SNS =.0.06 m Table 7: Electrical parameters 8 Microcontroller Part Numbers Tmega8P [MLF Package] TM96./ Project GENIE IOLINK PHY SPECIFICTION microelectronic G SISTM96.0 9/9