FreeBSD/RISC-V project

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1 FreeBSD/RISC-V project Ruslan Bukin University of Cambridge Computer Laboratory August 25, 2016 Approved for public release; distribution is unlimited. This research is sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contract FA C The views, opinions, and/or findings contained in this article/presentation are those of the author(s)/presenter(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. 1 / 29

2 RISC-V, 2010 David Patterson and Krste Asanović began searching for a common research ISA in 2010 x86 and ARM: too complex, IP issues Decided to develop their own ISA (Summer 2010) 2 / 29

3 RISC-V, 2014 Released frozen User Spec (v2.0) in May 2014 Fifth RISC ISA from Berkeley, so RISC-V Modular ISA: Simple base instruction set plus extensions Less than 50 hardware instructions in the base ISA Designed for extension/customization 3 / 29

4 RISC-V privileged v1.9 ISA RV32, RV64, RV128 (32 registers) extensions A atomic C compressed, 2-byte instruction size E embedded, 16 registers F Single precision FPU G General extensions, G is combination IMAFD M integer multiplication... 4 / 29

5 RISC-V assembly No conditional flags No branch delay slot Little-endian Branch offsets relative to PC 4-level pagetables 4 privilige levels 4-byte instruction length, 2-byte compressed 5 / 29

6 Some reasons to use FreeBSD/RISC-V Full stack BSD license (RISC-V, FreeBSD, LLVM/Clang) Technology transition Growing community, 42 Universities, 63 companies attended latest RISC-V workshop 90 RISC-V Foundation Members Bluespec, Cortus, Draper, IBM, Mellanox, Google, NVIDIA, HP, Microsemi, Microsoft, Oracle, Qualcomm, Western Digital, AMD, etc 6 / 29

7 FreeBSD/RISC-V: first 6 months Commiting to FreeBSD head Project started Kernel works Userland works Aug 2015 Oct 2015 Dec 2015 Jan / 29

8 FreeBSD/RISC-V: next 6 months Modules Berkeley Boot Loader SMP KDB DTrace ISA v1.9 update Feb 2016 Mar 2016 Apr 2016 May 2016 July 2016 Aug / 29

9 Early assembly code 1. Puts the hardware into a known state 2. Build a ring buffer for machine mode interrupts 3. Builds the initial pagetables 4. Enables the MMU 5. Branches to a virtual address (exiting from machine mode) 6. Calls into C code 9 / 29

10 Porting: kernel 1/2 Early HTIF console device EARLY PRINTF Atomic inline functions atomic add(..) atomic cmpset(..) atomic readandclear(..)... Providing physical memory regions for VM subsystem add physmap entry(0, 0x ,..); /* 128 MB at 0x0 */ VM (pmap) 10 / 29

11 Porting: kernel 2/2 Exceptions, context-switching, fork trampoline Timer, interrupt controller drivers HTIF block device driver (or use memory disk) copy data from/to userspace fubyte, subyte, fuword, suword, sueword, fueword copyin, copyout Trying to run /bin/sh (staticaly linked) Signals 11 / 29

12 FreeBSD/RISC-V: VM (pmap) Most sensitive machine-dependent part of VM subsystem Around 40 machine-dependent functions for managing page tables, address maps, TLBs pmap enter(pmap t pmap, vm offset t va, vm page t m, vm prot t prot, u int flags, int8 t psind) pmap extract(..) pmap remove(..) pmap invalidate range(..) pmap remove write(..) pmap protect(..) pmap activate(..) pmap release(..) pmap unwire(..) / 29

13 Porting: userspace jemalloc csu crt1.s, crtn.s, crti.s libc syscalls setjmp, longjmp set tp msun rtld-elf (runtime-linker) 13 / 29

14 Challenges Single page table base register Single tp (thread pointer) register Single sscratch register Single exceptions entry 14 / 29

15 FreeBSD/RISC-V: single page table base register problem Install kernel pagetables to each user pmap Update/delete on kernel pmap requires to update all the user pmaps 15 / 29

16 FreeBSD/RISC-V: single sscratch and tp registers Store PCPU on supervisor stack first Then store supervisor stack to sscratch register 16 / 29

17 FreeBSD/RISC-V: Exceptions entry problem ENTRY( c p u e x c e p t i o n s u p e r v i s o r ) [.. ] c a l l C LABEL ( d o t r a p s u p e r v i s o r ) [.. ] END( c p u e x c e p t i o n s u p e r v i s o r ) ENTRY( c p u e x c e p t i o n u s e r ) [.. ] c a l l C LABEL ( d o t r a p u s e r ) [.. ] END( c p u e x c e p t i o n u s e r ) 17 / 29

18 FreeBSD/RISC-V: Exceptions entry solution ENTRY( c p u e x c e p t i o n h a n d l e r ) c s r r w sp, s s c r a t c h, sp beqz sp, 1 f / User mode d e t e c t e d / c s r r w sp, s s c r a t c h, sp j c p u e x c e p t i o n h a n d l e r u s e r 1 : / S u p e r v i s o r mode d e t e c t e d / c s r r w sp, s s c r a t c h, sp j c p u e x c e p t i o n h a n d l e r s u p e r v i s o r END( c p u e x c e p t i o n h a n d l e r ) 18 / 29

19 Privilege levels User mode Supervisor mode Hypervisor mode Machine mode 19 / 29

20 Machine mode User mode (Apps) Supervisor mode (FreeBSD kernel) Machine mode (timer, console, HTIF) Collecting events 20 / 29

21 FreeBSD/RISC-V: Berkeley Boot Loader Original firmware from RISC-V project 21 / 29

22 FreeBSD/RISC-V: facts Based on ARMv8 port Patch to head 25k lines (200 new files) External GNU toolchain used (GCC 6.1) 6 months from scratch 22 / 29

23 Thanks People involved (Thanks!) Robert Watson (University of Cambridge) David Chisnall (University of Cambridge) Andrew Turner (ABT Systems) Arun Thomas (BAE Systems) Ed Maste (The FreeBSD Foundation) Yukishige Shibata (Sony Japan) Sean Bruno 23 / 29

24 Tools Table: Simulator/Emulator supported Wrotten in FreeBSD support Spike C++ Yes QEMU C Yes, v1.7 ISA RocketCore FPGA Chisel Yes lowrisc FPGA Chisel Not yet 24 / 29

25 RocketChip 6-stage single-issue in-order pipeline Chisel verilog bitfile Synthesized on ZedBoard also SiFive Freedom U500 Platform 25 / 29

26 lowrisc RocketChip fork University of Cambridge Chisel verilog bitfile Synthesized on Nexys4 26 / 29

27 FreeBSD/RISC-V: Current port status Everything works (tm) 27 / 29

28 TODO Ports/packages for toolchain, for tools, for BBL QEMU integration for ports (usermode QEMU) FPU (Floating Point Unit) LLVM/Clang support FDT/non-FDT GENERIC kernel 28 / 29

29 Questions Project home: 29 / 29

Porting FreeBSD to AArch64

Porting FreeBSD to AArch64 Andrew Turner andrew@fubar.geek.nz 12 June 2015 About me Source committer focusing on ARM Freelance Software Engineer Status of arm64 (AArch64) Support to boot in QEMU committed