Virtual Memory, Address Translation
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1 Memory Hierarchy Virtual Memory, Address Translation Slides contents from: Hennessy & Patterson, 5ed Appendix B and Chapter 2 David Wentzlaff, ELE 475 Computer Architecture MJT, High Performance Computing, NPTEL
2 Process/Program Address Space Byte Address 0 CODE DATA HEAP STACK
3 Process/Program Address Space Byte Address 0 CODE DATA HEAP Compiler assumes a linear address space Byte 0 to Byte STACK
4 Process/Program Address Space Byte Address 0 CODE DATA HEAP Compiler assumes a linear address space Byte 0 to Byte Virtual Address space STACK
5 Process/Program Address Space Byte Address 0 CODE DATA HEAP Compiler assumes a linear address space Byte 0 to Byte Virtual Address space The entire process data structure may not be present in MM at all times STACK
6 Paged Virtual Memory Byte 0 Virtual Address Space Virtual Page Number 0 Virtual Page Number 1 Virtual Page Number N
7 MAIN MEMORY MAIN MEMORY Paged Virtual Memory Page Number 0 Byte 0 Virtual Address Space Virtual Page Number 0 Virtual Page Number 1 Page Number 13 Virtual Page Number N
8 MAIN MEMORY MAIN MEMORY HARD DISK HARD DISK Paged Virtual Memory Page Number 0 Byte Virtual Address Space 0 Virtual Page Number 0 Virtual Page Number 1 Page Number 13 Page Number 1 Page Number 2 Virtual Page Number N Page Number N-1
9 MAIN MEMORY MAIN MEMORY HARD DISK HARD DISK Paged Virtual Memory Page Number 0 Byte Virtual Address Space 0 Virtual Page Number 0 Virtual Page Number 1 Physical Address Space Page Number 13 Page Number 1 Page Number 2 Virtual Page Number N Page Number N-1
10 The Memory Hierarchy Virtual Virtual Addresses Physical Physical Addresses Main memory Virtual memory Registers Cache Words (transferred explicitly via load/store) Lines (transferred automatically upon cache miss) Pages (transferred automatically upon page fault) Virtual Virtual Addresses Addresses
11 Address Translation Table VPN 0 VPN 1 Physical Page Numbers PPN 0 VPN N-1
12 Address Translation Table Virtual Address VPN PO VPN 0 VPN 1 Physical Page Numbers PPN 0 PPN VPN N-1
13 Address Translation Table Virtual Address VPN PO VPN 0 VPN 1 Physical Page Numbers PPN 0 PPN VPN N-1
14 Address Translation Table Virtual Address VPN PO VPN 0 VPN 1 Physical Page Numbers PPN 0 PPN PPN PO Physical Address VPN N-1
15 Virtual Memory
16 Virtual Memory
17 Virtual Memory
18 Address Translation Table Virtual Address VPN PO VPN 0 VPN 1 MAIN MAIN MEMORY Physical Page Numbers PPN PPN PO Physical Address VPN N
19 Address Translation Table Virtual Address VPN PO VPN 0 VPN 1 MAIN MAIN MEMORY Physical Page Numbers HARD DISK DISK Disk Addresses PPN Disk Address PPN PO Physical Address VPN N
20 Address Translation Table MAIN MAIN MEMORY HARD DISK DISK Virtual Address VPN PO VPN 0 VPN 1 Physical Page Numbers Disk Addresses V PPN Disk Address PPN PO Physical Address VPN N
21 Implementation of Address Translation Process always uses virtual addresses
22 Implementation of Address Translation Process always uses virtual addresses Memory Management Unit (MMU): part of CPU; hardware that does address translation
23 Implementation of Address Translation Process always uses virtual addresses Memory Management Unit (MMU): part of CPU; hardware that does address translation The page tables are (at best) present in the MM (OS virtual address space) One main memory reference per address translation!
24 Implementation of Address Translation Process always uses virtual addresses Memory Management Unit (MMU): part of CPU; hardware that does address translation To translate a virtual memory address, the MMU has to read the relevant page table entry out of memory
25 Implementation of Address Translation Process always uses virtual addresses Memory Management Unit (MMU): part of CPU; hardware that does address translation To translate a virtual memory address, the MMU has to read the relevant page table entry out of memory Caches recently used translations in a Translation Lookaside Buffer (Page Table Cache)
26 Caches and Address Translation CPU Virtual Address MMU Physical Address Cache
27 Caches and Address Translation Physically Addressed Cache CPU Virtual Address MMU Physical Address Cache
28 Caches and Address Translation Physically Addressed Cache CPU Virtual Address MMU Physical Address Cache CPU Virtual Address Cache Cache Miss MMU Physical Address Main Memory
29 Caches and Address Translation Physically Addressed Cache CPU Virtual Address MMU Physical Address Cache CPU Virtual Address Cache Cache Miss MMU Physical Address Main Memory Virtually Addressed Cache
30 Which is less preferable? Physical addressed cache Virtual addressed cache
31 Which is less preferable? Physical addressed cache Hit time higher (cache access after translation) Virtual addressed cache
32 Which is less preferable? Physical addressed cache Hit time higher (cache access after translation) Virtual addressed cache Data/instruction of different processes with same virtual address in cache at the same time
33 Which is less preferable? Physical addressed cache Hit time higher (cache access after translation) Virtual addressed cache Data/instruction of different processes with same virtual address in cache at the same time Flush cache on context switch, or Include Process id as part of each cache directory entry
34 Which is less preferable? Physical addressed cache Hit time higher (cache access after translation) Virtual addressed cache Data/instruction of different processes with same virtual address in cache at the same time Flush cache on context switch, or Include Process id as part of each cache directory entry Synonyms
35 Synonyms (Aliases) VA-T1 P1 t1 P2 t2 VA-T2 Shared L2 t1: t1: Read x X
36 Synonyms (Aliases) VA-T1 P1 t1 P2 t2 VA-T2 Shared L2 t1: t1: Read x X
37 Synonyms (Aliases) VA-T1 P1 t1 P2 t2 VA-T2 Shared L2 t1: t1: Read x t2: t2: Read x X
38 Synonyms (Aliases) VA-T1 P1 t1 P2 t2 VA-T2 Shared L2 t1: t1: Read x t2: t2: Read x X
39 Synonyms (Aliases) VA-T1 P1 t1 P2 t2 VA-T2 Shared L2 L2 uses virtual addresses X 2 copies of of one physical page in in the the cache!
40 Overlapped Operation MMU CPU Virtual Address Indexing using VA Cache Tag check using PA
41 Overlapped Operation MMU CPU Virtual Address Indexing using VA Cache Tag check using PA Virtually Indexed Physically Tagged Cache (VIPT) Other options: PIPT, PIPT, VIVT VIVT
42 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address
43 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address b address
44 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2
45 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2
46 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2 32B 32B Block
47 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2 W 1 W 2 7 W 8
48 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2 W 1 32B 32B W 2 Block 7 W 8 =? W 1 W 2 7 W 8
49 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2 W 1 32B 32B W 2 Block 7 W 8 No Cache Miss =? Yes Cache Hit W 1 W 2 7 W 8
50 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2 W 1 32B 32B W 2 Block 7 W 8 =? W 1 W 2 7 W 8 No Cache Miss Yes Cache Hit To Processor
51 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (10b) (10b) 3 Offset 2 Tag is not needed until the cache line has been read W 1 32B 32B W 2 Block 7 W 8 =? W 1 W 2 7 W 8 No Cache Miss Yes Cache Hit To Processor
52 64 b VM address VM Example
53 64 b VM address VM Example Virtual Page No (50) Page Offset (14)
54 64 b VM address VM Example Virtual Page No (50) Page Offset (14) Index (8) Offset (6)
55 64 b VM address VM Example Virtual Page No (50) Page Offset (14) Index (8) Offset (6) 26b 26b Cache Block
56 64 b VM address VM Example Virtual Page No (50) Page Offset (14) Index (8) Offset (6) 26b 26b Cache Block =? L1 Hit/Miss
57 64 b VM address VM Example Virtual Page No (50) Page Offset (14) Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? L1 Hit/Miss
58 64 b VM address VM Example Virtual Page No (50) Page Offset (14) Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? L1 Hit/Miss Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged)
59 64 b VM address VM Example Virtual Page No (50) Page Offset (14) (43) TLB Tag (7) TLB Index Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? L1 Hit/Miss Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged)
60 64 b VM address VM Example Virtual Page No (50) Page Offset (14) (43) TLB Tag (7) TLB Index Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? TLB Hit/ Page Fault =? L1 Hit/Miss Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged)
61 64 b VM address VM Example Virtual Page No (50) Page Offset (14) (43) TLB Tag (7) TLB Index Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? TLB Hit/ Page Fault Physical Address (40) =? L1 Hit/Miss Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged)
62 64 b VM address VM Example Virtual Page No (50) Page Offset (14) (43) TLB Tag (7) TLB Index Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? TLB Hit/ Page Fault Physical Address (40) =? L1 Hit/Miss To L2 Tag Index Offset Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged)
63 64 b VM address VM Example Virtual Page No (50) Page Offset (14) (43) TLB Tag (7) TLB Index Index (8) Offset (6) (26) Physical Address (Tag) (Tag) 26b 26b Cache Block =? TLB Hit/ Page Fault Physical Address (40) =? L1 Hit/Miss To L2 Tag Index Offset Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged) =? L2 L2 Cache Block
64 Translation Lookaside Buffer Cache of page table mappings entries long SA, FA, or DM Dirty flag use during page write back Ref used for LRU VPN (tag) PPN (data) Valid Ref Dirty Access Rights
65 Page Fault Virtual address generated by processor is not available in main memory
66 Page Fault Virtual address generated by processor is not available in main memory Detected on attempt to translate address Page Table entry is invalid
67 Page Fault Virtual address generated by processor is not available in main memory Detected on attempt to translate address Page Table entry is invalid Must be `handled by operating system Identify slot in main memory to be used Get page contents from disk Update page table entry
68 Page Fault Virtual address generated by processor is not available in main memory Detected on attempt to translate address Page Table entry is invalid Must be `handled by operating system Identify slot in main memory to be used Get page contents from disk Update page table entry Provide data to the processor
69 Abstraction: Virtual vs Physical Memory Programmer sees virtual memory Can assume the memory is infinite
70 Abstraction: Virtual vs Physical Memory Programmer sees virtual memory Can assume the memory is infinite Reality: Physical memory size is much smaller than what the programmer assumes
71 Abstraction: Virtual vs Physical Memory Programmer sees virtual memory Can assume the memory is infinite Reality: Physical memory size is much smaller than what the programmer assumes The system (system software + hardware, cooperatively) maps virtual memory addresses are to physical memory The system automatically manages the physical memory space transparently to the programmer
72 Abstraction: Virtual vs Physical Memory + Programmer does not need to know the physical size of memory nor manage it A small physical memory can appear as a huge one to the programmer Life is easier for the programmer -- More complex system software and architecture A classic example of the programmer/(micro)architect tradeoff
73 Virtual Memory What is the size of the Page Table? Where is it stored? What factors decide the size of a page? What are its side effects? Page size is constant/variable?
74 Extra
75 Fast Translation Address translation is on the critical path Paging 2 memory accesses! Address Translation Table + Data Translation Lookaside Buffer (TLB): Part of MMU that caches address translations
76 Size of a Page Page is the unit of Memory Management Too large vs Too small Page Offset field need not be translated What if the Page Offset field was 12 bits? (Page size = 4KB)
77 Paged Virtual Memory 48 bit Virtual Addresses, 40 bit Physical Addresses Page size = 16KB How many entries in a process's Page Translation Table? What is the size of the Page Translation Table?
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