Analyzing Designs with Quartus II Netlist Viewers

Transcription

1 19 QII51013 Subscribe This chapter describes how you can use the Quartus II Netlist Viewers to analyze and debug your designs. As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize, and constrain your design is critical. With today s advanced designs, several design engineers are involved in coding and synthesizing different design blocks, making it difficult to analyze and debug the design. The Quartus II RTL Viewer, State Machine Viewer, and Technology Map Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes. This chapter contains the following sections: When to Use the Netlist Viewers: Analyzing Design Problems on page 19-1 Introduction to the User Interface on page 19-5 Quartus II Design Flow with the Netlist Viewers on page 19-2 State Machine Viewer Overview on page 19-4 RTL Viewer Overview on page 19-3 Technology Map Viewer Overview on page 19-4 Filtering in the Schematic View on page Probing to a Source Design File and Other Quartus II Windows on page Probing to a Source Design File and Other Quartus II Windows on page Viewing a Timing Path on page When to Use the Netlist Viewers: Analyzing Design Problems You can use the Netlist Viewers to analyze and debug your design. This section provides simple examples of how to use the RTL Viewer, State Machine Viewer, and Technology Map Viewer to analyze problems encountered in the design process. Using the RTL Viewer is a good way to view your initial synthesis results to determine whether you have created the necessary logic, and that the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer and State Machine Viewer to check your design visually before simulation or All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

2 19-2 Quartus II Design Flow with the Netlist Viewers other verification processes. Catching design errors at this early stage of the design process can save you valuable time. If you see unexpected behavior during verification, use the RTL Viewer to trace through the netlist and ensure that the connections and logic in your design are as expected. You can also view state machine transitions and transition equations with the State Machine Viewer. Viewing your design helps you find and analyze the source of design problems. If your design looks correct in the RTL Viewer, you know to focus your analysis on later stages of the design process and investigate potential timing violations or issues in the verification flow itself. You can use the Technology Map Viewer to look at the results at the end of Analysis and Synthesis. If you have compiled your design through the Fitter stage, you can view your post-mapping netlist in the Technology Map Viewer (Post-Mapping) and your post-fitting netlist in the Technology Map Viewer. If you perform only Analysis and Synthesis, both the Netlist Viewers display the same post-mapping netlist. In addition, you can use the RTL Viewer or Technology Map Viewer to locate the source of a particular signal, which can help you debug your design. Use the navigation techniques described in this chapter to search easily through your design. You can trace back from a point of interest to find the source of the signal and ensure the connections are as expected. The Technology Map Viewer can help you locate post-synthesis nodes in your netlist and make assignments when optimizing your design. This functionality is useful when making a multicycle clock timing assignment between two registers in your design. Start at an I/O port and trace forward or backward through the design and through levels of hierarchy to find nodes of interest, or locate a specific register by visually inspecting the schematic. You can use the RTL Viewer, State Machine Viewer, and Technology Map Viewer in many other ways throughout the design, debug, and optimization stages. This chapter shows you how to use the various features of the Netlist Viewers to increase your productivity when analyzing a design. QII51013 Quartus II Design Flow with the Netlist Viewers on page 19-2 State Machine Viewer Overview on page 19-4 RTL Viewer Overview on page 19-3 Technology Map Viewer Overview on page 19-4 Quartus II Design Flow with the Netlist Viewers When you first open one of the Netlist Viewers after compiling the design, a preprocessor stage runs automatically before the Netlist Viewer opens. The preprocessor process box contains a link to the Settings > Compilation Process Settings page where you can turn on the Run Netlist Viewers preprocessing during compilation option. When this option is turned on, the preprocessing becomes part of the full project compilation flow and the Netlist Viewer opens immediately without displaying the preprocessing dialog.

3 QII51013 RTL Viewer Overview Figure 19-1: Quartus II Design Flow Including the RTL Viewer and Technology Map Viewer 19-3 This figure shows how Netlist Viewers fit into the basic Quartus II design flow. Before the Netlist Viewer can run the preprocessor stage, you must compile your design: To open the RTL Viewer or State Machine Viewer, first perform Analysis and Elaboration. To open the Technology Map Viewer (Post-Fitting) or the Technology Map Viewer (Post-Mapping), first perform Analysis and Synthesis. The Netlist Viewers display the results of the last successful compilation. Therefore, if you make a design change that causes an error during Analysis and Elaboration, you cannot view the netlist for the new design files, but you can still see the results from the last successfully compiled version of the design files. If you receive an error during compilation and you have not yet successfully run the appropriate compilation stage for your project, the Netlist Viewer cannot be displayed; in this case, the Quartus II software issues an error message when you try to open the Netlist Viewer. Note: If the Netlist Viewer is open when you start a new compilation, the Netlist Viewer closes automatically. You must open the Netlist Viewer again to view the new design netlist after compilation completes successfully. RTL Viewer Overview The Quartus II RTL Viewer allows you to view a register transfer level (RTL) graphical representation of your Quartus II integrated synthesis results or your third-party netlist file in the Quartus II software. You can view results after Analysis and Elaboration when your design uses any supported Quartus II design entry method, including Verilog HDL Design Files (.v), SystemVerilog Design Files (. sv), VHDL Design Files (. vhd), AHDL Text Design Files (.tdf), or schematic Block Design Files (.bdf). You can also view the hierarchy of atom primitives (such as device logic cells and I/O ports) when your design uses a synthesis tool to generate a Verilog Quartus Mapping File (.vqm) or Electronic Design Interchange Format (.edf) file.

4 19-4 State Machine Viewer Overview The Quartus II RTL Viewer displays a schematic view of the design netlist after Analysis and Elaboration or netlist extraction is performed by the Quartus II software, but before technology mapping and any synthesis or fitter optimizations. This view is not the final design structure because optimizations have not yet occurred. This view most closely represents your original source design. If you synthesized your design with the Quartus II integrated synthesis, this view shows how the Quartus II software interpreted your design files. If you use a third-party synthesis tool, this view shows the netlist written by your synthesis tool. When displaying your design, the RTL Viewer optimizes the netlist to maximize readability in the following ways: Logic with no fan-out (its outputs are unconnected) and logic with no fan-in (its inputs are unconnected) are removed from the display. Default connections such as V CC and GND are not shown. Pins, nets, wires, module ports, and certain logic are grouped into buses where appropriate. Constant bus connections are grouped. Values are displayed in hexadecimal format. NOT gates are converted to bubble inversion symbols in the schematic. Chains of equivalent combinational gates are merged into a single gate. For example, a 2-input AND gate feeding a 2-input AND gate is converted to a single 3-input AND gate. State machine logic is converted into a state diagram, state transition table, and state encoding table, which are displayed in the State Machine Viewer. To run the RTL Viewer for a Quartus II project, first analyze the design to generate an RTL netlist. To analyze the design and generate an RTL netlist, on the Processing menu, point to Start and click Start Analysis & Elaboration. You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Quartus II compilation flow. To run the RTL Viewer, on the Tools menu, point to Netlist Viewers and click RTL Viewer. QII51013 State Machine Viewer Overview The State Machine Viewer presents a high-level view of finite state machines in your design. The State Machine Viewer provides a graphical representation of the states and their related transitions, as well as a state transition table that displays the condition equation for each of the state transitions, and encoding information for each state. To run the State Machine Viewer, on the Tools menu, point to Netlist Viewers and click State Machine Viewer. To open the State Machine Viewer for a particular state machine, double-click the state machine instance in the RTL Viewer. State Machine Viewer on page Technology Map Viewer Overview The Quartus II Technology Map Viewer provides a technology-specific, graphical representation of your design after Analysis and Synthesis or after the Fitter has mapped your design into the target device.

5 QII51013 Introduction to the User Interface The Technology Map Viewer shows the hierarchy of atom primitives (such as device logic cells and I/O ports) in your design. For supported families, you can also view internal registers and look-up tables (LUTs) inside logic cells (LCELLs) and registers in I/O atom primitives. Where possible, the port names of each hierarchy are maintained throughout synthesis; however, port names might change or be removed from the design. For example, if a port is unconnected or driven by GND or V CC, it is removed during synthesis. When a port name changes, the port is assigned a related user logic name in the design or a generic port name such as IN1 or OUT1. You can view your Quartus II technology-mapped results after synthesis, fitting, or timing analysis. To run the Technology Map Viewer for a Quartus II project, on the Processing menu, point to Start and click Start Analysis & Synthesis to synthesize and map the design to the target technology. At this stage, the Technology Map Viewer shows the same post-mapping netlist as the Technology Map Viewer (Post-Mapping). You can also perform a full compilation, or any process that includes the synthesis stage in the compilation flow. If you have completed the Fitter stage, the Technology Map Viewer shows the changes made to your netlist by the Fitter, such as physical synthesis optimizations, while the Technology Map Viewer (Post-Mapping) shows the post-mapping netlist. If you have completed the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer. To open the Technology Map Viewer, on the Tools menu, point to Netlist Viewers and click Technology Map Viewer (Post-Fitting) or Technology Map Viewer (Post Mapping) View Contents of Nodes in the Schematic View on page Viewing a Timing Path on page Introduction to the User Interface The Netlist Viewer is a graphical user-interface for viewing and manipulating nodes and nets in the netlist. The RTL Viewer and Technology Map Viewer each consist of these main parts: The Netlist Navigator pane displays a representation of the project hierarchy. The Find pane allows you to find and locate specific design elements in the schematic view. The Properties pane displays the properties of the selected block when you select Properties from the shortcut menu. The schematic view displays a graphical representation of the internal structure of your design.

6 19-6 Introduction to the User Interface Figure 19-2: RTL Viewer QII51013 This figure shows the schematic view and the Netlist Navigator pane of the RTL Viewer. Netlist Viewers also contain a toolbar that provides tools to use in the schematic view. Use the Back and Forward buttons to switch between schematic views. You can go forward only if you have not made any changes to the view since going back. These commands do not undo an action, such as selecting a node. The Netlist Viewer caches up to ten actions including filtering, hierarchy navigation, netlist navigation, and zooming. The Refresh button restores the schematic view and optimizes the layout. Refresh does not reload the database if you change your design and recompile. The Find button opens and closes the Find pane. The Selection tool and Zoom tool buttons toggle between the selection mode and zoom mode. The Fit in Page button resets the schematic view to encompass the entire design. The Netlist Navigator button opens or closes the Netlist Navigator pane. The Color Settings button opens the Colors pane where you can customize the color scheme used in the Netlist Viewer. The Bird's Eye View opens the Bird's Eye View window which displays a miniature version of your design and allows you to navigate within the design and adjust the magnification in the schematic view quickly.

7 QII51013 Netlist Navigator Pane You can have only one RTL Viewer, one Technology Map Viewer (Post-Fitting), one Technology Map Viewer (Post-Mapping), and one State Machine Viewer window open at the same time, although each window can show multiple pages, each with multiple tabs. For example, you cannot have two RTL Viewer windows open at the same time Netlist Navigator Pane on page 19-7 Netlist Viewers Find Pane on page 19-9 Properties Pane on page 19-8 Netlist Navigator Pane The Netlist Navigator pane displays the entire netlist in a tree format based on the hierarchical levels of the design. In each level, similar elements are grouped into subcategories. You can use the Netlist Navigator pane to traverse through the design hierarchy to view the logic schematic for each level. You can also select an element in the Netlist Navigator to highlight in the schematic view. Note: Nodes inside atom primitives are not listed in the Netlist Navigator pane. For each module in the design hierarchy, the Netlist Navigator pane displays the applicable elements listed in the following table. Click the + icon to expand an element. Table 19-1: Netlist Navigator Pane Elements Elements Description Instances State Machines Primitives Modules or instances in the design that can be expanded to lower hierarchy levels. State machine instances in the design that can be viewed in the State Machine Viewer. Low-level nodes that cannot be expanded to any lower hierarchy level. These primitives include: Registers and gates that you can view in the RTL Viewer when using Quartus II integrated synthesis Logic cell atoms in the Technology Map Viewer or in the RTL Viewer when using a VQM or EDIF from third-party synthesis software In the Technology Map Viewer, you can view the internal implementation of certain atom primitives, but you cannot traverse into a lower-level of hierarchy.

8 19-8 Properties Pane QII51013 Elements Description Ports The I/O ports in the current level of hierarchy. Pins are device I/O pins when viewing the top hierarchy level and are I/O ports of the design when viewing the lower-levels. When a pin represents a bus or an array of pins, expand the pin entry in the list view to see individual pin names. Properties Pane You can view the properties of an instance or primitive using the Properties pane. Figure 19-3: Properties Pane To view the properties of an instance or primitive in the RTL Viewer or Technology Map Viewer, right-click the node and click Properties.

9 QII51013 Netlist Viewers Find Pane The Properties pane contains tabs with the following information about the selected node: The Fan-in tab displays the Input port and Fan-in Node. The Fan-out tab displays the Output port and Fan-out Node. The Parameters tab displays the Parameter Name and Values of an instance. The Ports tab displays the Port Name and Constant value (for example, V CC or GND). The possible value of a port are listed below Table 19-2: Possible Port Values Value Description V CC GND -- Unconnected The port is not connected and has V CC value (tied to V CC ) The port is not connected and has GND value (tied to GND) The port is connected and has value (other than V CC or GND) The port is not connected and has no value (hanging) If the selected node is an atom primitive, the Properties pane displays a schematic of the internal logic. Netlist Viewers Find Pane You can narrow the range of the search process by setting the following options in the Find pane: Click Browse in the Find pane to specify the hierarchy level of the search. In the Select Hierarchy Level dialog box, select the particular instance you want to search. Turn on the Include subentities option to include child hierarchies of the parent instance during the search. Click Options to open the Find Options dialog box. Turn on Instances, Nodes, Ports, or any combination of the three to further refine the parameters of the search. When you click the List button, a progress bar appears below the Find box. All results that match the criteria you set are listed in a table. When you double-click an item in the table, the related node is highlighted in red in the schematic view. Schematic View The schematic view is shown on the right side of the RTL Viewer and Technology Map Viewer. The schematic view contains a schematic representing the design logic in the netlist. This view is the main screen for viewing your gate-level netlist in the RTL Viewer and your technology-mapped netlist in the Technology Map Viewer. The RTL Viewer and Technology Map Viewer attempt to display schematic in a single page view by default. If the schematic crosses over to several pages, you can highlight a net and use connectors to trace the signal in a single page. Display Schematics in Multiple Tabbed View The RTL Viewer and Technology Map Viewer support multiple tabbed views.

10 19-10 Schematic Symbols With multiple tabbed view, schematics can be displayed in different tabs. Selection is independent between tabbed views, but selection in the tab in focus is synchronous with the Netlist Navigator pane. To create a new blank tab, click the New Tab button at the end of the tab row. You can now drag a node from the Netlist Navigator pane into the schematic view. You can right-click in a tab to see a shortcut menu where you can: Create a blank view with New Tab Create a Duplicate Tab of the tab in focus Choose to Cascade Tabs Choose totile Tabs Choose Close Tab to close the tab in focus Choose Close Other Tabs to close all tabs except the tab in focus QII51013 Schematic Symbols The symbols for nodes in the schematic represent elements of your design netlist. These elements include input and output ports, registers, logic gates, Altera primitives, high-level operators, and hierarchical instances The following table lists and describes the primitives and basic symbols that you can display in the schematic view of the RTL Viewer and Technology Map Viewer. Note: The logic gates and operator primitives appear only in the RTL Viewer. Logic in the Technology Map Viewer is represented by atom primitives, such as registers and LCELLs. Table 19-3: Symbols in the Schematic View Symbol Description I/O Ports RESET_N CLK_SEL[1:0] I/O Connectors [1,3] MEM_OE_N [1,15] OR, AND, XOR Gates always1 always0 C An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or bidirectional pin when viewing the top-level hierarchy. The symbol can also represent a bus. Only one wire is shown connected to the bidirectional symbol, representing the input and output paths. Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols appear on the right-most side of the schematic. An input or output connector, representing a net that comes from another page of the same hierarchy. To go to the page that contains the source or the destination, double-click on the connector to jump to the appropriate page. An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble symbol) on an input or output port indicates the port is inverted.

11 QII51013 Schematic Symbols Symbol Description MULTIPLEXER SEL[2:0] DATA[7:0] Mux5 OUT A multiplexer primitive with a selector port that selects between port 0 and port 1. A multiplexer with more than two inputs is displayed as an operator. BUFFER DATAIN OE LATCH latch PRE D Q ENA CLR OUT0 A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port. Other buffers without an enable port include LCELL, SOFT, CARRY, and GLOBAL. The NOT gate and EXP expander buffers use this symbol without an enable port and with an inverted output port. A latch/dff (data flipflop) primitive. A DFF has the same ports as a latch and a clock trigger. The other flipflop primitives are similar: DFFEA (data flipflop with enable and asynchronous load) primitive with additional ALOAD asynchronous load and ADATA data signals DFFEAS (data flipflop with enable and synchronous and asynchronous load), which has ASDATA as the secondary data port Atom Primitive F DATAA DATABCOMBOUT DATAC LOGIC_CELL_COMB (7F7F7F7F7F7F7F7F) Other Primitive CPU_D[10] PADIN PADIO Instance accel_in clk reset PADOUT BIDIR speed_ch:speed Ecrypted Instance streaming_cont IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 get_ticket An atom primitive. The symbol displays the atom name, the port names, and the atom type. The blue shading indicates an atom primitive for which you can view the internal details. Any primitive that does not fall into the previous categories. Primitives are low-level nodes that cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive or operator type, and its name. An instance in the design that does not correspond to a primitive or operator (a user-defined hierarchy block). The symbol displays the port name and the instance name. A user-defined encrypted instance in the design. The symbol displays the instance name. You cannot open the schematic for the lower-level hierarchy, because the source design is encrypted.

12 19-12 Schematic Symbols QII51013 State Machine Instance Symbol Description A finite state machine instance in the design. speed accel_in clk reset warning RAM my_20k_sdp CLK0 CLK1 CLR0 PORTAADDRSTALL PORTAADDR[8:0] PORTABYTEENMASK[3:0] PORTADATAIN[35:0] PORTAWE PORTBADDRSTALL PORTBADDR[8:0] PORTBRE Constant 8 h80 RAM PORTBDATAOUT[35:0] A synchronous memory instance with registered inputs and optionally registered outputs. The symbol shows the device family and the type of memory block. This figure shows a true dual-port memory block in a Stratix M-RAM block. A constant signal value that is highlighted in gray and displayed in hexadecimal format by default throughout the schematic. The following table lists and describes the symbol open only in the State Machine Viewer. Table 19-4: Symbol Available Only in the State Machine Viewer Symbol Description State Node The node representing a state in a finite state machine. State transitions are indicated with arcs between state nodes. The double circle border indicates the state connects to logic outside the state machine, and a single circle border indicates the state node does not feed outside logic. The following lists and describes the additional higher level operator symbols in the RTL Viewer schematic view. Table 19-5: Operator Symbols in the RTL Viewer Schematic View Symbol Description A[3:0] B[3:0] Add0 OUT[3:0] An adder operator: OUT = A + B A[0] B[0] Mult0 OUT[0] A multiplier operator: OUT = A B

13 QII51013 Select Items in the Schematic View Symbol Description A[0] B[0] Div0 OUT[0] A divider operator: OUT = A / B A[1:0] B[1:0] Equal3 OUT Equals A[0] COUNT[0] ShiftLeft0 OUT[0] A left shift operator: OUT = (A << COUNT) ShiftRight0 A[0] OUT[0] COUNT[0] A right shift operator: OUT = (A >> COUNT) A[0] B[0] Mod0 OUT[0] A modulo operator: OUT = (A%B) LessThan0 A[0] OUT B[0] A less than comparator: OUT = (A<:B:A>B) SEL[2:0] DATA[7:0] Mux5 OUT A multiplexer: OUT = DATA [SEL] sel range size The data range size is 2 SEL[2:0] DATA[2:0] Selector1 OUT A selector: A multiplexer with one-hot select input and more than two input signals IN[5:0] Decoder0 OUT[63:0] A binary number decoder: OUT = (binary_number (IN) == x) for x = 0 to x = 2 (n+1) - 1 Partition the Schematic into Pages on page Follow Nets Across Schematic Pages on page State Machine Viewer on page Select Items in the Schematic View To select an item in the schematic view, ensure that the Selection Tool is enabled in the Netlist Viewer toolbar (this tool is enabled by default). Click an item in the schematic view to highlight it in red. Select multiple items by pressing the Shift key while selecting with your mouse.

14 19-14 Shortcut Menu Commands in the Schematic View QII51013 Items selected in the schematic view are automatically selected in the Netlist Navigator pane. The folder then expands automatically if it is required to show the selected entry; however, the folder does not collapse automatically when you are not using or you have deselected the entries. When you select a hierarchy box, node, or port in the schematic view, the item is highlighted in red but none of the connecting nets are highlighted. When you select a net (wire or bus) in the schematic view, all connected nets are highlighted in red. Once you have selected an item, you can perform different actions on it based on the contents of the shortcut menu which appears when you right-click on your selection. Netlist Navigator Pane on page 19-7 Shortcut Menu Commands in the Schematic View When you right-click on an instance or primitive selected in the schematic view, the Netlist Viewer displays a shortcut menu. If the selected item is a node, you see the following options: Click Expand to Upper Hierarchy to displays the parent hierarchy of the node in focus. Click Copy ToolTip to copy the selected item name to the clipboard. This command does not work on nets. Click Hide Selection to remove the selected item from the schematic view. This does not delete the item from the design, merely masks it in the current view. Click Filtering to display a sub-menu with options for filtering your selection. When the selected item is a net, the shortcut menu displays the option to Unbundle Net. When you unbundle a net, all connected bus pins and ports are ungrouped and displayed. You can use this to trace bundled connections more easily. Filtering in the Schematic View Filtering allows you to filter out nodes and nets in your netlist to view only the logic elements of interest to you. You can filter your netlist by selecting hierarchy boxes, nodes, ports of a node, or states in a state machine that are part of the path you want to see. The following filter commands are available: Sources Displays the sources of the selection. Destinations Displays the destinations of the selection. Sources & Destinations displays the sources and destinations of the selection. Selected Nodes Displays only the selected nodes. Between Selected Nodes Displays nodes and connections in the path between the selected nodes. Bus Index Displays the sources or destinations for one or more indices of an output or input bus port. Filtering Options Displays the Filtering Options dialog box: Stop filtering at register Turning this option on directs the Netlist Viewer to filter out to the nearest register boundary. Filter across hierarchies Turning this option on directs the Netlist Viewer to filter across hierarchies. Maximum number of hierarchy levels Sets the maximium number of hierarchy levels displayed in the schematic view.

15 QII51013 View Contents of Nodes in the Schematic View To filter your netlist, select a hierarchy box, node, port, net, or state node, right-click in the window, point to Filter and click the appropriate filter command. The Netlist Viewer generates a new page showing the netlist that remains after filtering. When filtering in a state diagram in the State Machine Viewer, sources and destinations refer to the previous and next transition states or paths between transition states in the state diagram. The transition table and encoding table also reflect the filtering View Contents of Nodes in the Schematic View In the RTL Viewer and the Technology Map Viewer, you can view the contents of nodes to see their underlying implementation details. You can view LUTs, registers, and logic gates. You can also view the implementation of RAM and DSP blocks in certain devices in the RTL Viewer or Technology Map Viewer. In the Technology Map Viewer, you can view the contents of primitives to see their underlying implementation details. Figure 19-4: Wrapping and Unwrapping Objects If you can unwrap the contents of an instance, a plus symbol appears in the upper right corner of the object in the schematic view. To wrap the contents (and revert to the compact format), click the minus symbol in the upper right corner of the unwrapped instance. Note: In the schematic view, the internal details in an atom instance cannot be selected as individual nodes. Any mouse action on any of the internal details is treated as a mouse action on the atom instance. Figure 19-5: Nodes with Connections Outside the Hierarchy In some cases, the selected instance connects to something outside the visible level of the hierarchy in the schematic view. In this case, the net appears as a dotted line. Double-click on the dotted line to expand the view to display the destination of the connection.

16 19-16 Moving Nodes in the Schematic View Moving Nodes in the Schematic View You can drag and drop items in the schematic view to rearrange them. Figure 19-6: Drag and Drop Movement of Nodes QII51013 To move a node from one area of the netlist to another, select the node and hold down the Shift key. Legal placements appear as shaded areas within the hierarchy. Click to drop the selected node. Right-click and click on Refresh to restore the schematic view to its default arrangement. View LUT Representations in the Technology Map Viewer You can view different representations of a LUT by right-clicking the selected LUT and clicking Properties. You can view the LUT representations in the following three tabs in the Properties dialog box: The Schematic tab the equivalent gate representations of the LUT. The Truth Table tab the truth table representations. Properties Pane on page 19-8 Zoom Controls You can control the magnification of your schematic on the View menu, with the Zoom Tool in the toolbar, or with mouse gestures. By default, the Netlist Viewer displays most pages sized to fit in the window. If the schematic page is very large, the schematic is displayed at the minimum zoom level, and the view is centered on the first node. Click Zoom In to view the image at a larger size, and click Zoom Out to view the image (when the entire image is not displayed) at a smaller size. The Zoom command allows you to specify a magnification percentage (100% is considered the normal size for the schematic symbols).

17 QII51013 Navigating with the Bird's Eye View Within the schematic view, you can also use the following mouse gestures to zoom in on a specific section: zoom in Dragging a box around an area starting in the upper-left and dragging to the lower right zooms in on that area. zoom -0.5 Dragging a line from lower-left to upper-right zooms out 0.5 levels of magnification. zoom 0.5 Dragging a line from lower-right to upper-left zooms in 0.5 levels of magnification. zoom fit Dragging a line from upper-right to lower-left fits the schematic view in the page. You can also use the Zoom Tool on the Netlist Viewer toolbar to control magnification in the schematic view. When you select the Zoom Tool in the toolbar, clicking in the schematic zooms in and centers the view on the location you clicked. Right-click in the schematic to zoom out and center the view on the location you clicked. When you select the Zoom Tool, you can also zoom into a certain portion of the schematic by selecting a rectangular box area with your mouse cursor. The schematic is enlarged to show the selected area Filtering in the Schematic View on page Navigating with the Bird's Eye View To open the Bird s Eye View, on the View menu, click Bird s Eye View, or click on the Bird s Eye View icon in the toolbar. Viewing the entire schematic can be useful when debugging and tracing through a large netlist. The Quartus II software allows you to quickly navigate to a specific section of the schematic using the Bird s Eye View feature, which is available in the RTL Viewer and Technology Map Viewer. The Bird s Eye View shows the current area of interest. Select an area by clicking and dragging the indicator or right-clicking to form a rectangular box around an area. Click and drag the rectangular box to move around the schematic. Resize the rectangular box to zoom-in or zoom-out in the schematic view. Partition the Schematic into Pages For large design hierarchies, the RTL Viewer and Technology Map Viewer partition your netlist into multiple pages in the schematic view. When a hierarchy level is partitioned into multiple pages, the title bar for the schematic window indicates which page is displayed and how many total pages exist for this level of hierarchy. The schematic view displays this as Page <current page number> of <total number of pages>. Introduction to the User Interface on page 19-5 Follow Nets Across Schematic Pages Input and output connector symbols indicate nodes that connect across pages of the same hierarchy. Double-click a connector to trace the net to the next page of the hierarchy. Note: After you double-click to follow a connector port, the Netlist Viewer opens a new page, which centers the view on the particular source or destination net using the same zoom factor as the previous page. To trace a specific net to the new page of the hierarchy, Altera recommends that you first select the necessary net, which highlights it in red, before you double-click to traverse pages.

18 19-18 State Machine Viewer Schematic Symbols on page QII51013 State Machine Viewer The State Machine Viewer displays a graphical representation of the state machines in your design. You can open the State Machine Viewer in any of the following ways: On the Tools menu, point to Netlist Viewers and click State Machine Viewer. Double-click a state machine instance in the RTL Viewer Figure 19-7: The State Machine Viewer The following figure shows an example of the State Machine Viewer for a simple state machine and lists the components of the viewer. Back/Forward Display Toolbar Highlight Fan-in/Fan-out Toolbar View Toolbar Tool Toolbar State Machine Selection Box State Machine Viewer Toolbar State Diagram View State Encoding Table Tab State Transition Tab State Diagram View The state diagram view appears at the top of the State Machine Viewer. It contains a diagram of the states and state transitions.

19 QII51013 The nodes that represent each state are arranged horizontally in the state diagram view with the initial state (the state node that receives the reset signal) in the left-most position. Nodes that connect to logic outside of the state machine instance are represented by a double circle. The state transition is represented by an arc with an arrow pointing in the direction of the transition. When you select a node in the state diagram view, and turn on the Highlight Fan-in or Highlight Fan-out command from the View menu or the State Machine Viewer toolbar, the respective fan-in or fan-out transitions from the node are highlighted in red. Note: State Transition Table An encrypted block with a state machine displays encoding information in the state encoding table, but does not display a state transition diagram or table. State Transition Table The state transition table on the Transitions tab at the bottom of the State Machine Viewer displays the condition equation for each state transition. Each row in the table represents a transition (each arc in the state diagram view). The table has the following columns: Source State the name of the source state for the transition Destination State the name of the destination state for the transition Condition the condition equation that causes the transition from source state to destination state To see all of the transitions to and from each state name, click the appropriate column heading to sort on that column. The text in each column is left-aligned by default; to change the alignment and to make it easier to see the relevant part of the text, right-click the column and click Align Right. To revert to left alignment, click Align Left. Click in any cell in the table to select it. To select all cells, right-click in the cell and click Select All; or, on the Edit menu, click Select All. To copy selected cells to the clipboard, right-click the cells and click Copy Table; or, on the Edit menu, point to Copy and click Copy Table. You can paste the table into any text editor as tab-separated columns. State Encoding Table The state encoding table on the Encoding tab at the bottom of the State Machine Viewer displays encoding information for each state transition. To view state encoding information in the State Machine Viewer, you must synthesize your design with the Start Analysis & Synthesis command. If you have only elaborated your design with the Start Analysis & Elaboration command, the encoding information is not displayed. Select Items in the State Machine Viewer You can select and highlight each state node and transition in the State Machine Viewer. To select a state transition, click the arc that represents the transition. When you select a node or transition arc in the state diagram view, the matching state node or equation conditions in the state transition table are highlighted; conversely, when you select a state node or equation condition in the state transition table, the corresponding state node or transition arc is highlighted in the state diagram view.

20 19-20 Switch Between State Machines Switch Between State Machines QII51013 A design may contain multiple state machines. To choose which state machine to view, use the State Machine selection box located at the top of the State Machine Viewer. Click in the drop-down box and select the necessary state machine. Probing to a Source Design File and Other Quartus II Windows The RTL Viewer, Technology Map Viewer, and State Machine Viewer allow you to cross-probe to the source design file and to various other windows in the Quartus II software. You can select one or more hierarchy boxes, nodes, state nodes, or state transition arcs that interest you in the Netlist Viewer and locate the corresponding items in another applicable Quartus II software window. You can then view and make changes or assignments in the appropriate editor or floorplan. To locate an item from the Netlist Viewer in another window, right-click the items of interest in the schematic or state diagram, point to Locate, and click the appropriate command. The following commands are available: Locate in Assignment Editor Locate in Pin Planner Locate in Chip Planner Locate in Resource Property Editor Locate in Technology Map Viewer Locate in RTL Viewer Locate in Design File The options available for locating an item depend on the type of node and whether it exists after placement and routing. If a command is enabled in the menu, it is available for the selected node. You can use the Locate in Assignment Editor command for all nodes, but assignments might be ignored during placement and routing if they are applied to nodes that do not exist after synthesis. The Netlist Viewer automatically opens another window for the appropriate editor or floorplan and highlights the selected node or net in the newly opened window. You can switch back to the Netlist Viewer by selecting it in the Window menu or by closing, minimizing, or moving the new window. Probing to the Netlist Viewers from Other Quartus II Windows You can cross-probe to the RTL Viewer and Technology Map Viewer from other windows in the Quartus II software. You can select one or more nodes or nets in another window and locate them in one of the Netlist Viewers. You can locate nodes between the RTL Viewer, State Machine Viewer, and Technology Map Viewer, and you can locate nodes in the RTL Viewer and Technology Map Viewer from the following Quartus II software windows: Project Navigator Timing Closure Floorplan Chip Planner Resource Property Editor Node Finder Assignment Editor

21 QII51013 Messages Window Compilation Report TimeQuest Timing Analyzer (supports the Technology Map Viewer only) To locate elements in the Netlist Viewer from another Quartus II window, select the node or nodes in the appropriate window; for example, select an entity in the Entity list on the Hierarchy tab in the Project Navigator, or select nodes in the Timing Closure Floorplan, or select node names in the From or To column in the Assignment Editor. Next, right-click the selected object, point to Locate, and click Locate in RTL Viewer or Locate in Technology Map Viewer. After you click this command, the Netlist Viewer opens, or is brought to the foreground if the Netlist Viewer is open. Note: Viewing a Timing Path The first time the window opens after a compilation, the preprocessor stage runs before the Netlist Viewer opens. The Netlist Viewer shows the selected nodes and, if applicable, the connections between the nodes. The display is similar to what you see if you right-click the object, point to Filter, and click Selected Nodes using Filter across hierarchy. If the nodes cannot be found in the Netlist Viewer, a message box displays the message: Can t find requested location. Viewing a Timing Path You can cross-probe from a report panel in the TimeQuest Timing Analyzer to see a visual representation of a timing path. To take advantage of this feature, you must complete a full compilation of your design, including the timing analyzer stage. To see the timing results for your design, on the Processing menu, click Compilation Report. On the left side of the Compilation Report, select TimeQuest Timing Analyzer. When you select a detailed report, the timing information is listed in a table format on the right side of the Compilation Report; each row of the table represents a timing path in the design. You can also view timing paths in TimeQuest analyzer report panels. To view a particular timing path in the Technology Map Viewer or RTL Viewer, right-click the appropriate row in the table, point to Locate, and click Locate in Technology Map Viewer or Locate in RTL Viewer. To locate a path, on the Tasks pane, in the Custom Reports folder, double-click Report Timing. In the Report Timing dialog box, make necessary settings, and then click the Report Timing button. After the TimeQuest analyzer generates the report, right-click on the node in the table and select Locate Path. In the Technology Map Viewer, the schematic page displays the nodes along the timing path with a summary of the total delay. When you locate the timing path from the TimeQuest analyzer to the Technology Map Viewer, the interconnect and cell delay associated with each node is displayed on top of the schematic symbols. The total slack of the selected timing path is displayed in the Page Title section of the schematic. In the RTL Viewer, the schematic page displays the nodes in the paths between the source and destination registers with a summary of the total delay. The RTL Viewer netlist is based on an initial stage of synthesis, so the post-fitting nodes might not exist in the RTL Viewer netlist. Therefore, the internal delay numbers are not displayed in the RTL Viewer as they are in the Technology Map Viewer, and the timing path might not be displayed exactly as it appears in the timing analysis report. If multiple paths exist between the source and destination registers, the RTL Viewer might display more than just the timing path. There are also some cases in which the path cannot be displayed, such as paths through state machines, encrypted intellectual property (IP), or registers that are created during the fitting process. In cases where the timing path displayed in the RTL Viewer might not be the correct path, the compiler issues messages.

22 19-22 Document Revision History QII51013 Document Revision History Date Version Changes November 2013 November 2012 June 2012 November 2011 December 2010 July 2010 November 2009 March 2009 November Removed HardCopy device information. Reorganized and migrated to new template. Added support for new Netlist viewer. Added sections to support Global Net Routing feature. Removed survey link. Template update. Changed to new document template. Updated screenshots Updated chapter for the Quartus II software version 10.0, including major user interface changes Updated devices Minor text edits Chapter 13 was formerly Chapter 12 in version Updated Figure 13 2, Figure 13 3, Figure 13 4, Figure 13 14, and Figure Added Enable or Disable the Auto Hierarchy List on page Updated Find Command on page Changed page size to

23 QII51013 Document Revision History Date Version Changes May Added Arria GX support Updated operator symbols Updated information about the radial menu feature Updated zooming feature Updated information about probing from schematic to SignalTap II Analyzer Updated constant signal information Added.png and.gif to the list of supported image file formats Updated several figures and tables Added new sections Enabling and Disabling the Radial Menu, Changing the Time Interval, Changing the Constant Signal Value Formatting, Logic Clouds in the RTL Viewer, Logic Clouds in the Technology Map Viewer, Manually Group and Ungroup Logic Clouds, Customizing the Shortcut Commands Renamed several sections Removed section Customizing the Radial Menu Moved section Grouping Combinational Logic into Logic Clouds Updated document content based on the Quartus II software version 8.0 For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook Archive. Quartus II Handbook Archive