FPGA Block Modular Design Tutorial

Transcription

1 FPGA Block Modular Design Tutorial Introduction This tutorial describes the Block Modular Design (BMD) methodology and relative tools in isplever that assist distributed teams in collaborating on large FPGA designs. BMD can also be employed as part of a incremental design strategy that is especially effective when isolated changes to a design are required and there is a need to minimize the impact to other modules in the design. In this tutorial you will implement a small Verilog HDL design that will be partitioned between a top-level project and two sub-module projects. Throughout the tutorial you will act both in the role of the team leader and a team member. As the team leader, you will be responsible for the organization and management of the overall project and its files, area and resource budgeting, and final assembly of all modules in the top-level project. In the role of a team member, you will be responsible for preparing sub-modules for final assembly, that is, implementing each sub-module in its own child project to create physical design (.ncd) files. Team members must coordinate their sub-module designs based on the resources and timing objectives assigned by the team leader. Learning Objectives When you have completed this tutorial, you should be able to: Understand and follow the recommended team methodology for a team to collaborate on a large FPGA design. Partition and budget logic resources for multiple sub-modules. Define the relative location of the data paths between sub-modules. FPGA Block Modular Design Tutorial 1

2 Introduction Establish location and timing objectives for the top-level design. Archive and deploy sub-module projects. Implement a sub-module project. Perform incremental verification of the top-level project. Assemble and verify the top-level project. Time to Complete This Tutorial The time to complete this tutorial is about 45 minutes. System Requirements This section lists following software requirements, installation configurations, and software versions used in this tutorial. To run this tutorial successfully through completion, ensure that you have the following: Installed version of isplever software version 5.0 SP1 or higher. Installed isplever or isplever Starter software package with active licenses for Mentor Graphics Precision RTL Synthesis or Synplicity Synplify with Verilog HDL support. At least the OEM version of Mentor Graphics Precision or Synplicity s Synplify for synthesis of HDL source files. The body of the tutorial uses the Precision synthesis flow and alternate procedures for the Synplify synthesis flow are given in the appendix. You must use the tutorial design files in the bmd_tutor.zip file in the <install>\examples\tutorial folder after installation of isplever. This tutorial bmd_tutor.pdf file you are using is located in the <install>\ispcpld\tutorial directory path. This tutorial is PC-based; however, it can also be run on UNIX/Linux if you are familiar enough with the isplever interface on both platforms. About the Tutorial Design The tutorial design is a small data path design featuring one sub-module named (multreg16) with a multiplexer, multiply, with a registered output followed by another register stage named (rotate) that provides an optional rotate function. "Block Diagram of the Tutorial Design" on page 3 provides a high level block diagram of the system. FPGA Block Modular Design Tutorial 2

3 Introduction Figure 1: Block Diagram of the Tutorial Design FPGA Block Modular Design Tutorial 3

4 Introduction The Block Modular Design Methodology This section describes the Block Modular Design (BMD) methodology and its major process steps. The tutorial follows this approach, either taking you though each procedure step-by-step, or providing you with a finished input for illustrative purposes. The following is brief overview of each step: Step 1: Block Modular Design Entry In the first step, the top-level design is written in HDL and each sub-module is instantiated along with synthesis compiler directives to treat them as black-boxes. The team leader should take special consideration that each design module is a good sub-module candidate. The isplever online help provides guidelines on this topic. See the Block Modular Design Step Guide in the FPGA Flow Help system and the Block Modular Design Wizard Help system. In the tutorial, this step is already completed for you as these source Verilog HDL design files are supplied. Step 2: Block Modular Design Synthesis In the second step, the RTL of each sub-module is synthesized. This step can be performed in parallel with or before Step 3; however, the device resource utilization report generated by logic synthesis will help ease the team leader s task of budgeting area size and region for each sub-module in Step 3. The tutorial guides you through synthesis of the top-level and sub-module designs using Precision RTL Synthesis and Synplify. Synplify synthesis flow procedures are given in the appendix. Step 3: Top-Level Block Module Configuration During Step 3, the team leader budgets logic resources and the location of each sub-module on the target device floorplan. The size and location of each sub-module must accommodate the synthesized logic produced in Step 2. Timing constraints are initially defined in this step. Global device resources like I/Os and PLLs are also assigned at this point. The team leader should adhere to the configuration requirements described in isplever online help in the Top-Level Design Configuration Requirements topic in the Block Modular Design Step Guide in the FPGA Flow Help. In the tutorial, preferences are already set for you in a supplied preference file and can be viewed to illustrate how a designer takes existing area and resource considerations into account. Step 4: Block Module Implementation In Step 4, each sub-module is implemented by respective team members concurrently to produce physical design (.ncd) files to be merged next step, that is, final assembly. The toplevel or parent project lends its logical translated netlist (.ngo) file and logical preference (.lpf) file to guide this process. Each sub-module is implemented into.ncd files ready for final assembly with other sub-modules and the top-level project. Timing objectives established in Step 3 by the team leader are applied and often extended by the team member responsible for the sub-module. The tutorial guides you through this step. Step 5: Block Modular Design Assembly In the final assembly step, the top-level and all sub-modules are merged together into one design. The tutorial guides you through this step. FPGA Block Modular Design Tutorial 4

5 Introduction The Tutorial Process Flow This section describes the sequence of processors and major data files you will apply during the tutorial tasks. The tutorial tasks lead you through the typical routine within the isplever design environment to follow the BMD methodology described earlier. Figure 2: Top-Level Process Flow FPGA Block Modular Design Tutorial 5

6 Introduction Figure 3: Sub-Module Process Flow Before You Begin Before beginning, you must set up the tutorial design files to be used with this tutorial. To work with this tutorial, please take the following steps: 1. Go to the <install_dir>\examples\tutorial\bmd_tutor directory and create a directory called isplever to work with this tutorial. Please note that you can set up your tutorial directory anywhere you wish; however, this tutorial will instruct you to this file path in procedures. All files in this isplever folder will be consistent in a relative manner to whatever file path you use to run this tutorial, that is, all recursive directories and files should be the same. 2. In the <install_dir>\examples\tutorial\bmd_tutor folder, open the bmd_tutor.zip file and extract the files to the same directory path or to the bmd_tutor folder. Restoring the Tutorial Installation After running through this tutorial one time, you may want to repeat it or allow someone else to run it locally or over the network. To restore the original state of the tutorial installation, remove contents of the isplever sub-directory you created in the bmd_tutor directory. The original source files for this tutorial will remain undisturbed in the bmd_tutor.zip file in the source directory in.\examples\tutorial\bmd_tutor. FPGA Block Modular Design Tutorial 6

7 Task 1: Top-Level Module Design Entry and Synthesis Task 1: Top-Level Module Design Entry and Synthesis In this task, you act in the role as the team leader and examine a pre-defined top-level tutorial design using Synplicity Synplify Pro for Lattice. The top-level design is written in Verilog HDL and each sub-module is instantiated along with synthesis compiler directives to treat each as a black-box. Black boxes are passed into the EDIF netlist as-is with no internal logic defined. "Block Diagram of the Tutorial Design" on page 3 illustrates the top-level organization and sub-module interconnect between sub-modules multreg16 and rotate. Top-Level Synthesis with Synplify Pro for Lattice Use the following procedure to synthesize the design using Synplify Pro for Lattice. To create a Synplify project, inspect the top-level design, and synthesize it to EDIF: 1. From the Start menu, select Programs > Lattice Semiconductor > Accessories > Synplify Pro for Lattice. The Synplicity Synplify Pro for Lattice interface appears. 2. Select File > New Project. A default project Temp.prj appears and defaults to save to some location on your local hard disk. 3. On the button bar on the left of the Project View, click the Add File button. The Select Files to Add to Project dialog appears. 4. Browse to the..\examples\tutorial\bmd_tutor folder, control-click to select both the veriloghdsn.v and LatticeEC_66MHz_PLL.v files, click <- Add, and then click OK. FPGA Block Modular Design Tutorial 7

8 Task 1: Top-Level Module Design Entry and Synthesis 5. In the Project View, expand the project hierarchy and drag and drop the veriloghdsn.vhd file to the bottom of the Verilog folder file list. Note that your project device could show a previous implementation. Ignore this. We will specify our target device later in the procedure. 6. Create a folder...\examples\tutorial\bmd_tutor\synplify\veriloghdsn. 7. In Synplify Pro, select File > Save. The Save As dialog appears. 8. Browse to the...\examples\tutorial\bmd_tutor\synplify\veriloghdsn folder, specify veriloghdsn.prj, and click Save. FPGA Block Modular Design Tutorial 8

9 Task 1: Top-Level Module Design Entry and Synthesis 9. Click on the Implementation Options button. An Implementation dialog for the veriloghdsn project rev_1 appears. 10. In the default Device tab, select the following settings: Technology: LatticeECP Part: LFECP6E Speed Grade: -4 Package: T144I 11. Click the Implementation Results tab in the dialog and select the following: Results Directory:...\examples\tutorial\bmd_tutor\isplever\veriloghdsn Result File Name: veriloghdsn.edn 12. Click OK. 13. In the Project View, expand your project hierarchy under the Verilog tab and double click on veriloghdsn.v to open the file. The top-level Verilog module appears in the Text Editor. 14. Page down to the module declarations for multreg16 and rotate. Make note of the Synplify compiler directives added to the module declarations of multreg16 and rotate. The syn_black_box command directs the compiler to pass the module instance untouched into the EDIF netlist. module multreg16(q, dataa, datab, datac, sel, clk, rst) /* synthesis syn_black_box */; output [15:0] q; input [7:0] dataa, datab, datac; input clk /* synthesis syn_isclock = 1 */; input sel, rst; reg [15:0] q; endmodule FPGA Block Modular Design Tutorial 9

10 Task 1: Top-Level Module Design Entry and Synthesis module rotate(q, data, clk, r_l, rst) /* synthesis syn_black_box */; output [15:0] q; input [15:0] data; input clk /* synthesis syn_isclock = 1 */; input r_l, rst; 15. Click the Run button. Synplify creates an output EDIF netlist (veriloghdsn.edn) for the implementation. 16. In the Implementation Results View, double click the veriloghdsn.edn file. The netlist opens in the text editor. FPGA Block Modular Design Tutorial 10

11 Task 2: Sub-Module Design Entry and Synthesis Task 2: Sub-Module Design Entry and Synthesis In this task, you will act in the role of a team member responsible for the design of a sub-module. You will synthesize the tutorial HDL source files for each sub-module. In this scenario you define and optionally debug sub-module logic that is independent of the top-level design or other sub-modules. After synthesis you will use the utilization report of the compiler to make a rough estimate of the FPGA resources that will be required to accommodate the sub-module. This information will help the team leader make a better choice about location and size of the sub-module on the device floorplan. Sub-Module Synthesis of multreg16 with Synplify Pro Use the following procedure to synthesize the design using Synplify. To create a Synplify project for the sub-module and synthesize it to EDIF: 1. If Synplify is not already running, from the Start menu, select Programs > Lattice Semiconductor > Accessories > Synplify Pro for Lattice. The Synplicity Synplify for Lattice interface appears. 2. Select File > New Project. 3. A default project proj.temp appears. 4. Click the Add File button. The Select Files to Add to Project dialog appears. 5. Browse to the.\bmd_tutor folder, select multreg16.v, click <- Add, and then click OK. 6. Create a folder...\examples\tutorial\bmd_tutor\synplify\multreg Select File > Save. The Save As dialog appears. 8. Browse to the...\examples\tutorial\bmd_tutor\synplify\multreg16 folder, specify multreg16.prj, and click Save. 9. Click on the Implementation Options button. An Implementation dialog for the multreg16 project rev_1 appears. 10. In the default Device tab and select the following: Technology: LatticeECP Part: LFECP6E Speed Grade: -4 Package: T144I Device Mapping Options: Disable I/O Insertion (Enable) 11. Click the Implementation Results tab in the dialog and select the following: Results Directory:...\examples\tutorial\bmd_tutor\Synplify\multreg16 Result File Name: multreg16.edn 12. Click OK. 13. Select the multreg16.prj project in the Project View. FPGA Block Modular Design Tutorial 11

12 Task 2: Sub-Module Design Entry and Synthesis 14. Click the Run button. Synplify Pro creates an output EDIF netlist (multreg16.edn) for the implementation. 15. Double click the log file multreg16.srr. Note the Resource Usage Report section of the log file. This estimate of physical FPGA resources required to accommodate the sub-module is helpful information for the lead system engineer when the entire design is budgeted. In this example the following resources will be required: Register bits: 0 of 6144 => 0 slices required for register logic. DSP primitives: 1 => 1 sysdsp block required for the MULT9X9 inferred by the multiply operator and registered output. ORCALUT4: 8 => 4 slices (or 1 PFU) required to accommodate the multiplexer logic Resource Usage Report Part: lfecp6e-4 Register bits: 0 of 6144 (0%) I/O cells: 0 DSP primitives: 1 Details: MULT9X9: 1 ORCALUT4: 8 VHI: 1 VLO: Select File > Save. Sub-Module Synthesis rotate with Synplify Pro Use the following procedure to synthesize the rotate sub-module design using Synplify. 1. Repeat steps 2 through 14 from the procedure above using the rotate.v source file. Use the same folder naming convention as you did for multreg Double-click the log file rotate.srr. The following resources will be required: Register bits: 16 of 6144 => 8 slices (or 2 PFUs) required for register logic. ORCALUT4: 16 => 8 slices (or 2 PFUs) required for other logic Resource Usage Report Part: lfecp6e-4 Register bits: 16 of 6144 (0%) I/O cells: 0 Details: FD1S3DX: 16 ORCALUT4: 16 VHI: 1 FPGA Block Modular Design Tutorial 12

13 Task 2: Sub-Module Design Entry and Synthesis VLO: 1 3. Select the rotate.prj window. 4. Select File > Save. 5. Select File > Exit. 6. Go to "Task 3: Top-Level Block Module Configuration" on page 14. FPGA Block Modular Design Tutorial 13

14 Task 3: Top-Level Block Module Configuration Task 3: Top-Level Block Module Configuration In this task, you will act again as the team leader and budget logic resources for each sub-module, assign I/Os, and define top-level timing objectives. To get started, you will first set up your BMD parent project which contains your top-level design and import all of your sub-modules into it. In reality, you are reserving area on the chip for the sub-modules prior to actually incorporating the sub-module logic into the final design. Sub-module area resources are defined using the isplever Block Modular Design Wizard (BMD Wizard) application. In the BMD Wizard, the Device Region view provides an abstraction of the device floorplan to help you interactively locate and assign specific physical resources for each submodule. The primary outputs of the BMD Wizard are MODULE preferences stored as part of the top-level preference file and a sub-module project file (.syn) for the isplever Project Navigator. MODULE preferences specify allowable regions for placement of sub-module resources. Figure 4: Simplified LatticeECP-DSP Block diagram and Sub-modules "Simplified LatticeECP-DSP Block diagram and Sub-modules" on page 14 shows the simplified block diagram of the ECP6 device s hardware resources illustrating approximately where the two sub-modules will be located. The following are examples of key design characteristics that will influence module size and location: Position of top-level signal and logic contained in PICs. In the tutorial design, external ports: a, b, and c occupy PICs of the lefthand side. FPGA Block Modular Design Tutorial 14

15 Task 3: Top-Level Block Module Configuration Sub-module data flow. In the tutorial design, the reg_out bus between multreg16 and rotate implies where they should be in proximity. Logic resources required. In the tutorial, by reviewing the device resources required for each sub-module during "Task 2: Sub-Module Design Entry and Synthesis" on page 11, it was discovered that each submodule requires a small number of slice resources. We know that multreg16 must be positioned so that a sysdsp block resource is available for the 9X9 MULT component inferred during logic synthesis. Defining Sub-Modules and Budgeting Logic Resources In the following procedures you will define the sub-module projects and allocate specific physical resources to for each using the BMD Wizard. You must, however, first create your top-level project. Creating your top-level project In this step you will create the top-level project for your block modular design. This is the parent project that will be used to merge the other child project sub-module designs into one merged design. Note that you should have already set up the..\bmd_tutor\isplever folder as described in the section, "Before You Begin" on page 6. To create a project for the top-level design: 1. Start the isplever system, if it is not already running. 2. In Project Navigator, select File > New Project to open the Project Wizard dialog box. Note that if the Create New Project dialog appears instead of the Project Wizard, select Options > Environment to change the default setting. In the Advanced tab, the Use Project Wizard to Create New Design option should be checked. 3. In the Project Wizard dialog box, select or specify the following: Project Name: veriloghdsn Location:...\examples\tutorial\bmd_tutor\ispLEVER Design Entry Type: EDIF Synthesis Tools: Synplify Click Next. FPGA Block Modular Design Tutorial 15

16 Task 3: Top-Level Block Module Configuration 4. In the Project Wizard Select Device dialog box, select the following options and click Next: Family: LatticeECP Device: LFECP6E Speed Grade: -4 Package Type: TQFP144 Operating Conditions: Industrial FPGA Block Modular Design Tutorial 16

17 Task 3: Top-Level Block Module Configuration 5. In the Project Wizard Add Source dialog box, select Add Source. 6. In the Import File (EDIF) dialog, browse to the veriloghdsn_impl_1 directory in..\bmd_tutor\synplify\veriloghdsn\rev_1 and select veriloghdsn.edn, click Open. 7. In the Project Wizard Project Information dialog box, click Finish. The new EDIF-based project is created with an EDIF netlist of the tutorial design added to the source file list in the Sources window. Floorplanning and project setup in the BMD Wizard In the next procedure you will first convert the EDIF netlist into a logical database (.ngd) file in Project Navigator and then use the Block Modular Wizard to budget area placement of sub-modules on the device floorplan. Figure 2, "Top-Level Process Flow" on page 5 illustrates the data flow details. To create a logical netlist reader file (.ngo) and launch the BMD Wizard. 1. Select the top-level veriloghdsn.edn file in the Sources window. This is named verilog_hierarchical_design. 2. In the Processes window, double-click Compile EDIF File process for the current source list. FPGA Block Modular Design Tutorial 17

18 Task 3: Top-Level Block Module Configuration The Report Viewer will automatically open the automake.log file showing all the process commands and indicating it has completed successfully. 3. In the Report Viewer, click File > Exit to close the automake.log. 4. In Project Navigator, select Tools > Block Modular Design Wizard or click the BMD Wizard icon in the toolbar. The BMD Wizard appears. 5. Look in the Device Region view on the right. In the Device Region view, an abstract, top-level representation of the ECP6 device floorplan appears. The gray shaded boxes indicate PFUs, a row of blue colored boxes indicate sysdsp blocks, and the second row of rectangular boxes indicate sysmem EBR memory blocks. 6. Click the Zoom In button on the toolbar to increase the view of the ECP6 floorplan. 7. Place your cursor over the first shaded box top-left in the top left. The floorplan coordinate, R2C2D, appears in a yellow box to the upper right of the Device Region view. FPGA Block Modular Design Tutorial 18

19 Task 3: Top-Level Block Module Configuration Experiment with this dynamic reporting by moving the cursor over the floorplan. The anchor point for module definitions must be located at a slice coordinate. 8. Select Settings > Sub Module. The Sub Module Settings dialog box appears. 9. In the Sub Module Settings dialog, click Create. The Create Module dialog box appears. 10. In the Create Module dialog, specify the following and click OK: Module Name: multreg16 Display Color: (As Desired) Site: Row: 2 Site: Column: 2 BBox: Height: 9 BBox: Width: 8 FPGA Block Modular Design Tutorial 19

20 Task 3: Top-Level Block Module Configuration Note: If a Block Modular Design Wizard dialog box appears, select Yes. A colored region named multreg16 appears in the upper left area of the floorplan. 11. In the Sub Module Settings dialog, click Create. The Create Module dialog box appears. 12. In the Create Module dialog, specify the following and click OK: Module Name: rotate Display Color: As Desired Site: Row: 2 Site: Column: 10 BBox: Height: 8 BBox: Width: 6 FPGA Block Modular Design Tutorial 20

21 Task 3: Top-Level Block Module Configuration Note: If a Block Modular Design Wizard dialog box appears, select Yes. A colored region named rotate appears in the upper left area of the floorplan. 13. In the Sub Module Settings dialog, click Close. 14. Select the multreg16 source file icon in the Projects window. You can also click on the sub-module multreg16 region in the Device Region view. The module definition and resources included within its dimensions is reported in the Message Board tab: Module "multreg16": Site [Row 2, Column 2]; BBox [Height 9, Width 8] => 64 PFUs, 256 Slices In the earlier tasks you examined the physical resource estimates reported by logic synthesis. The two sub-modules defined here will provide plenty of logic to hold the synthesized logic, and in the case of the multreg16 sub-module, the design requires a sysdsp block to accommodate the MULT9X Click the DRC Check button in the toolbar. The BMD Wizard confirms the basic module definition rules pass and reports no errors. 16. In the popup dialog, click OK at the BMD Wizard prompt. FPGA Block Modular Design Tutorial 21

22 Task 3: Top-Level Block Module Configuration 17. Click the Save Module Region button in the toolbar. This will save those MODULE definitions to the top-level preference (.lpf) file. 18. Select File > Exit. The BMD Wizard creates new project resources and an updated top-level preference file. The following new isplever project files and subdirectories are created: isplever project file:...\bmd_tutor\isplever\veriloghdsn\multreg16\multreg16.syn isplever project file:...\bmd_tutor\isplever\veriloghdsn\rotate\rotate.syn Top-level preference file: veriloghdsn.lpf 19. In the Sources window in Project Navigator, select the LFECP6E-4T144I device icon. On the right, the Processes window display will show the implementation flow. Take notice of following two processes particular to the Block Modular Design flow: Build Toplevel Database Assemble Database 20. In the Processes window under the Build Toplevel Database process, double-click Edit Preferences (ASCII). The top-level preference file appears in the Text Editor. Note the module preferences created by the BMD Wizard in the logical preference (.lpf) file: INDUSTRIAL ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; MODULE "multreg16" BBOX 9 8 SITE "R2C2D" ; MODULE "rotate" BBOX 8 6 SITE "R2C10D" ; Note Please note that error messages may appear from NGDBUILD in the automake.log file reporting missing sub-module.ncd files. These messages can be safely ignored. For example, the errors may appear as follows: ERROR - ngdbuild: Failed to open file 'multreg16/multreg16.ncd' ERROR - ngdbuild: Failed to open file 'rotate/rotate.ncd' 21. Select File > Exit to close the Text Editor. 22. If open, choose File > Exit to close the Report Viewer. Importing top-level location and timing constraints In the next procedure you will import predefined location and timing preferences for the top-level design. Normally, you would use the Design Planner (Pre-Map) process in Project Navigator to establish these constraints. We have already set these constraints for you, so you only need to import the tutorial preference file into your project. FPGA Block Modular Design Tutorial 22

23 Task 3: Top-Level Block Module Configuration To import location and timing preferences: 1. Select Source > Import Constraint/Preference File. The Import Preference File dialog box appears. 2. Navigate to the.\bmd_tutor directory where you extracted your tutorial zip file, select veriloghdsn.lpf and click Open. 3. In the Import Constraints dialog box, click OK. The software will automatically create a backup preference file with the.bak extension. 4. Select No in the dialog that prompts you to reset your project status. You have completed this task. 5. Save your project and close isplever. Note The Block Modular Design approach was designed for a distributed team environment. After the Top-level Block Module Configuration step, you will typically use the Project Navigator Archive Project feature to create a ZIP archive of each sub-module project and related resources in preparation to deploy them to team members. In the tutorial procedures you will implement and assemble the entire design on the same system. Go to "Task 4: Block Module Implementation" on page 24. FPGA Block Modular Design Tutorial 23

24 Task 4: Block Module Implementation Task 4: Block Module Implementation In this task, you will act in the team member role and implement the two submodules, multreg16 and rotate, as shown in Figure 1, "Block Diagram of the Tutorial Design" on page 3. The output of this task is a physical database (NCD) file for each sub-module to be used in the final assembly stage in the top-level project. Be aware that in a real design scenario each one of these sub-module projects can be implemented in parallel by team members. See Figure 3, "Sub-Module Process Flow" on page 6 for details of the sub-module process flow. To implement the sub-module projects: 1. Start the isplever system, if it is not already running. Notice that you will see the multreg16 and rotate projects you created earlier in the BMD Wizard in the Project Navigator Sources window and the top-level design indicates that its database been assembled to this point. 2. In Project Navigator s Sources in Project window, double click the multreg16.syn file beneath the parent, top-level veriloghdsn.syn project. This will bring up the multreg16 sub-module project in another Project Navigator window. 3. Select Source > Import. The Import Source dialog box appears. 4. In the file path \bmd_tutor\synplify\multreg16\rev_1 select the multreg16.edn file and click Open. 5. In the Processes window under Map Design, double-click Map Report (multreg16.mrp). The design mapper runs and the Map Report (.mrp) file appears. FPGA Block Modular Design Tutorial 24

25 Task 4: Block Module Implementation Take note of the sub-module resource utilization shown in Map Report file. Unlike a typical MRP file, this sub-module Map report reflects design resources allocated by the team leader in "Task 3: Top-Level Block Module Configuration" on page 14. For example, the number of module SLICEs reflects the number of slices used within the sub-module border for multreg16 defined earlier in the BMD Wizard. From the Map Report file: Module Design Summary Number of SLICEs: 8 out of 256 (3%) SLICEs(logic/ROM): 8 out of 192 (4%) SLICEs(logic/ROM/RAM): 0 out of 64 (0%) As RAM: 0 As Logic/ROM: 0 Number of PFU registers: 0 Number of logic LUT4s: 8 Number of distributed RAM: 0 (0 LUT4s) Number of ripple logic: 0 (0 LUT4s) Number of shift registers: 0 Total number of LUT4s: 8 Number of block RAMs: 0 out of 0 Number Of Mapped DSP Components: MULT36X36 0 MULT18X18 0 MULT18X18MAC 0 MULT18X18ADDSUB 0 MULT18X18ADDSUBSUM 0 MULT9X9 1 MULT9X9MAC 0 MULT9X9ADDSUB 0 MULT9X9ADDSUBSUM Number of used DSP Sites: 1 out of 8 (12 %) Complete Design Summary Number of registers: 0 PFU registers: 0 PIO registers: 0 Number of SLICEs: 8 out of 3072 (0%) SLICEs(logic/ROM): 8 out of 2304 (0%) SLICEs(logic/ROM/RAM): 0 out of 768 (0%) As RAM: 0 As Logic/ROM: 0 Number of logic LUT4s: 8 Number of distributed RAM: 0 (0 LUT4s) Number of ripple logic: 0 (0 LUT4s) Number of shift registers: 0 Total number of LUT4s: 8 Number of PIO sites used: 27 out of 97 (28%) 6. Click File > Exit to close the Report Viewer. FPGA Block Modular Design Tutorial 25

26 Task 4: Block Module Implementation 7. In the Processes window, double-click Place & Route Design. The Project Navigator implements the sub-module project with the constraints you imported. Note Note here that the Place & Route Design process may not appear as though it has successfully completed routing. Please check the automake log file window to ensure it has so you can proceed. Also, it is likely that this process will not complete without some warning or error messages causing the yellow exclamation point symbol to appear next to the process in the Processes window instead of the expected green check mark. Please be aware that there are many false warning and error messages associated with this process flow that can be safely ignored. Please refer to the Block Modular Design Troubleshooting topic in the Block Modular Design Step Guide in the FPGA Flow Help for details. 8. Click File>Save to save your sub-module design project. 9. In Project Navigator s Sources in Project window, double click on the veriloghdsn top-level project icon. Your top-level project will open. 10. In Project Navigator s Sources in Project window, double click the rotate.syn file beneath the parent, top-level veriloghdsn.syn project to open it. 11. Repeat steps 2 through 7 for the rotate.syn sub-module project. Note The Block Modular Design approach was designed for a distributed team environment. After the Block Module Implementation step, you will typically use the Project Navigator Archive Project feature to create a ZIP archive of each sub-module project and related resources and return it to the team leader for assembly. In the next step, you will implement and assemble the entire design on the same system. Go to "Task 5: Block Modular Design Assembly" on page 27 FPGA Block Modular Design Tutorial 26

27 Task 5: Block Modular Design Assembly Task 5: Block Modular Design Assembly In this final task, you will act as the team leader and merge all sub-modules with the top-level design. Refer to Figure 2, "Top-Level Process Flow" on page 5 for details of the process flow. Verifying Sub-module Project Status Before you assemble the design, take notice of the Project hierarchy tree in the Sources in Project window in Project Navigator. This shows all of the submodule projects present in the top-level design. Each sub-module project is represented with a <project_name>.syn file name next to the project icon. You can double click on these different project file icons to jump back and forth between projects. In addition, the top-level designer can check on the readiness of the submodule designs in the in the Sources in Project window automatically. If there is a green check mark by a submodule, it has been successfully placed and routed. No check mark indicates the submodule is not ready. After this step has been completed, both submodule projects should have check marks by them in the Sources window. To assemble the top-level design: 1. Start the isplever system, if it is not already running. 2. In the Project Navigator, select File > Open Project. The Open Project dialog box appears. 3. Browse to the.\bmd_tutor\isplever folder, select veriloghdsn.syn, and click Open. The parent block modular design project veriloghdsn appears. 4. Click on the Device icon in the Sources window to view the implementation processes in the Processes window on the right. FPGA Block Modular Design Tutorial 27

28 Task 5: Block Modular Design Assembly 5. In the Processes window, double-click the Design Planner (Post-Map) process. The Design Planner opens in the default Spreadsheet view. 6. In the Spreadsheet view, click File > Close View. 7. From the Design Planner Control window select View > Floorplan View. The ECP6 floorplan appears. Note the colored regions in the upper left. These indicate sub-module preferences created earlier by the BMD Wizard. The Floorplanner displays the MODULE preference in a read-only mode as a colored border to represent the bounding box of the area. To directly edit a MODULE preference you must use the BMD Wizard or the ASCII Text Editor to modify the preference file. FPGA Block Modular Design Tutorial 28

29 Task 5: Block Modular Design Assembly 8. In the Floorplan View, click the Show Ratsnets button in the toolbar to enable this feature and zoom in to see the connections. In this Floorplan view, notice that colored lines showing signal routes are now visible. These signals were imported from the sub-module projects. Cyan colored lines indicate routed signals and yellow lines indicate partially routed signals between modules. In the final place-and-route assembly phase these logical connections will be routed. 9. In the Floorplan view, click File > Close View. 10. From the Design Planner Control window, select File > Exit. 11. In the popup dialog prompting you to save the changed design select No. 12. In the Processes window in Project Navigator, double-click Place & Route Design. The PAR program connects the remaining connections for the design. You have completed this tutorial. FPGA Block Modular Design Tutorial 29

30 Task 5: Block Modular Design Assembly FPGA Block Modular Design Tutorial 30