Global Trigger Processor Emulator

Transcription

1 Global Trigger Processor Emulator Dr. Katerina Zachariadou Athens University Paris Sphicas Vassilis Karageorgos (Diploma) NCSR Demokritos Theo Geralis Christos Markou Isidoros Michailakis (Electronics Engineer) Katerina Zachariadou

2 Global Trigger Processor RTP TPG FES LV1 TTC FED Timing, Trigger & Control optical network BackPressure GTP TTS FRL LV1A BackPressure EVM RCN RU BCN BDN BU GTP

3 TTC GTP Global Trigger Emulator TTS Tasks: Generate Level-1 triggers (according to trigger rules). EVM Sent triggers to TimingTriggerControl system Generate Event Number, BX counts and Trigger record data to be sent to the Event Manager (via S-Link64) Receive Trigger Throttling System levels (Ready, Busy, Error)

4 GTP-EVM-TTS simulation Global Trigger Processor Running on PC#1 Vassilis Karageorgos University of Athens Diploma work Intercommunication between programs via sockets over TCP/IP Trigger Throttling System Running on PC#3 Event Manager Running on PC#2

5 Hardware components (final) TTC-ex TTC-vi FEDs TT S VME cc 1A LV PCI-MXI2-VME PC#1:Linux OS Control VME Control G3 PC#3: Wind GB, 2.6GHz Quartus + DK1: FPGA code G3 S-LINK64 G3 PCIbus GTP emulation PC#2: Linux OS PIII 512MB,550MHz PCIbus EVM emulation

6 GENERIC-III, S-LIN64 B D E A F A. FPGA (APEX Altera 200K usable logic gates) B. 32 MB SDRAM (133Mhz) C. 1 MB Flash D. S_Link64 connectors (data transmission) E. User connectors F. PCI interface for S-LINK64 C

7 S-LIN64 Data link to connect front-end to readout at any stage in a dataflow environment Data movement,error detection, return channel for flow control CMC transmitter card: CMC receiver card: Converts S-LINK64 signals to LVDS format Converts LVDS signals to S-LINK64 signals On-board FIFO(32Kbytes) buffers incoming data

8 Hardware components (Actual) TTC-ex TTC-vi FEDs VME Dig. Oscilloscope HP54615B For hardware tests PC#1: Linux OS Labview 6.1/RUlib Control PCI bus Control G3 PC#3: Wind PIV 250MB, 800MHZ Quartus + DK1: FPGA code cc 1A LV PCI-MXI2-VME S T T G3 S-LINK64 G3 LV1Acc PCIbus GTP emulation PC#2: Linux OS PCIbus EVM emulation

9 GTP emulator schematic DK1.1 Celoxica design software In Handel-C VHDL, AHDL Quartus 2.2-Altera software PCI control GTP emulation SDRAM control SLINK-64 control OS: Linux PCI bus OS: WindowsXX PC Parallel port with a byte-blaster

10 PCI control PCI Controller: PCI communication (Dominique Gigi-CERN) Registers for Control, Status, Error, Reset operations (Isidoros Michailakis)

11 GTP- transmitter GTP -transmitter PCI control S-LINK64 Command CONTROL MEM_FULL S-LINK64 WRITE_MEM (Back_Pressure) GTP Local FIFO DATA[63..0] MEM_FULL DATA[63..0] S-LINK64

12 EVM-receiver PCI control Command S-LINK64 CONTROL Local FIFO DATA[63..0] DATA[63..0] S-LINK64

13 S-LINK64 control S-LINK64 Controller (by Isidoros) Read local fifo Transfer data PCI BackPressure transmitter

14 GTP- part Lemo Output LV1A BX_gen BX Bx_Rndm bxn evn Write_evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

15 BX generator module DK1 module that generates the LHC proton beam structure (40.8MHz) 3564 bunches = {[(72b +8e)x3+30e]x2+[(72b+8e)x4+31e]}x3 + {[(72b+8e)x3+30e]x3+81e} Clock = 80 MHz (for tests used the PCI ) Simulator output: BX is created as in LHC LV1Acc occurs only on full bunches

16 BX_Rndm module Lemo Output LV1A BX_gen BX Bx_Rndm bxn evn Write_evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

17 BX_rndm module BX_rndm module tasks: Random number generator (22 bits long Period = 4x106 events) At non empty BXs generates LV1Accept signals randomly at a frequency of 100KHz (or at any frequency [4Hz, 100KHz]) Associates a BX Number [0,3563] and an Event Number

18 BX_rndm module CLK BX BXN LV1-A rate DK1 Handel-C code Edif file Symbol for BX_rndm in Quartus EVN LV1A

19 LV1A on the scope For this test 50KHz

20 Write_Evm module Lemo Output LV1A BX_gen BX Bx_Rndm bxn evn Write_Evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

21 Write_Evm module BX number event 1. Prepares data to be sent to the local FIFO number 2. Checks the FIFO full flag (BackPressure) 3. Writes data in FIFO if not full. If the local FIFO is full the data are lost. FIFO full DATA[63..0] WEN

22 Write_Evm module timing

23 Local FIFO Lemo Output LV1A BX_gen BX Bx_Rndm bxn evn Write_evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

24 Local FIFO LOCAL FIFO (by Isidoros) FIFO : 1024 x 64 bits words, rw MUX for accessing the Control, Status etc registers

25 GTP EVM via SLINK-64 tests GTP vi running on PC#1: Generate Level1 Accept triggers at user defined frequency Send data to the Event Manager Receiver vi running on PC#2: Get data

26 Summary Dig. Oscill 1A LV Control G3+VME Quartus + DK1: FPGA code TTC GTP TTS SLINK-64 GTP EVM EVM GTP emulator conceptual design LHC beam structure, LV1A signal, EVN, BXN SLINK-64 control GTP EVM via SLINK-64

27 Future Plans TTC 1A LV Further tests of the design+integration tests of all components in a complete GTP emulator : S TT FED BackPressure signals from TTS & EVM Generate Level-1 triggers according to trigger rules Implement Trigger Summary Block Standard (FEDkit) receiver GTP BackPressure EVM TTS signals Ready Busy inhibit set of Trigger Rules : Synchr. failure inhibit + synchr command via TTC to FED s (reset counters) No more than N Level-1 Triggers in Overflow reduction of trigger rate a given time interval.

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29 RECEIVER GTP emulator G3 SLINK Byteblaster to the scope