Schematic. A: Overview of the Integrated Detector Readout Electronics and DAQ-System. optical Gbit link. 1GB DDR Ram.

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1 A: Overview of the Integrated Detector Readout Electronics and DAQ-System N s CASCADE Detector Frontend (X0) (X) (Y0) (Y) optional: CIPix- Board (T) Optical Gigabit Link CDR.0 FPGA based readout board SRAM 6 MByte optional: DDR- SDRAM ( GByte) for histogramming Optical Gigabit Link PC Schematic GB DDR Ram optical Gbit link CIPix x CIPix y CIPix x0 CIPix y0 backplane of the detector front-end The entire electronic readout and DAQ-system can be directly mounted onto the backside of the detector front-end. It is equipped with analogue front-end electronics based upon an ASIC chip called CIPix, with FPGA based readout and control of the four CIPix (28+28 readout channels), with FPGA based datapre-processing and compression and with on board RAM to realize freely configurable histogram counters. An overall number of 4 million data counters are available with a depth of 32 bit each (optional: GByte on board DDR-SDRAM for 256 Mio. counters (32 bit)). Fast logical inputs (TTL or alternatively a fibre optical trigger input) can be used to trigger time of flight measurements externally. The data counters, operating locally within the electronic itself, allow to effectively histogram and thus compress neutron data to a level, where exclusively user relevant information remains. The 256 million histogram channels could for example be configured to realize a two dimensional histogram containing a time of flight (TOF) spectrum with 6 thousand time bins for every single one of the 6k channels simultaneously. Finally, also list-mode data can be taken and read out as one possible configuration. Communication with the detector is realized through a fiber optical link, which decouples the system galvanically. It serves on one hand to configure the system through a few user accessible registers. On the other hand it provides a high bandwidth data link, which serves to download the histograms, the system has acquired. Internet:

2 B: The ASIC Readout Boards AS20- and AS20-3 AS20- ASIC CIPix. bonded to PCB AS20-3 Schematic of the CIPix. The highly integrated multi-channel analogue front-end electronics is based upon a CMOS ASIC chip called CIPix.. The system is equipped with four such chips to provide individual analogue readout of 256 channels. Up to a maximum of five chips could be employed (320 channels). The board does come in two versions: A robust version AS20-3 with input protective circuitry in particular designed for gas detector applications. Noise may prove to be 50% higher. A low noise version AS20- where protective circuitry is removed in order to achieve the best possible noise performance. : AS20- and AS20-3 AS20- AS equipped with one CIPix. 64 independent analogue input channels: low-noise charge sensitive preamplifier (2.9 mv/fc), shaper and discriminator, which accepts statistical data of 330kHz at 0% dead time, Discrimination of positive or negative signals, Discrimination threshold from 200mV up to 200mV programmable via I 2 C-interface, One analogue output of one channel can be chosen free for PHA and monitoring purposes, Internal clock 0MHz, Output signal 4-fold multiplexed TTL at 40MHz, Power requirements ±5V, I/O Connectors dual inline 70 pin, Analogue output connector Lemo, Connector for daisy chain with 20 pin. Internet:

3 C: The CASCADE Detector Readout board CDR.0 CDR.0 Power Supply CASCADE Detecor Readout Board CDR.0 CDR.0 FPGA parallel data processing unit Xilinx Virtex II XC2V3000, 6 MByte on board fast histogramming SRAM for a total of 4 million 32 bit counters, non interfering list mode FIFO for monitoring purposes, optional: GByte on board DDR-SDRAM for a total of 256 million 32 bit counters, fast trigger inputs: 2 Lemo, optical trigger input, fast trigger output: Lemo, Automatic download of operating code from PROMs on board during power up, Programming interface via JTAG. Power Supply Linearly regulated power supply (220V/0V AC), Special, shielded power cable of up to 5m length. Internet: Specific measurement tasks to be executed on the detector can be defined through a set of digital registers in the CDR.0 board.

4 D: The DAQ-System Programmable pulse height analysis electronics IF5-2 Fiber optical Gbit link SIS00 from SIS GmbH, Hamburg : IF5-2 IF5-2 5 independent ADC input channels with 2bit resolution at 40MHz, FPGA parallel data processing unit Xilinx Spartan 3 with peak finder algorithm, controlled via CDR.0, 5 analogue input connectors Lemo, 3 I/O connectors dual inline 2 pin to CDR.0, Power supply from CDR.0. Internet: : optical Gbit link SIS00 SIS00OPT Small form factor (SFF) for Gigabit link media: LC connectors, Link is clocked at 25 MHz with a theoretical payload of 25 Mbytes/s, Standard multimode link media allows distances of up to 450m. SIS00CMC Single CMC site carrier board, Standard PCI (32-bit, 33 MHz), Single +5 V supply 2

5 E: CDT Detector Control Software Windows based software package CDT Detector Control allows stand alone operation of the detector and its readout electronics from a PC. It supports easy configuration of the system, starting and ending data acquisition as well as data download and variable display. The program itself is held in the typical Windows-style. Various types of measurements (e.g. 2D-readout, TOF-spectra or pulse height spectra) can be configured individually in a self explanatory way. Software drivers allow integration of the detector system into already existing instrument control under Windows (NT/2000/XP) and Linux (Kernel 2.4.x). Support for high level programming under C++ is provided with the CASCADE Hardware- Library, which supplies routines for configuration and measurement of the detector respective the CDR.0 board and each CIPix readout board. Internet: