SoLID GEM Detectors in US

Transcription

1 SoLID GEM Detectors in US Kondo Gnanvo University of Virginia SoLID Collaboration JLab, 05/07/2016 Outline Overview of SoLID GEM Trackers Design Optimization Large Area GEMs for PRad in Hall B Integration of APV25 readout in CODA

2 Overview of SoLID GEM Trackers Tracking requirements for PVDIS Luminosity ~ /cm 2 /s Rate: from 100 khz/cm 2 to 600 khz/cm 2 (with baffles) from GEANT4 estimation Spatial Resolution: ~ 100 µm (σ) in azimuthal direction Total area: ~37 m2 total area (30 sectors 5 planes, each sector covering 12 degree) Need radiation and magnetic field tolerant Large area GEM challenges Larger SoLID GEM modules as large as 113 cm 55 cm New Single Mask technique allows to make GEM foils as large as 200 cm 55 cm The remaining challenge is large production capacity: If all LHC related large GEM project (CMS, ALICE, TOTEM) gets underway, this will require almost 100 % of CERN production capacity Currently work going on for large GEM production capabilities in China and in the US. PVDIS 5 disk layers SIDIS 6 disk layers Large number of readout channels; but cost of electronics going down cost per channel for the RD51 SRS APV-25 based readout is ~ $ U/V stereo angle 2D readout reduce the channel count while maintaining a very good spatial resolution 2

3 Overview of SoLID GEM Trackers: PVDIS Configuration Instrument five locations with GEMs 30 GEM modules at each location PVDIS Largest GEM module size required: 113 cm x 55 cm about the size of PRad GEM chambers currently in Hall B With ~5% spares, we will need about 170 k readout channels. 3

4 Overview of SoLID GEM Trackers: SIDIS Configuration Six locations instrumented with GEM trackers: Original idea: Re-arrange PVDIS module in SIDIS configuration PVDIS Plane Z (cm) R I (cm) R O (cm) Active area (m 2 ) # of channels k k k k k k SIDIS total: ~20.4 ~ 161 k However, GEM module length L is set by the inner and outer radius of the disk layer: L= R_out R_in A SIDIS and PVDIS layers can used the same GEM modules only if L is the same, unless there is a tolerance dl on the layer GEM dimensions (for SIDIS) given the module size of a PVDIS GEM module L SIDIS = L PVDIS + dl 4

5 Design optimization: Can we use the same modules in both PVDIS & SIDIS layers? Assuming different level of tolerance dl on SIDIS GEM modules: dl = 1 cm only GEM module #3 used for PVDIS layer #1 can be reused for SIDIS layer #6 dl = 5 cm only GEM modules #3 and #5 used for PVDIS layer #1 & #3 can be re-used for SIDIS layer #6 & #2 dl = 12 cm all 5 PVDIS GEM modules can be re-used in SIDIS Configuration Experiment module Id Layer Id R_in (cm) R_out (cm) Length [R_out - R_in] (cm) Z (cm) SIDIS SIDIS PVDIS SIDIS PVDIS PVDIS SIDIS SIDIS SIDIS PVDIS PVDIS Basically, we can not use the same modules in both PVDIS and SIDIS configuration if we want to keep from the currents dimensions (R_out R_in) fixed 9 GEM modules design (different size and UV angle) (for both SIDIS and PVDIS But (from Zhiwen) it looks like we can play with outer radius of SIDIS layers and in that case, the number of modules can be limited to 6 5

6 Design optimization: Do we need 30 modules / layers? Large GEM modules: All GEM modules with a width of ~ 55 cm Current limitation imposed by raw material (width of the roll ~ 61 cm) we can limit the number of modules in each layer Cost saving in materials & labor Optimize dead-to-active area ratio Reduced constraints on the GEM frames widths Performances of the readout strips With the U/V stereo angle strips readout spatial resolution or occupancy do not depend of the detector width We can arrange to have HV sector on the foils Example of PVDIS layer Example of SIDIS layer 6

7 Design optimization: Do we need 30 modules / layers? This is a quick estimation of how many modules are needed for each layer for both PVDIS and SIDIS with the assumption that layer #3 and #5 are common for PVDIS and SIDIS 151 GEM modules needed for all 9 GEM designs module Id Experiment Layer Id Z (cm) R_in (cm) R_out (cm) L = R_out - R_in (cm) # modules / layer 1 SIDIS SIDIS PVDIS SIDIS PVDIS PVDIS SIDIS SIDIS SIDIS PVDIS PVDIS TOTAL 151 7

8 Large Area GEMs for PRad Experiment in Hall 8

9 The PRad Experimental Setup in Hall B Target specs: cell length 4.0 cm cell diameter 8.0 mm cell material 30 μm Kapton input gas temp. 25 K target thickness 1x10 18 H/cm 2 average density 2.5x10 17 H/cm 3 Cell pressure 0.6 torr Vacuum in target chamber ~5x10-3 torr H 2 target GEMs: factor of >10 improvements in coordinate resolutions similar improvements in Q2 resolution (very important) unbiased coordinate reconstruction (including transition region) increase Q2 range by including Pb-glass part GEMs HyCal Vacuum box HyCal specs: 34 x 34 matrix of 2.05 x 2.05 x 18 cm 3 PbWO4 shower detectors 576 Pb-glass shower detectors (3.82x3.82x45.0 cm 3 ) 5.5 m from H 2 target (~0.5 sr acceptance) Resolutions for PbWO4 shower: σ/e = 2.6 %/ E, σ xy = 2.5 mm/ E Resolution for Pb-glass shower detectors factor of ~2.5 worse 9

10 cm Large Area PRad GEMs: Requirements & Design PRad GEM chambers: 2 large modules side by side 105 cm 2D strips readout spatial resolution < 70 mm GEM foil F. Sauli, Nucl. Instr. and Meth. A386(1997)531 Exploded view COMPASS triple-gem design Copper 10

11 PRad GEMs in Hall JLab Two chambers were built at UVa and sent to JLab in February 2016 we setup a cosmic run with PrimEx Scintillators layers used for trigger of the APV25 SRS The chambers are now in Hall B, installed in front of the HyCal Installation is ongoing and commissionning to start on May 13 PRad GEMs move to the Hall last week PRad GEMs on cosmic setup in EEL 11

12 Front-End Electronics for PRad GEMs: The Scalable Readout System (SRS) Multichannel electronics developed by the RD51 Collaboration for Micro Pattern Gaseous Detectors such as GEMs. It is based on: SRS-APV25: Front End cards (hybrids hosting the APV25 chip) mounted on the detector send multiplexed data from128 channels to SRS-ADC cards via standard commercial HDMI cables. SRS-ADC: card that host the ADC chips, de-multiplex and convert data from up to 16 SRS-APV25 cards into digital format then send them to the SRS-FEC cards SRS-FEC: is the FPGA board, handles the clock and trigger synchronization of the SRS-APV hybrid cards, send digitized data from ADC to the SRS-SRU via 1 Gb Ethernet Copper link. SRS-SRU: handles communication between multiple (up to 40) SRS-FEC cards and the DAQ computer. It Need for the PRad GEMs: also distributes the clock and trigger synchronization Hardware: 72 SRS-APV FE cards (36 per GEMs) total of 9184 channels to read out to the SRS-FEC cards and send the data fragment to 8 SRS-ADC / SRS-FECs with 9 APVs cards, 3 time samples the DAQ PC through Gb Ethernet. 2 SRS-SRUs to collected the data from the FECs transfer to the DAQ PC TIpcie: Interface the SRS electronics into JLab DAQ (CODA) Firmware upgrade 12

13 SRS Firmware Upgrades (B. Moffit, JLab DAQ group - B. Raydo, JLab Fast Electronics Group) SRS-SRU firmware upgrade: Standard firmware developped for APV25 had 1Gb Ethernet link Upgrade of APV25-compatible 10 Gb SRU firmware (JLab DAQ) Test setup 36 APVs, 3 Time sample, 3 FECs (Event size 38.5 kb) APV25 calibration pulse with internal trigger Rate tests with standard 1(Gb) and upgraded (10 Gb) firmware 1 Gb link (SRU): ~3.2 khz (Max. rate ~ 3.3 khz) 10 Gb link (SRU): linear data transfer speed up to 5.5 khz saturation expected beyond 6 khz (FEC data to 80 MB/s) SRS-FEC firmware upgrade: Trigger buffering and Busy signal implementation Test setup for 5 khz random trigger rate 9 / 12 APV25 (ADC channels), on 1 FEC with 3 time samples to the SRU (Expected configuration for PRad) Random pulse generator board Un-buffered triggers firmware: readout rate of ~2.8 khz (9 APVs on FEC) 44% dead time Buffered trigger firmware: readout rate of ~4.25 khz (9 APVs on FEC) 15% dead time, OK for PRad limitation 1 Gb FEC to SRU SRU 1Gb: limitation 1 Gb link to DAQ PC 13

14 Integration of SRS into JLab DAQ (B. Moffit, JLab DAQ group - B. Raydo, JLab Fast Electronics Group) PCIexpress Trigger Interface (TIpcie) PC / Server Integration into JLab Pipeline DAQ Standard PC Hardware allows for multiple network cards (1G, 10G, Infiniband) Fiber Connection (Clock, Trigger, Sync) to Trigger Supervisor Runs in Standalone (Master) or Larger-Scale DAQ (Slave). Software librairies for the slow control C Library written to be used with CODA, but also works standalone (Master mode) Kernel and userspace driver compatible with EL5, EL6 (i386, x86_64) Interface to the SRS APV Data from SRU to the DAQ PC with 10 Gb Ethernet SRU trigger from the TIpcie, FECs send BUSY signal to Trigger Supervisor Setup test with the Tipcie The back side of the DAQ PC shows: TIPCIe blue fiber connection to the TS Twisted pair connections for triggers. The 10 Gb card for data transfer with the links connected (black) to the SRU. DAQ PC multiple cores/threads for data processing online zero suppression for data reduction factor ~200 TIPCie to transfer data to main DAQ PC Online monitoring of Raw APVdata and GEM hits TIpcie 14

15 Summary / Outlook SoLID GEM-US program for a two years pre-r&d Optimized & finalize the design of GEM modules for all SoLID configuration Design ideas to improve performance and lower production cost Setup a program to start testing and characterization of Chinese GEM foils Investigate needs and option for SoLID GEM readout electronics Study the currently available candidate such as BNL VMM or Saclay DREAM chip Large GEM activities in US (UVa & Temple U) Production of Large Area GEM trackers for the SBS in Hall A and PRad in Hall B PRad GEM largest GEM detector built. Size comparable to largest SoLID GEM module Ongoing intensive GEM R&D for the EIC forward tracking Progress in the integration of the APV25 readout electronics into JLab CODA DAQ Development for both SRS and MPD readout systems 15

16 Back Up 16

17 The PRad JLab: ep ep Scattering Proton Radius puzzle PRad Experiment (E ): High A rating (JLab PAC 39, June 2011) Experimental goals: Very low Q 2 ( to ) 10 times lower than current Mainz Sub-percent precision in <r p2 > extraction Specifications for PRad Experiment Non Magnetic spectrometer High resolution and high acceptance calorimeter low scattering angle [0.7 o ] Simultaneous detection of ee ee (Moller Scattering) minimize systematics High density windowless H 2 gas target minimze background clean CEBAF electron beam (1.1 GeV & 2.2 GeV) minimze background 17

18 SRS-FEC Firmware Upgrade: Trigger Buffering (B. Moffit, JLab DAQ group - B. Raydo, JLab Fast Electronics Group) Non-buffered trigger FEC firmware (original): Live Dead APV UPD Frame APV UPD Frame ~10us Buffered trigger FEC firmware (new): ~200us Dead/busy while APV sends triggered data and dead/busy while UPD packets are sent For fixed trigger rate, the dead time is basically determined by the UDP data processing (~200 ms) For random trigger: the mechanism is inefficient Live Dead no use of live time with low trigger burst but high trigger burst mean data loss because of dead time APV APV UPD Frame APV APV APV UPD Frame ~10us ~200us Dead/busy while APV sends triggered data, no longer dead/busy while UPD packets are sent UDP processing of APV data is de-correlated from APV sending data When buffers in FPGA (holding captured APV for UDP processing) become full, then the FEC create necessary dead/busy time. For random high trigger burst, APV data are stocked in buffer and UDP packet is formed during the low trigger burst Dead/busy time while APV sends data can be eliminated to improve live time, but requires significant changes to FEC firmware. 18

19 Integration of SRS into JLab DAQ: PRad DAQ Overview JLab network Data/Control PRad DAQ PC GEM DAQ PC 10 GbE optical fiber SRS-SRU TIpcie 10 Gb NIC SRS-FECs Crate Gate for Fastbus ADCs Trigger to TI slaves SRS-FEC BUSY signal Logic and Translation Linear Sum Trigger to TI master Timing information to JLab discriminators 19