Physical Aware System Level Design for Tiled Hierarchical Chip Multiprocessors

Transcription

1 Physical Awae System Level Design fo Tiled Hieachical hip Multipocessos Jodi otadella, Javie de San Pedo, Nikita Nikitin and Jodi Petit Univesitat Politècnica de atalunya (Bacelona) Poject funded by Intel op.

2 Designing a hip Multipocesso DSP Gaphics Data Mining Bioinfomatics MP Off hip Memoy How many coes? How much /L3 on-chip cache? Inteconnect: mesh/ing/bus? How many memoy contolles? ISPD 2013 Tiled MPs 2

3 What is achitectual exploation? M M M Bus 2 1 R NI L3 6x4 mesh, 24 clustes total 144 coes 6 coes/cluste 1 1, 128K L1, 256K 5 2, 64K L1, 96K 146 Mb total shaed L3 M Thoughput = IP M M M R NI Bus 2 L3 5x5 mesh, 25 clustes total 100 coes 4 coes/cluste 3 1, 128K L1, 1M 1 2, 128K L1, 1M 130 Mb total shaed L3 Thoughput = IP M ISPD 2013 Tiled MPs 3

4 Libay of models ISPD 2013 Paamete hip aea Mesh dimensions Mem. ntl. latency Inteconnect Link width Wokload MPI Wokload MLP IP MP configuation Value oe libay 350 mm 2 2x2 to 16x cycles Bus, uni / bi ing bits (OoO) 1 (IO) Aea (mm 2 ) 3 (OoO) Tiled MPs Miss Ratio ache Size ache models Aea (mm 2 ) Latency (cycles) 64Kb Kb Kb Mb Miss ates fo SPE PU ache Size (Mb) 4

5 Physical planning fo tiled MPs N W E S ISPD 2013 Tiled MPs 5

6 Outline Achitectual exploation The cost of exploation Exploing with metaheuistics Analytical models Physical planning fo tiled MPs uent wok: egula flooplanning ISPD 2013 Tiled MPs 6

7 Exploation engines 1E+13 1E centuies Design space: 10 9 configuations Exploation untime (sec) 1E+11 1E+10 1E+09 1E+08 1E+07 1E+06 1E yeas 100 days seconds 10 1 Simulation (full system) Simulation (pobabilistic) Analytical (exhaustive) Analytical (metaheuistic) ISPD 2013 Tiled MPs 7

8 Scalable exploation Achitectual configuations Pomising configuations Analytical Modeling Simulation ISPD 2013 Tiled MPs 8

9 Automated exploation Models (pefomance/powe) oes On chip caches Off chip memoies Inteconnect fabics ache potocol Wokloads Physical info oes aches Inteconnects Exploation tool onstaints Aea Thoughput Powe Achitectual configuation Numbe of coes luste size /L3 size Inta cluste inteconnect Inte cluste inteconnect Memoy contolles ISPD 2013 Tiled MPs 9

10 Exploation engine: metaheuistics Exploe huge design spaces efficiently Ou poposal: Simulated Annealing (Kikpatick et al., 1983) Extemal Optimization (Boettche et al., 1999) Models onstaints Best configuation Patial geneation of configuations Simulation seach diection Analytical modeling Exploation tool ISPD 2013 Tiled MPs 10

11 Geneation of configuations Geneate neighbos by applying tansfomations Incease/Decease mesh dimensions coe count pe cluste L1, size hange inteconnect type (bus/uni ing/bi ing) omplex updates (incease mesh/decease coe count) Example: Incease_X(mesh 4x4) => mesh 5x4 Incease_X ISPD 2013 Tiled MPs 11

12 Analytical pefomance model fo MPs oe Memoy subsystem Nonlinea analytical models Thoughput model: λ oe oe λ i L i Queueing model: Umit Ogas et al. IEEE TAD, Dec 2010 L Thoughput L L Taffic model: Latency model: L, aveage latency (cycles) haacteistic of the coes/wokload λ (L) haacteistic of the I L(λ) Hop count λ, aveage taffic ate (flits/cycle) latency ISPD 2013 Tiled MPs 12

13 Analytical model vs. simulation 80 Modeling Analytical modeling Simulation Simulation Thoughput (IP) onfiguations soted in descending ode of thoughput ISPD 2013 Tiled MPs 13

14 ase Study: Powe pefomance exploation Thoughput (IP) Powe pefomance tade off (Seach space: configuations) 4x2, Bi Ring, x2, Bi Ring, x4, Bus, 4 2 6x5, Bus, x4, Bi Ring, 6 2 5x3, Bi Ring, 8 2 6x5, Bus, 4 2 7x4, Bus, x5, Bi Ring, 4 2 4x3, Bi Ring, x4, Bus, Powe (W) ISPD 2013 Tiled MPs 14

15 Outline Achitectual exploation Physical planning fo tiled MPs Impact of physical planning Flooplanning Wie planning uent wok: egula flooplanning ISPD 2013 Tiled MPs 15

16 Physical planning NSWE R L3 ISPD 2013 Tiled MPs 16

17 The impact of physical planning NSWE R L3 ISPD 2013 Tiled MPs 17

18 Physical planning fo tiles N W E S ISPD 2013 Tiled MPs 18

19 Link width: how many wies? Route ntl Add ache line > 1K wies 100 m ntl Add ache line Route ISPD 2013 Tiled MPs 19

20 3D Wie Planning m6 m5 m4 m3 oe Route Memoy m2 m1 FEOL ISPD 2013 In systems whee memoy bandwidth is the bottleneck, the physical esouces poviding the bandwidth ae citical Tiled MPs 20

21 Exploation without physical planning Models onstaints Geneation of configuations Achitectual exploation Analytical modeling seach diection Validation Best configuation Simulation ISPD 2013 Tiled MPs 21

22 Exploation with physical planning Models Phys. Info onstaints Geneation of configuations Achitectual exploation Analytical modeling seach diection Validation Physical planning Best configuation Simulation Wie Planning Flooplanning ISPD 2013 Tiled MPs 22

23 Physical planning Analytical Modeling Local I L3 R Physical Planning Simulation Estimations: Aea Wielength Routability L3 ISPD 2013 Tiled MPs 23

24 Physical planning technology Flooplanning Slicing stuctues & Simulated Annealing Lightweight 3D maze oute onstaints: Adjacency (oe ) Balanced links (ings) Wie planning SAT based 3D global outing Boolean constaints ISPD 2013 Tiled MPs 24

25 Slicing stuctues H V H V V H V H D.F. Wong and.l. Liu, A New Algoithm fo Flooplan Design DA, 1986, pages ISPD 2013 Tiled MPs 25

26 Bounding cuves Memoy L. Stockmeye, 1983, Optimal Oientation of ells in Slicing Flooplan Designs ISPD 2013 Tiled MPs 26

27 Wie planne SAT based appoach fo gidded outing Gid unit: link width ( wies) Suppot fo floating teminals ustomizable fo any type of Boolean encoded constaints (symmety, 1D/2D outing, ) Top view oss-section view ISPD 2013 Tiled MPs 27

28 Wie planne W W Route E E oncuent outing: all nets simultaneously Using Eule s theoy to find legal outes SAT: a oute is always found if it exists ILP based oute optimization ISPD 2013 Tiled MPs 28

29 Design space ISPD 2013 Tiled MPs 29

30 Design space Wie length [10 6 μm] ISPD 2013 Tiled MPs 30

31 Filteing flooplans Aea [mm2] ISPD 2013 Tiled MPs 31

32 Filteing flooplans Aea [mm2] ISPD 2013 Tiled MPs 32

33 Afte physical planning ISPD 2013 Tiled MPs 33

34 Afte physical planning ISPD 2013 Tiled MPs 34

35 Afte physical planning ISPD 2013 Tiled MPs 35

36 Outline Achitectual exploation Physical planning fo tiled MPs uent wok: egula flooplanning Memoy flooplanning Regulaity extaction ISPD 2013 Tiled MPs 36

37 Min aea flooplan NSWE R L3 L3 R ISPD 2013 Tiled MPs 37

38 Integated memoy flooplanne 1Mb 1Mb 1Mb 512Kb 512Kb 512Kb L-shape 512 Kb 256 Kb 512 R Kb 256 Kb T-shape ISPD 2013 Tiled MPs 38

39 Regula flooplan NSWE R L3 L3 R ISPD 2013 Tiled MPs 39

40 Regula flooplan L3 R L3 R Regulaity: Smalle design effot Efficient timing closue hoppability ISPD 2013 Tiled MPs 40

41 Regula flooplan L3 R L3 R Regulaity: Smalle design effot Efficient timing closue hoppability Exploation: Gaph based knowledge discovey Hieachical slicing stuctues Simulated Annealing ISPD 2013 Tiled MPs 41

42 onclusions Physical infomation is essential fo the achitectual exploation of tiled MPs Appoach: divide & conque 1 cluste flooplan + abutment constaints Build tiled MPs (scalable and choppable) Ongoing wok: Multi module memoy flooplanning Regulaity ISPD 2013 Tiled MPs 42