Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs

Transcription

1 Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurall Snthesize BDDs Sergei Devaze, Jaan Rai, Artur Jutman, Raimun Ubar Tallinn Universit of Technolog, Estonia {serega, jaan, artur, Abstract An efficient metho of parallel fault simulation for combinational circuits is propose. The metho is base on structurall snthesize BDDs (SSBDD which allow to represent gate level circuits at higher macro level where macros represent subnetwors of gates. Converting the gate-level circuits to the macrolevel is accompanie with corresponing fault collapsing. A parallel fault analsis algorithm for SSBDDs was evelope which calculates the etecte representative faults for a given set of test patterns in the corresponing macro. The algorithm is equivalent to parallel critical path tracing in the gate-level circuits of macros. Because of the reuce fault list an higher abstraction level moeling the spee of fault simulation is increase. For the faults in fanout noes a new full Boolean ifferentials base parallel fault analsis metho is propose. The paper presents experimental ata revealing the avantages of the propose ata structure in the fault simulation process. Introuction Fault simulation is a wiel use proceure in the igital circuit esign flow. Most of the test esign tass (fault injection, test pattern generation, built-in self-test, etc. rel on it. Thus, accelerating the subtas of fault simulation woul consequentl improve all the above-mentione applications. Parallel pattern single fault propagation (PPSFP [] is wiel use in combinational circuit fault simulation. Man propose fault simulators incorporate PPSFP with other sophisticate techniques such as test etect [2], critical path tracing [3,4], stem region [5] an ominator concept [4-6]. These techniques reuce the simulation time b utilizing information of previous simulate faults. Current paper combines parallel pattern simulation with parallel fault simulation b critical path tracing to create the full fault table for a group of test patterns with a single pass of the algorithm. In this paper we present a novel approach to parallel fault simulation for combinational circuits base on a special class of Binar Decision Diagrams (BDD. While the efficienc of BDDs for simulation is well nown, traitional BDDs o not allow to implicitl moel logic level faults an thus are not well-suite for fault simulation In [7], the logic netlist is partitione into supergates. In other wors, fault simulation is carrie out for circuit lines corresponing to the fanouts [4]. Current paper combines the two above ieas an goes much further b introucing the circuit moel of Structurall Snthesize Binar Decision Diagrams (SSBDD for fault simulation [8,9]. SSBDD moels allow consierabl coarser partitioning than supergates. Furthermore, the approach allows to restrict the number of consiere circuit lines to the fanout points while allowing to wor on the higher level of abstraction, without an nee to escen to simulation at the gate-level. Aitional benefit of SSBDDs lies in the fact that it provies for the fault collapsing in the moel itself without a nee to specif the list of collapse faults explicitl. In all the noes of an SSBDD, both, stucat 0 an stuc-at faults have to be covere in orer to guarantee 00 % fault coverage of the corresponing gate-level circuit. This means that, contrar to traitional gate-level collapsing techniques, it is not necessar to chec if a fault at a circuit line is inclue to the collapse list. This in turn results in time savings uring the simulation process. A combinational circuit is presente as a networ of SSBDDs. Each SSBDD ma represent a gate-level subcircuit calle a macro. In this paper we restrict with macros that correspon to fan-out free regions (FFR. An algorithm is evelope an implemente for parallel fault simulation base on the new SSBDD

2 moel. Up to the present moment, BDD moels have not been use for parallel simulation. One of the most efficient methos for fault simulation in igital circuits is critical path tracing metho [3,4]. It consists of simulating the fault-free circuit (true-value simulation an using the compute signal values for bactracing all sensitize paths from primar outputs towars primar inputs, to etermine the etecte faults. In the bactrace, a gate's input is sensitive if complementing its value changes the value of the gate's output. The trace continues until the paths become non-sensitive or en at networ primar inputs. Faults on the sensitive paths are etecte b the test. This proceure can be carrie out in parallel simultaneousl for a group of test patterns. In the case of macro-level representations of igital evices, Boolean erivatives can be use for critical path tracing through macrocomponents. The rawbac lies in that the librar is neee to represent the expressions of Boolean erivatives for ifferent macrocomponents. In this paper we propose SSBDDs for computing the values of Boolean erivatives [8,9]. Deicate libraries are not neee for storing expressions of erivatives. Instea, simple proceures on SSBDDs are use, which compute the Boolean erivatives in parallel simultaneousl for N test patterns where N is the length of the computer wor. An EDIF to SSBDD esign interface for the fault simulator has been evelope that provies the tool with a lin to most popular commercial CAD sstems, incluing Caence, Snopss, Mentor Graphics an Viewlogic. The paper is organize as follows. Section 2 introuces the moel of SSBDDs for representing logic circuits. In Section 3 the basics are given how to generate SSBDDs from gate level circuits. Section 4 explains how the parallel critical path tracing in FFRs can be prouce on SSBDDs. In Section 5 the critical path tracing metho is generalize to use it for reconvergent fan-out regions. Section 6 provies experimental results an Section 7 conclues the paper. 2. Structurall Snthesize BDDs Structurall Snthesize Binar Decision Diagram (SSBDD [8,9] is a planar, acclic BDD that is obtaine b superposition of elementar BDDs for logic gates. An SSBDD G is a triple (M, X, Γ, where M is a set of noes, X is a set of Boolean variables, x(m X is a function, which efines line variables labeling the noe m, an Γ(m, e is a function, which efines the successor noe of m with x(m = e, e {0, }. Denote the set of preecessors of m b Γ - (m M. The set of noes M is ivie into a set of nonterminal noes M N an to a set of terminals M T incluing 0- an -terminals, where M = M N M T. Fig. shows an FFR of a logic circuit with an output line an its corresponing SSBDD. Note, that in the Fig.b we have omitte the 0- an -labels at the eges, since their irection (own or right replaces the corresponing label. Downwar eges correspon to 0-eges an rightwar eges correspon to -eges. 0- an -terminal noes are illustrate b ashe lines an can be also omitte. In the latter case, exiting the BDD ownwars correspons to = 0 an rightwars to =, respectivel. In aition, SSBDD noes can also be labele b inverte variables (e.g., 5, an 72 in Fig a b c a b Fig.. a Gate level circuit an b its SSBDD In orer to consier simulation on SSBDD moels, let us introuce some basic efinitions. Let us enote Γ(m, e b m e. Then m 0 is the successor of m for the value x(m = 0 an m is the successor of m for the value x(m =. B the value assignment x(m = e, e {0,}, we sa that the ege between noes m an m e is activate. Consier a situation where all the variables x(m X are assigne b a Boolean vector X t {0,} X to some value. The eges activate b X t form an activate path FFR e -eges 0-eges

3 L* = (m 0,, m T from the root noe m 0 to one of the terminal noes m T M T. In [9], it has been prove that G represents a Boolean function = f(x, iff for all the possible vectors X t {0,} X a path L* = (m 0,, m T is activate so that = f(x t = x(m T. Differentl from traitional BDDs, SSBDDs support test generation for gate-level structural faults in terms of signal paths without representing these faults explicitl. Furthermore, the worst case complexit an memor requirements for generating SSBDD moels for FFRs are linear in respect to the number of logic gates in the circuit, while for traitional BDDs the total storage space excees 2 n bits for an n-input combinational circuit [0]. Hence, SSBDDs for an arbitrar realistic-size igital circuit can be generate ver rapil using onl a small amount of computer memor. 3. Snthesis of SSBDDs The most significant ifference between the traitional BDD an the SSBDD representations is the metho how the are generate. While traitional BDDs are generate b Shannon's expansions, which extracts the function of the logic circuit, SSBDD moels are generate b a superposition proceure that extracts both, function an ata about structural paths of the circuit. Another ifference between the classical an the SSBDD approach is that in SSBDDs we represent a igital circuit as a sstem of BDDs, where for each fanout-free region (FFR of the circuit a separate SSBDD is generate. SSBDD moels for gate-level igital circuits are generate as follows. Starting from the output of the FFR (i.e. primar output or a fanout point of the circuit, logic gates are recursivel substitute b their respective elementar BDDs. The proceure of superposition terminates in those noes, which represent a primar input or a fanout branch of the circuit. Fig.2b shows the superposition-base SSBDD generation for the FFR given in Fig.2a. Note, that in SSBDDs the noes can be labele b both, variables x i an their inversions x i. An important propert of SSBDD is that each noe in it represents a relate signal path in the corresponing gate-level circuit. For example, the noe enote b bol circle in Fig.2b correspons to the path mare b bol lines in Fig. 2a. There are four ifferent signal paths in the circuit an thus, four noes in the respective SSBDD. From the above-mentione propert it follows that if we cover the stuc-at faults in all the noes of the SSBDD (in other wors, cover ever signal path, we will consequentl cover all the stuc-at faults in the corresponing gate-level FFR. Thus, SSBDD moels are capable of implicit representation of gate-level stuc-at faults. 3 a b Fig. 2. Superposition of SSBDD moels As it was mentione above, the stuc-at faults in SSBDDs are moele at noes an each noe correspons to a istinct path in an FFR. However, the number of signal paths in an FFR is alwas less or equal than the number of lines between the gates of the FFR. Hence, b generating an SSBDD for a circuit we simultaneousl perform collapsing of the faults. Unlie in traitional fault collapsing where the aim is simpl to minimize the number of faults in the fault list, here, we are at the same time capable of rising to a higher abstraction level of circuit moeling. While fault simulation an test generation are the main areas of using SSBDD moels, this tpe of representations have been successfull implemente in a wie range of other VLSI CAD applications. These inclue multi-value simulation [], timing simulation [2] an esign error iagnosis [3]. 4. Parallel critical path tracing on SSBDDs Parallel fault simulation taes avantage of the wororiente nature of operations in the computer to simulate the effects of a number of faults simultaneousl. The number of faults that can be 2 4

4 simulate uring a simulation pass is etermine b the wor length n of the host CPU. If the number of faults is large then multiple simulation passes are require. Consier a fanout free region = F(X in the given gate level networ an the corresponing SSBDD G = (M, X, Γ. The noes in the graph have to be orere for processing in such a wa that for each noe m M with the numerical label l(m, all its preecessors j Γ - (m must have labels l(j less than l(m. The fanout region = F(X will be fault simulate in parallel for a test vector T = (t, t 2,... t n. Fault-free simulation In the first stage parallel fault free simulation is carrie out for all fanout regions starting from the primar inputs. To simulate the vector function = F(X with G for the given test vector T, all the vector variables in X shoul have got alrea values. The simulation taes place as follows. Starting from the noe with the highest label value (final noe where Γ(m,e =, we repeat the vector operation: 0 x( m = ( x( m x( m ( x( m x( m for each noe of the SSBDD. In this operation, m enotes the current noe an m 0 an m are its 0- an -successors, respectivel. x(m enotes value of the vector variable labeling the noe m. The result of the simulation will be the value of calculate for the root noe m 0 where Γ - (m =. The rest of the calculate new values of x(m represent the values of subfunctions with roots in m M\m 0. Calculation of activate noes In this stage for each test vector t T simulate in parallel the noes m M in SSBDD will be foun which are laing on the activate paths L*(t M. It is eas to unerstan that onl these noes are responsible for the value of the graph variable (t. Hence, onl these noes m L*(t are caniates for fault etection. To fin the caniates for fault etection the noes m M are processe in the irect orer recursivel in the following wa: L(m = L(m [L(m x(m], L(m 0 = L(m 0 [L(m x (m ], starting with initial values L(m 0 =... an for all other noes m i M: L(m i = The value of the component L (m= of the calculate vector L(m means that the noe m i M was traverse b the test pattern t, othervise not. Critical path tracing In the last stage, we carr out parallel critical tracing to fin out at which noes of activate paths L(m(t the faults are etecte. Detectabilit of faults in the FFR = F(X represente b G on the output of the FFR is calculate: S(m = L(m [x(m 0 x(m ]. The value of the -th bit S (m in the vector S(m is (0 if the fault in x(m is etecte (is not etecte on the output b the -th test pattern t of the pacage T simulate. 5. Reconvergent fanouts The parallel gate-level critical path tracing insie the FFRs is straightforwar. We have shown how to generalize this proceure to the higher macro level b calculation Boolean erivatives for arbitrar tree-lie subcircuits in parallel b SSBDDs. To exten the usabilit of parallel critical path tracing metho beon the fan-out free regions we propose to use partial Boolean ifferentials [4]. Fig.3. Gate-level circuit with reconvergent fanout Assume that the final gate (with arbitrar Boolean function of the convergent fan-out region in circuit Fig.3 is = F(x,, x i, x j, x n. Assume that the input variables x,,x i of the gate F are connecte via gate-level networ with functions x = f (x,x,, x i = f i (x,x i to the fanout noe x. Then the function of the full convergent fan-out region can be represente as = F(f (x,x,, f i (x,x i, x i, x n. The full Boolean ifferential of the gate F is = F(( x x,..., ( xi xi, ( x x,..., ( x x j j Consiering now the impact of onl the stem variable x to the value of, uner conitions x j = 0,, x n = 0 (no faults in x j, x n, we can represent the partial Boolean ifferential of regaring x as follows: F = F(( x f,..., ( x f, x,..., x. x x x i x j n x x n x i xi i j n F n

5 Since partial ifferentials for x h = f h (x,x h, where h =,..i, regaring x are we get f h h xh fh = x = x, i x F = F(( x x,..., ( xi xi, x j,..., xn Since the partial ifferential for regaring x is x F = x, an assuming that x = we get = F(( x,..., ( x, x,..., x i i j n ( From the formula ( the metho results to generalize the parallel critical path tracing beon the fan-out free regions. Inee, all the calculations in ( can be fulfille in parallel. If we now the values of the Boolean erivatives /,, i /, the erivative / can be calculate irectl at the gate F after correcting the values of its input variables x,, x i. But the values of /,, i / can be calculate in parallel uring the normal critical path tracing insie the given fan-out free region with output. In the general case of neste convergent fan-out regions we can easil create the respective neste calculation flows to fin the etectabilit of fan-out variables. An example of a neste reconvergent fan-out circuit is represente in Fig. 4. There are two reconvergencies at the gates z = F z (c,b,x z an = F (,e,x. Denote b A,B,C,D,E the calculate activities on the respective paths of the circuit. For example, b/ = B, c/ = AC, / = AD, an e/ z = E. x A B q C X z c b Fig.4. Neste reconvergent fanouts All the path activities A,B,C,D,E can be calculate b parallel path tracing onl once. When reaching uring the bactrace the fan-out point q, we calculate = F ( D, e CE, X. q D F z z E X e F For calculating the Boolean erivative / we have z = F ( AD, e E, X where z = z Fz ( c AC, b B, X c 6. Experimental ata A useful propert of SSBDDs is its abilit to provie fault collapsing in the moel. While in the gate-level escriptions we moel stuc-at faults at the interconnections between the gates, in SSBDD representations the faults are present at noes. For example, stuc-at-0 fault at a noe is moele with the 0-ege of the noe being constantl activate, regarless of the value of the variable labeling this noe. Each SSBDD noe represents a istinct path in the corresponing fanout-free circuit. B testing all the SSBDD noe faults we will consequentl test all the signal paths in the circuit an thus all the single stucat faults. This abilit of SSBDDs to implicitl moel logic level stuc-at faults is a ver important propert, which istinguishes it from other classes of BDDs. Table. Number of collapse an SSBDD faults in ISCAS85 circuits circuit faults collapse SSBDD c c c c c c c c Table compares the number of uncollapse faults, the number of stanar collapse faults an the number of SSBDD faults in the ISCAS 85 benchmar set. As we can see that reuction provie b collapsing in the SSBDD moel is about.5 times. While there exist more aggressive fault collapsing approaches the avantage of the SSBDD base collapsing over the traitional one is that it allows us at the same time to rise to a higher abstraction level of circuit moeling. In the traitional case we woul onl minimize the number of faults but woul still be woring at the level of logic gates. Table 2 presents the fault simulation results for two ifferent methos, parallel critical path tracing an euctive fault simulation [5], which were carrie out to compare the spee of gate-level an macro-level

6 simulation on SSBDDs. The simulation algorithms were compile b GNU C compiler using O option an experiments were run on a 366MHz SUN Ultra60 server using SUN Solaris 2.8 operating sstem. Table 2. Comparison of parallel critical path tracing with euctive fault simulation Circuit Vectors Parallel Critical Path Tracing Deuctive Fault Simulation Gate Macro Gate Macro c ,68 0,2,302 0,8 c ,385 0,56 4,567,662 c ,62 0,89 2,563,382 c ,573,002 4,657 2,754 c ,07,32 6,449 2,774 c ,835 2,493,207 4,888 c ,087 3,75 8,376 6,750 c ,65 0,82 3,224,392 c ,226 2,263 4,797 3,34 c ,04,482 7,54 2,283 T ,84 0,00 0,290 0,9 From Table 2 we see that the macro-level parallel critical path tracing metho outperforms the macrolevel euctive fault simulation in average 2-4 times. Here T024 represents a tree-lie circuit of 024 two input gates. So, we see that the avantage of the parallel critical path tracing methos increases with increasing of the tree-lie regions in circuits. Compare to the gate level simulation, the spee of the macro level critical path tracing is higher in average 2-6 times. In this version of the critical path tracing SW pacage we use parallel fault simulation for reconvergent fanout stems. When implementing the above iscusse parallel critical path tracing approach also for reconvergent fanout stems aitional increase in spee of simulation is expecte. 7. Conclusions A metho has been propose for macro-level parallel critical path fault tracing base on SSBDDs. Differentl from the nown critical path tracing approach partial Boolean ifferential base formulas were evelope which allow to generalize parallel critical path fault tracing beon the reconvergent fanout stems. Consierable increase in macro-level fault simulation base on using SSBDDs was shown compare to the plain gate-level simulation. Acnowlegements This wor has been supporte b the grants of Estonian Science Founation G5637, G5649 an G590 an Enterprise Estonia fune Technolog Development Center ELIKO project. References [] J.A.Waicuausi, E.B.Eichelberger, D.O.Forlenza, E.Linbloom an T.McCarth. Fault Simulation of Structure VLSI. VLSI Sstems Design, Vol.6, No.2, pp.20-32, 985. [2] B.Unerwoo, J.Ferguson. The Parallel Test Detect Fault Simulation Algorithm. Proc. International Test Conference, pp.72-77, 989. [3] M.Abramovici, P.R.Menon, D.T.Miller. Critical Path Tracing An Alternative to Fault Simulation. Proc. 20 th Design Automation Conference, pp. 2-5, 987. [4] K.J.Antreich, M.H.Schulz. Accelerate Fault Simulation an Fault Graing in Combinational Circuits. IEEE Trans. On Computer-Aie Design, Vol. 6, No. 5, pp , 987. [5] F.Maamari, J.Rajsi. A Metho of Fault Simulation Base on Stem Region. IEEE Trans. On Computer Aie Design, Vol. 9, No. 2, pp , 990. [6] H.K.Lee, D.S.Ha. An Efficient, Forwar Fault Simulation Algorithm Base on the Parallel Single Fault Propagation. Proc. International Test Conference, pp , 99. [7] S.C.Seth, L.Pan, V.D.Agrawal. Preict-Probabilistic Estimation of Digital Circuit Testabilit. Dig. Papers FTCS-5, June 985, pp [8] R. Ubar, Test Snthesis with Alternative Graphs, IEEE Design Test of Comp. Spring 996, pp [9] A. Jutman, A. Peer, J. Rai, M. Tomba, R. Ubar. Structurall snthesize binar ecision iagrams. 6th International Worshop on Boolean Problems, pp , Freiberg, German, Sept , [0] H.-T. Liaw, C.-S. Lin, On the OBDD-representation of general Boolean functions, IEEE Trans. on Computers, Vol. C-4, No. 6, pp , June 992. [] R.Ubar. Multi-value simulation of igital circuits with structurall snthesize BDDs. J. of Multiple Value Logic, Vol.4, 998, pp [2] R.Ubar, A.Jutman, Z.Peng. Timing simulation of igital circuits with BDDs. Proc. of DATE, 200, pp [3] A.Jutman, R.Ubar. Design error iagnosis in igital circuits with SAF moel. J. of Microelectronics Reliabilit. Vol.40, No.2, 2000, pp [4] A.Thase. Boolean Calculus of Differences. Springer Verlag, 98. [5] J.Rai, R.Ubar, S.Devaze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurall Snthesize BDDs. Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin Heielberg, 2005, pp