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1 Volume 4 Issue 05 May-2016 Pages ISSN(e): Website: DOI: DCT Compression of Test Vector in SoC Authors Ch. Shanthi Priya 1, B.R.K. Singh 2 1 PG Student,DVR & DR HS MIC College of Technology, Kanchikacherla, Krishna, AP, India, 2 Associate Professor,DVR & DR HS MIC College of Technology, Kanchikacherla, Krishna, AP, - spchatragadda5@gmail.com, bondilirk@gmail.com ABSTRACT This paper reports results on studies of the problem and demonstrates the feasibility of the suggested methodology with simulation runs on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits. When the storage nears it limit, they then try to reduce those files size to minimum by using data compression software. In this project i proposed a new algorithm for data compression, called DISCRETE COSINE transform. This algorithm will manipulates each bit of data inside file to minimize the size without losing any data after decoding to lossless compression. This basic algorithm is intended to be combining with other data compression algorithms to optimize the compression ratio. INTRODUCTION Recent advances in the process technology make more and more functions which are crammed into a single device. In modern devices Intellectual Property (IP) cores and several modules are integrated on a single chip. Billions of transistors are fabricated on a single wafer. Although increasing integration of transistors on a single chip produces robust design, more defects are produced accordingly. In this situation there is a need to test those designs. As the technology advances, huge volume of test data is needed to be tested. An important objective to realize through elaborate testing of very large scale integration (VLSI) circuits and systems is ensure that the manufactured products are free from defects and simultaneously guarantee that they meet deemed specifications. In addition, the information collected during the test process may help in an increase of the product yield by improving the process technology with consequent lowering of the production cost. The integrated circuit (IC) fabrication process involves various steps, viz., photolithography, printing, etching, and doping. In a real life environment, none of these steps is absolutely flawless and the unresolved imperfections may cause failure in the operation of the individual ICs. The introduction of VLSI technology gave rise to added complexity to the testing process of ICs, with resultant increase in the cost of electronic components. The problem of testing system-on-chip (SoC) ICs has also increased enormously due to the large numbers of intellectual property (IP) cores which are now being used on a single piece of silicon. Due to shrinking of the overall circuit geometry, sensitivity to performance variations has greatly increased but the individual components of the ICs must still be rigorously tested before being shipped to the customers. The testing undeniably improves the overall quality of the final product, although it has no relevance on the manufacturing excellence of the ICs. The testing assures the product imperfections only if implemented during the key phases in the development cycle. It can further be a strategy for validating the design and Ch. Shanthi Priya, B.R.K. Singh IJSRE Volume 4 Issue 5 May 2016 Page 5429

2 checking the processes involved. The various IP cores in an SoC are not readily accessible due to the complexity of the SoC and limited test pins. However, accessibility of a node that is either controllable or observable in a circuit can be increased using design-for-testability (DFT) strategies. Applying DFT reduces the test cost, enhances the quality of product, and makes the design characterization and test program implementation rather easy. To be able to effectively test these systems, every IP core must be duly exercised with a set of predetermined test patterns provided by the core vendor figure 1. For VLSI systems, because of higher storage requirements for the fault-free responses, the customary test processes thus become highly expensive, and therefore, alternate approaches are sought at minimizing the amount of needed storage or the test data volume. Built-in self-testing(bist) is a design methodology that has the capability of solving many of the problems otherwise encountered in testing digital systems. For testing an SoC, the test patterns are first generated and stored in a high-end computer. But, the increased variety of SoCs requires increased numbers of test patterns and frequent downloads of these test patterns into an automatic test equipment (ATE). The sizes of the test patterns can be in the order of several gigabytes, thereby taking a significant amount of time for downloading into ATE. For downloading the test vectors into ATE, a dedicated high speed bus is also a necessity. But, it still takes enormous amount of time for transferring data and ATE remains idle during this period, wasting valuable system resources. So, the overall performance of ATE is affected by the transfer time of test vectors. To improve the throughput of ATE, it is crucial to reduce the data transfer rate. A cost effective way to this end is to reduce the amount of data using some kind of data compression technique. EXISTING SCHEME Michael Burrows and David Wheeler released a research report in 1994 discussing work they had been doing at the Digital Systems Research Center in Palo Alto, California. Their paper, "A Block-sorting Lossless Data Compression Algorithm" presented a data compression algorithm based on a previously unpublished transformation discovered by Wheeler in The BWT is an algorithm that takes a block of data and rearranges it using a sorting algorithm. The resulting output block contains exactly the same data elements that it started with, differing only in their ordering. The transformation is reversible, meaning the original ordering of the data elements can be restored with no loss of fidelity. The BWT is performed on an entire block of data at once. Most of today's familiar lossless compression algorithms operate in streaming mode, reading a single byte or a few bytes at a time. But with this new transform, we want to operate on the largest chunks of data possible. Since the BWT operates on data in memory, you may encounter files too big to process in one fell swoop. In these cases, the file must be split up and processed a block at a time. Ch. Shanthi Priya, B.R.K. Singh IJSRE Volume 4 Issue 5 May 2016 Page 5430

3 PROPOSING SCHEME Figure 2 Discrete cosine transform (DCT) expresses a finite sequence of data points in terms of a sum of cosine functions oscillating at different frequencies. DCTs are important to numerous applications in science and engineering, from loss compression of audio and images to spectral methods for the numerical solution of partial differential equations. The use of cosine rather than sine functions is critical in these applications: for compression, it turns out that cosine functions are much more efficient (as described below, fewer functions are needed to approximate a typical signal), whereas for differential equations the cosines express a particular choice of boundary conditions. In particular, a DCT is a Fourier-related transform similar to the discrete Fourier transform (DFT), but using only real numbers. DCTs are equivalent to DFTs of roughly twice the length, operating on real data with even symmetry (since the Fourier transform of a real and even function is real and even), where in some variants the input and/or output data are shifted by half a sample. There are eight standard DCT variants, of which four are common. The most common variant of discrete cosine transform is the type-ii DCT, which is often called simply "the DCT", its inverse, the type-iii DCT, is correspondingly often called simply "the inverse DCT" or "the IDCT". Two related transforms are the discrete sine transforms (DST), which is equivalent to a DFT of real and odd functions, and the modified discrete cosine transforms (MDCT), which is based on a DCT of overlapping data. Like any Fourier-related transform, discrete cosine transforms (DCTs) express a function or a signal in terms of a sum of sinusoids with different frequencies and amplitudes. Like the discrete Fourier transforms (DFT), a DCT operates on a function at a finite number of discrete data points. The obvious distinction between a DCT and a DFT is that the former uses only cosine functions, while the latter uses both cosines and sines (in the form of complex exponentials). However, this visible difference is merely a consequence of a deeper distinction: a DCT implies different boundary conditions than the DFT or other related transforms. The Fourier-related transforms that operate on a function over a finite domain, such as the DFT or DCT or a Fourier series, can be thought of as implicitly defining an extension of that function outside the domain. That is, once you write a function as a sum of sinusoids, you can evaluate that sum at any, even for where the original was not specified. The DFT, like the Fourier series, implies a periodic extension of the original function. A DCT, like a cosine transform, implies an even extension of the original function. DCT, like a cosine transform, implies an even extension of the original function. Illustration of the implicit even/odd extensions of DCT input data, for N=11 data points (red dots), for the four most common types of DCT (types I-IV). However, because DCTs operate on finite, discrete sequences, two issues arise that do not apply for the continuous cosine transform. Before starting hardware assembling, we use software application to simulate the algorithm. The purpose of using software application for simulation, it is to verify the correctness of the logic function. Skipping this step will result in frustration in finding errors during hardware assembling. It is extremely difficult to locate the error during the VLSI design. The following is the software application using Java language to manipulate the DCT algorithm Ch. Shanthi Priya, B.R.K. Singh IJSRE Volume 4 Issue 5 May 2016 Page 5431

4 BLOCK DIAGRAM INPUT SIGNAL DCT COMPRESSION IDCT DATA RECONSTRUCTION SIGNAL Input Signal: A test vector is considered as ATE input which compressed 8-bit data. DCT Block: The 8-bit test vectors were compressed using this block is spitting the data into high frequency and low frequency automatically along with transformation. Compressed Data: A compressed data vector will obtained at this point. IDCT: To recover the compressed data without error IDCT is used. Reconstruction Signal: Test vector is reconstructed. SIMULATION RESULT Figure 3 shows simulation output. Here A1 to A8 are the Registers, B1 to B8 are also Registers. C1 to C8 are the control signals. SMux is for selection. We give an input data into A1 to A8 and B1 to B8 some 32-bits(20). Same as C1 to C8 for control signals. We got a output from Out[3:0] 4-bits(3). If Done[3:0] is 0000, the compression was completed. If Done[3:0] is 1111, the compression not completed. CONCLUSION & FUTURE SCOPE ATE needs to be simple in size and efficient in data verification. BWT got a complex architecture to simply and enhance the compression of data DWT has been used and proved as an efficient scheme of compression and fast in comparing with BWT. Even though we had a little bit error in reconstruction in data. So, we can access encoding scheme in future. REFERENCES 1. K. Basu and P. Mishra, Test data compression using efficient bitmask and dictionary selection methods, IEEE Trans. VLSI Syst., vol. 18, no. 9, pp , Sep S. Sivanatham, M. Padmavathy, S. Divyanga, and P. V. Anitha Lincy, System-on-a-chip test data compression and decompression with reconfigurable serial multiplier, Int. J. Eng. Technol., vol. 5, no. 2, pp , 2013 Ch. Shanthi Priya, B.R.K. Singh IJSRE Volume 4 Issue 5 May 2016 Page 5432

5 3. S. Saravanan, R. V. Sai, and H. N. Upadhyay, Higher test pattern compression for scan based test vectors using weighted bit position based method, ARPN J. Eng. Appl. Sci., vol. 7, no. 3, pp , A. El-Maleh, S. Al Zahir, and E. Khan, A geometric-primitives-based compression scheme for testing system-on-a-chip, in Proc. VLSI Test Symp., 2001, pp S. Saravanan and H. N. Upadhyay, Adapting scan based test vector compression method based on transition technique, Proc. Eng. Elsevier Sci., vol. 30, no. 20, pp , M. Nelson, Data compression with the Burrows Wheeler transform, Dr. Dobb s J., vol. 9, pp , Sep M. Burrows and D. J. Wheeler, A block-sorting lossless data compression algorithm, Digit. Syst. Res. Center, Palo Alto, CA, USA, Tech. Rep. 124, S. W. Golomb, Run-length encoding, IEEE Trans. Inf. Theory, vol. IT-12, no. 3, pp , Jul J. Ziv and A. Lempel, A universal algorithm for sequential data compression, IEEE Trans. Inf. Theory, vol. IT-23, no. 3, pp , May T. Skopal, ACB compression method and query preprocessing in text retrieval systems, in Proc. DATESO, 2002, pp Hamzaoglu and J. H. Patel, Test set compaction algorithms for combinational circuits, in Proc. Int. Conf. Comput.-Aided Des., 1998, pp Ch. Shanthi Priya, B.R.K. Singh IJSRE Volume 4 Issue 5 May 2016 Page 5433