CHAPTER 1 INTRODUCTION

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1 CHAPTER 1 INTRODUCTION Rapid advances in integrated circuit technology have made it possible to fabricate digital circuits with large number of devices on a single chip. The advantages of integrated circuits are reduced system cost, better performance and reliability. These advantages would be lost unless integrated circuit devices can be economically tested. Testing is one of the important fields, which validates the functionality of any manufacturing process. Manufacturing testing is essential to reduce the risk of shipping a defective product and is a process where circuit inputs are exercised using certain patterns and the resulting response is compared to the golden response to eliminate the defective parts [l]-[5]. The primary objective of this thesis is to develop new algorithms for test generation and simulation of stuck-at faults in sequential circuits using Genetic Algorithms and Fuzzy Logic. This chapter provides a brief introduction to testing and simulation of integrated circuits. Major contributions of the thesis are summarized and the organization of the thesis is outlined at the end of the chapter. 1.1 Design of Integrated Circuits Very Large Scale Integrated Circuits (VLSI) is the fabrication of millions of components on the same chip and is an integral part of modem electronic systems. Due to the significant improvements in the integrated circuit (IC) manufacturing

2 2 technology, the integrated circuit performance and density have increased tremendously. For example, today microprocessors with internal clocks closer to 1 GHz and containing more than 25 million transistors are manufactured [6]. The design of such circuits is a complicated and time-consuming process. The key to the success of VLSI technology lies in the development of powerful design tools and software systems that help the designer to produce an integrated circuit chip. Fig. 1.1 shows the various phases of the IC design process. The design refers to the process of transforming abstract ideas or behavioural specifications of a system into a manufacturable assembly of known parts. In order to reduce the complexity of the design process, several intermediate levels of abstractions are introduced and computer-aided design (CAD) tools are used during all phases of the design process. The three important steps in VLSI design process are simulation, synthesis and layout. Simulation verifies the functionality, logic synthesis translates the design to lower levels of abstraction and layout or physical design takes circuit schematics and creates masks for fabrication steps. The first task in the IC design process consists of casting an idea into model, which captures the function that the circuit will perform. The design can start at behavioural, logic or circuit levels of abstraction. Design typically starts at very high levels of abstraction using some high level Hardware Description Languages (HDL) such as Verilog or VHSIC hardware description language (VHDL). Simulators based on HDL models are used lo venly die design. I lien (lie 11DL speeiliealions are synllicsi/cd using a given library of components. The next step is the circuit design phase, which is influenced

3 3 by the circuit performance, power, area, noise, reliability, testability and time to market [6]-[8]. Timing Accuracy LOW Cost of Fixing Errors LOW HIGH HIGH Fig. 1.1: Phases in Integrated Circuit Design Following the design entry, verification and synthesis steps, is the task of layout generation, which provides all the information necessary for generating masks for wafer fabrication. Layout must be verified to ensure that they conform to design rules before the masks are generated. Test patterns are necessary to test the chip once they are fabricated and these tests may be generated once the design entry is completed. An Automatic Test Generator (ATG) may be used for this purpose. A fault simulator is used to evaluate the quality of the tests generated in terms of fault coverage [ 1 ][7].

4 4 As the design moves from the abstract architectural level to the physical representation or fabrication, the complexity of the design increases. There could be several iterations of each phase during the IC development to ensure quality and performance. During the various iterations several CAD tools assist in translating the design into an IC. For example, the formal verification tools ensure that the translation process does not introduce errors. Timing analysis tools measure the design s performance at various stages. Several analysis tools such as those for power estimation and floor planning aid the process of creating the IC. Even though CAD techniques have reached fairly good level of maturity in many areas, as technology improves and chip performance increases, there is a need for new techniques and efficient methods for design and lest of integrated circuits. For example, design implementation s delay is shifting towards domination by interconnect delay rather than gate delay. The design s timing is unpredictable until the designers determine the layout and interconnect between the cells. Design and test methodologies are changing to compensate this shift in delay to keep the design iterations to a minimum. The more dense integration of nanometer technologies also amplifies cross talk issues [9], 1.2 Testing of Integrated Circuits Tests may fall into two main categories, the functionality test and manufacturing test. The functionality test verifies that the chip performs its intended function. These tests are usually used early in the design cycle to verify the functionality of the integrated circuit. Manufacturing test involves the development

5 5 of test suite to screen out defective parts before shipping the product to customers. This is an important stage of integrated circuit development as it affects the quality of the product. In any manufacturing process physical defects are almost invariably introduced. A number of manufacturing defects might occur during fabrication or during accelerated life testing. Typical defects include layer to layer shorts, discontinuous wire, the thin-oxide shorts to substrate or well, pin holes in oxide layer, surface defects due to dust particles and inputs floating or outputs disconnected [10]. The testing process detects the physical defects produced during fabrication of an integrated circuit chip. Testing of a die/chip can occur at the wafer level, packed chip level, board level, system level or in the field. The cost of identifying a faulty component during its life cycle is lowest before it is packed [2][6]. This cost increases rapidly as the component becomes a part of a larger system. Due to the complexity of the IC manufacturing process, a number of defects might occur during fabrication and hence no process can guarantee 100% yield. Fig. 1.2 [11] illustrates that the costs associated with designing the transistor continue to shrink and testing costs are on the rise. If these trends do not change, in future the cost of testing a transistor might become more than the cost of designing the transistor. Therefore, testing is a very important aspect of any integrated circuit manufacturing system. The testing process involves the application of test vectors to the circuit and a comparison of the circuit response with the expected response. Any discrepancy in the output response indicates the presence of fault. Automatic test equipment is used

6 6 to run tests typically generated by test process. If incorrect behaviour is detected, a second goal of testing may be carried out to diagnose or identify the location of the fault. In this thesis the focus is on the detection of faults. Cost per transistor (cents) o o o o Silicon manufaturing Test equipment depreciation Fig. 1.2: Trends derived from NTRS Given today s very large designs, the test process relies heavily on automation. Various test development automation tools for the tasks of design for testability, test pattern generation and pattern grading have been used to reduce the bottleneck in the products time to market [12], The focus of this thesis is on Automatic Test Pattern Generation (ATPG). Automatic test pattern generation is one of the most difficult problems for electronic design automation and has been a popular research topic. The objective of automatic test pattern generation is to

7 7 obtain a set of test vectors that will detect any defect that might occur in the manufacturing process. However, covering all potential defects would be very difficult and would require an inordinate number of test vectors. Therefore automatic test pattern generating tools operate on an abstract representation of defects referred to as faults and model a subset of potential faults. The faults in digital circuits are classified as logic or parametric faults. A logic fault causes the logic function of the circuit, on an output signal to be changed to some incorrect function. Parametric faults are the faults, which alter the magnitude of the circuit parameters causing changes in speed of operation or the levels of voltages and currents [1]. This thesis, deals with the detection of logical faults. The effects of manufacturing defects are represented at the logic level using a fault model. Fault models can describe the faults at different abstraction levels. The common abstraction level is the gate level. Most fault models assume that the circuit contains only a single fault, as the number of potential multiple fault combinations is so large that test generation becomes infeasible. The widely used gate level fault model for digital circuits is the single stuck-at fault model. This model assumes that any physical defect in a digital circuit results in a node in the circuit being fixed either at logic 0 or logic 1 and appropriately called stuck-at-0 and stuck-at-1 respectively [1]-[5][13]. These faults occur most frequently in Complementary Metal Oxide Semiconductor (CMOS) process technology due to thin oxide shorts (the n transistor gate to VSs or the p transistor gate to VDD) or metal to metal shorts [10].

8 8 Testing is an essential part of any VLSI manufacturing system. For a manufacturer to ensure product quality, it is necessary to separate bad circuits from the good ones. The testing process detects the physical defects produced during fabrication. Test generation for sequential circuits is a search problem over large vector space, proportional to the number of inputs and number of states and is a Non deterministic Polynomial (NP) complete problem [1][4][12]. 1.3 Logic Simulation Simulation plays a crucial role in the design and test of integrated circuits. Digital logic simulation involves the construction of a computer model of the hardware that is being designed and execution of the model for a set of input signals and observation of the output signals. Simulation replaces the prototype with software, which can be analysed and modified easily. The logic simulation may be used to verify that the operation of the system is correct independent of the initial state, not sensitive to some variations in the delays, free of critical races, oscillations, illegal input conditions and hang-up states [1] [14], Logic simulators are also used for fault analysis, to determine the faults detected by a given test sequence or vector. Simulation can be done at various levels of abstraction: Devicelevel, circuit-level, switch-level, gate-level, register-transfer level and system level. This thesis focuses on the gate level model. Gate level simulators are generally classified according to the type of internal model that they process. The basic methods to simulate a circuit at the gate level are compiler driven simulation and event driven simulation. The output of any

9 9 physical gate will take sometime to change after an input has changed. Delays involved can affect the correct functioning of the circuit, typically when the circuit has asynchronous parts. Hence an accurate modelling of the delay is important [14]-[16], Compiler driven simulation is the one that executes a compiled code model and is quite faster but can only deal with limited delay models. The compiled code model is generated such that the computations of values proceed level by level. Levelling is the process of determining the order in which the signals carried by the net will be computed. The compiled simulator evaluates all- the elements in the circuit for every input vector. This type of simulation is not accurate for asynchronous circuits whose operation is based on certain delay values. An event driven simulator uses a structural model of a circuit to propagate events and can deal with very general delay models at the expense of more computer time. The event driven simulation is motivated by the fact that normally very few gates are switching simultaneously and that recomputing signal propagation through all the gates at each time instant, as in compiler-driven simulation amounts to many unnecessary calculations. A signal change is called an event and only those signals that are actually changing are recomputed. Event driven simulation can process real time inputs, that is, inputs whose times of changes are independent of the activity in the simulated circuit. This is an important feature for design verification testing, as it allows accurate simulation of nonsynchronized events such as interrupts or competing requests for use of a bus [14]. In this thesis, the compiler driven simulation is used for the simulation of

10 10 synchronous sequential circuit and an event driven simulation technique based on fuzzy delay model is proposed and used to evaluate the test patterns generated for asynchronous sequential circuits. 1.4 Scope and Objectives In this thesis, algorithms for test generation and simulation of stuck-at faults in synchronous and asynchronous sequential circuits using Genetic Algorithms (GA) [17] and Fuzzy Logic [18] are proposed and investigated. The contributions of this thesis are: Two new crossover operators: Weight based cross over (WCO) and Sequence based crossover (SCO) operators are proposed for test generation and the effectiveness of the operators on the automatic test pattern generation of sequential circuits are analysed. The effect of the adaptive probabilities [19] of crossover on ATPG is also investigated. A two phase ATPG based on Guided Genetic Algorithm (GGA) [20] for synchronous sequential circuits is formulated and tested. FDSIM: A simulation algorithm based on novel fuzzy delay model [6[[21 ][22] for asynchronous sequential circuits is developed. The applicability of FDSIM for testing asynchronous sequential circuits using synchronous test model [23] is studied.

11 11 ATPG algorithm based on Genetic Algorithms for asynchronous sequential circuits is presented and analysed. The FDSIM is used to validate the test patterns generated. A two phase ATPG for asynchronous sequential circuit in a GGA framework is developed and investigated. The performance of the proposed algorithms, are tested using standard benchmark circuits. The timing information for the components in the circuit is derived using a 1.0 micron standard cell library [24]. Good fault coverage and test sets are obtained for most of the benchmark circuits. 1.5 Organisation of this Thesis This thesis starts with a review of the background areas of test generation for combinational and sequential logic circuits in chapter 2. Since the thesis deals with the test generation of both synchronous and asynchronous sequential circuits, the motivation for using asynchronous circuits is presented at the end of chapter 2. Chapter 3 discusses the proposed new crossover operators for GA based ATPG. Test generation results are presented for the ISCAS 89 benchmark circuits. Chapter 4 describes the Guided Genetic Algorithm and the proposed ATPG for synchronous sequential circuits using GGA. The following chapters deal with simulation and testing of asynchronous sequential circuits.

12 12 Chapter 5 gives an introduction to fuzzy delay model that can model uncertainty related to manufacturing anomalies. Then the proposed fuzzy delay model based simulation algorithm (FDSIM) for asynchronous circuits is illustrated. An ATPG algorithm based on synchronous model is described in chapter 6 and the FDSIM is used to validate the patterns generated. SIS benchmark circuits are used to illustrate the method. The simulation based test generation algorithms for asynchronous sequential circuits are presented in chapter 7. Experimental results on the SIS benchmark circuits are given. Chapter 8 concludes this thesis with a summary of the contributions and suggestions for further research.