E Flash Program Procedure via JTAG AN 0136 Jun 15, 2015

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1 1 Scope This document describes flash access procedures via JTAG interface. The compliance of the rules below guaranties the reliable programming of the E TEN TEN LN24 D5 JTAG MASTER TCK TDI +5V R 1k TCK TDI ELMOS E C 1uF +5V +24V TDO TDO LN0 Test enable by +5V on pin TEN, Power supply 5V on pins D5/LN0, FLASH program supply 24V on pins LN24/LN0. 2 References [JTAG] [25DS0163E.xx] IEEE Std (IEEE Standard Test Access Port and Boundary-Scan Architecture) E Data sheet - Smoke Detector Controller, 3 Basic Flash Information The flash standard cell is up to 1K words FLASH Memory with 16 bit words length. It is a matrix of flash cells organized in rows (word lines) and columns (bit lines). Four adjoining rows builds a page. The pages may be erased individually. 3.1 Flash Addressing Modification of FLASH Memory data (Erasing or Programming) is block-wise. Minimum block to program data is word line. Minimum block to erase data is page. Table 1. FLASH addressing Flash Address Bus [11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] unused word line address word address within word line unused page number word line number within page word address within word line 3.2 Flash control signals The 9 control signals define the flash operating mode (see table 2). Table 2. FLASH control signals Signal name CR Register Bit Function AUTOINC [12] Enable FLASH Address Automatic Increment FTEST [10] Flash Test Enable (Active = 1) FSEL [8] Select FLASH Memory ( Active = 1) PGM [7] Set Program Mode ERASE [6] Set Erase Mode VERIFY [5] Set Verify Read Mode for programmed cell state. VERIFY1 [4] Set Verify Read Mode for erased cell state. HVEN [3] High Voltage Enable MASSER [1] Set erase all. The next erase cycle will change the whole array. 1/12

2 3.3 Flash Operating modes Read In the Read mode, the flash cell behaves like a random access memory. To reach the read mode the FSEL and FTEST control signals must be set high, while other control signals must be kept low Write Setting PGM or ERASE high opens write access to embedded data register. In the Write Mode only exact 8 data words can be stored in the internal data register. In the followed high voltage phase of the program cycle the content of this register will be transferred into the selected word line of the array Mass Erase Before the memory is programmed, it must be erased. There are two erase modes implemented in the flash: mass erase and page erase. Mass Erase will erase the complete flash area. In page erase mode only selected page will be erased. The verification of the erased region is necessary to guarantee that no any disturbances was happen during the erase procedures. Use the following procedure to erase the entire FLASH memory: Set the following bits: FSEL, ERASE, MASSER, and FTEST for mass erase Write dummy data 0x0000 to be erased addressed by A[10:0]= 0x000. Set the HVEN bit and wait for 10ms. That will apply the erasing HV pulse to the cells. There are no internal timer inside the flash. Duration of the erasing pulse is defined externally Clear the HVEN bit and wait for 500us (mass erase) for the high voltages to dissipate. Clear the ERASE and MASSER bits and Set VERIFY1 bit Wait for 50us before the verification mode is settled. Read out the erased data and compare the data with 0. Repeat the steps above if the reliable erased state is not reached (max. 2 times) Clear the VERYFY1 bit After 50us the memory can be accessed in read mode. The erased cell state is Programming The programming procedure consist of two steps: the data programming and data verification and must be used for the customer programming in the factory. The purpose of the verification is to ensure that data has been programmed with sufficient margin for long-term data retention and no any disturbances was happen during the programming procedure. Programming of the FLASH memory is done on a block basis. A block consists of 8 consecutive words addressed with A[10:3] one word line. To program and verification read the flash memory, use the following algorithm. Set the PGM, FTEST, and FSEL bits Write 8 words of data to the specified range within one selected word line. The data is latched in the FLASH Write Register and ready to be programmed. Set the HVEN signal and wait for 300µs. That applies the HV programming pulse to the cells. Clear the HVEN signal and wait for 10µs for the high voltages to dissipate. Set the VERIFY signal Clear the PGM signal Read back the data in verification mode from the range within the latched word line. Clear the VERIFY signal If some cells within the range haven t been programmed sufficiently (i.e. in VERIFY mode they are still read as 0 ), then repeat the Program operation ( max. 5 time ) Repeat the programming steps above for the all data to be programmed Wait 20µs before read the data in normal read mode. Note: The PGM bit should be cleared only after the VERIFY bit is set (not in a single clock cycle). In this case no additional wait cycle after set VERIFY is needed to settle the reference voltage. 2/12

3 Program Flash Initialize Attempt counter to Zero Set PGM Write Data to Selected Word Line Set HVEN Wait 300us Clear HVEN Wait 10us Set VERIFY Clear PGM Clear VERIFY Verify Read of Word Line Data Increment Attempt Counter Read Out Data Equal To Write Data? No Attempt Counter >5? No Yes Clear VERIFY Yes Programming Operation Failed All Data Programmed? Yes No Increment Word Line Address Programming Operation Complete Figure 1. Flash Programming Algorithm. 3/12

4 4 JTAG Interface The JTAG is the Elmos standard access interface for the flash programming procedures. The flash cell can be directly accessed via TDI, TCK, and TDO when JTAG interface is activated. Each product can have its own activating procedure. This document describes the flash access procedures after JTAG is activated. The Flash access mode depends from the appropriated JTAG instruction is loaded into the JTAG instruction register (see examples later on). 4.1 JTAG Overview The used JTAG signals are described here: Table 3. JTAG Signals Pin Dir. Usage TEN IN Signal to control the JTAG enable. IN Signal to control the JTAG state machine TCK IN JTAG clock input *) TDI IN JTAG data input TDO OUT JTAG data output *) Max. TCK frequency is 1 MHz FLASH JTAG Registers IR 8 Bit JTAG instructions register CR 14 Bit JTAG Flash Control register DR16 16 Bit JTAG Flash Data register AR12 12 Bit JTAG Address register Flash JTAG Instructions 0xA2 access to Flash Control Register 0xA3 16 Bit Flash data read 0xA4 16 Bit Flash data write Flash Control Register The signals in JTAG flash control register (CR) control the flash operation modes. The typical partitioning of this register is shown in the table below and will be used in all followed JTAG access sequences. Bit NB Name - AUTOINC 0 FTEST 0 FSEL PGM ERASE VERIFY VERIFY1 HVEN 0 MASSER 0 4/12

5 4.2 JTAG TAP Controller For an overview the TAP controller flow is described in the following figure: Figure 2. JTAG TAP Controller States 4.3 E JTAG Access Procedures Before FLASH procedures can be used JTAG interface itself should be activated. FLASH test access activated in three followed steps: 1) enable test mode by force TEN pin with +5V; 2) initialization of JTAG TAP by five consecutive TCK impulses with high; 3) set FLASH access mode (See 5.1.) Enable test mode Only if TEN=5V than, TCK, TDI, and TDO will be activated for JTAG interface. 5/12

6 4.3.2 Initialization of JTAG TAP After test mode activation JTAG TAP Controller can be in any state. To have definite state of TAP Controller it is necessary to initialize it by five consecutive TCK impulses with high and two TCK impulses with low (see following figure). After described above sequence TAP Controller will be in Run-Test/Idle. TCK TDI 4.4 JTAG Macros To simplify this documentation some high-level macros are used to describe JTAG access. This macro notation will be used in the pseudo-code examples WAIT (n) MACRO The macro WAIT has to guaranty a delay of n µs ( microseconds) between JTAG operations IR_SHIFT (cmd) MACRO Figure 3. JTAG initialization by keeping = 1 five TCK periods This macro loads a desired JTAG instruction into the JTAG instruction register (IR) of the target device. This register is 8 bits wide with the least-significant bit (LSB) shifted in first. Each instruction bit is captured from TDI by the target on the rising edge of TCK. Figure IR_SHIFT Macro shows how to load an instruction into the JTAG IR register: LSB MSB TCK TDI IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 TDO ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Figure 4. IR_SHIFT Macro DR_SHIFT n (data) MACRO This macro loads n-bit data into a JTAG data register (DR). The data is shifted, most-significant bit (MSB) first, into the targets TDI input. Each bit is captured from TDI on a rising edge of TCK. At the same time, TDO shifts out the previously captured/ stored value in the addressed data register. A new bit is present at TDO with a falling edge of TCK. The next figure shows how to load a 16-bit word into the JTAG DR and to read out a stored value via TDO. DR_SHIFT16 is used to access a 16 bit wide data register. DR_SHIFT14 is used for access to control register. 6/12

7 The figure below shows the behaviour of the JTAG DR_SHIFT16 macro: MSB LSB TCK TDI D15 DI14 DI13 DI12 DI11 D10 D9 D8 DI4 DI3 DI2 DI1 DI0 TDO DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DO4 DO3 DO2 DO1 DO0 Figure 5. DR_SHIFT16. NOTE: The data on the TDO is coming from the previous DR_SHIFT sequence. For example: 1. DR_SHIFT16(D0) shifts 16bit data D0 into JTAG data register, TDO output is undefined, 2. DR_SHIFT16(D1) shifts the next data D1 into register, TDO output D0, 3. DR_SHIFT5(DR) shifts 5bit data DR into JTAG data register DR1 4. DR_SHIFT14(DR) shifts 14bit data DR into JTAG data register DR2 or FLASH CR DAR_SHIFT28 (address, data) MACRO This macro loads 16 bit data and 12 bit address into a JTAG data register. The data is shifted first. The next figure shows how to load data/address into the JTAG register and to read out a stored value via TDO. TCK MSB MSB LSB LSB TDI DI15 DI14 DI13 DI2 DI1 DI0 A11 A10 A9 A2 A1 A0 TDO DO15 DO14 DO13 DO2 DO1 DO0 AO11 AO10 AO9 AO2 AO1 AO0 Figure 6. DAR_SHIFT28 for 16Bit data and 12Bit address NOTE: A[11] = 0 NOTE: The data on the TDO is coming from the previous DR_SHIFT sequence. For example: 1. DAR_SHIFT28(A0,D0) shifts address A0 and data DI0 into JTAG data register, TDO output is undefined, 2. DAR_SHIFT28(A1,D1) shifts the next address and data into register, TDO output A0, D0. 7/12

8 5 Flash JTAG Access Procedures This section demonstrates the typical operations by providing example pseudo-code sequences using the defined macros. 5.1 FLASH Initialization Sequence /* */ /* SET FLASH ACCESS MODE */ /* */ IR_SHIFT(0xCC); DR_SHIFT5(0x16); DR_SHIFT5(0x0); DR_SHIFT5(0x12); IR_SHIFT(0xC1); DR_SHIFT14(0x00AC); 5.2 JTAG Read Sequence /* */ /* INPUT: PstrtADDR - page start address */ /* PendADDR - page end address */ /* OUTPUT: none */ /* Variable: ADDR current flash address */ /* */ IR_SHIFT(0xA2); /* Setup IR register access to CR*/ DR_SHIFT14(0x0540); /* Setup CR register - set ERASE */ IR_SHIFT(0xA4); /* Setup IR register - access to DR for writing */ DAR_SHIFT28(PADDR,0x0000); /* Set page address and any data, ignore output values */ DR_SHIFT14(0x0548); /* Setup CR register - enable HV pulse */ WAIT(10000); /* Wait 10 ms for page erase */ DR_SHIFT14(0x0540); /* Setup CR register - reset HV pulse */ WAIT(100); /* Wait 100 us for HV dissipation after page erase */ DR_SHIFT14(0x0500); /* Setup CR register set default FSEL & FTEST*/ DR_SHIFT14(0x0510); /* Setup CR register - set VERIFY1 */ WAIT(50); /* Wait 50us for setup the reference voltage high*/ /* The next command sets start address for internal Flash address counter. After that operations with autoincrement are provided - they are faster. The first read out value is ignored. Write data is not interesting - 0x0000 is sent*/ DAR_SHIFT28(PstrtADDR,0x0000); DR_SHIFT14(0x1510); /* Setup CR register set autoincrement */ DR_SHIFT16(Ign_Data); /* Dummy read */ /* Read array and compare the data with 0x0000 */ for (ADDR=PstrtADDR;ADDR<=PendADDR;ADDR++) DR_SHIFT16(DataOut[ADDR]); if DataOut!= 0x0000 repeat the erase sequence max. 2 times; DR_SHIFT14(0x0500); /* Setup CR register - set default FSEL & FTEST */ WAIT(100); /* Wait 100us before read*/ 8/12

9 5.3 JTAG Erase Sequences JTAG Mass Erase Sequence /* */ /* INPUT: none */ /* OUTPUT: none */ /* Variable:ADDR current flash address */ /* */ IR_SHIFT(0xA2); /* Setup IR register access to CR*/ DR_SHIFT14(0x0542); /* Setup CR register - set MER and ERASE */ IR_SHIFT(0xA4); /* Setup IR register - access to DR for writing */ DAR_SHIFT28(0x0000,0x0000); /* Set some dummy address and data, ignore output values */ DR_SHIFT14(0x054A); /* Setup CR register - enable HV pulse */ WAIT(10000); /* Wait 10 ms for mass erase */ DR_SHIFT14(0x0542); /* Setup CR register - reset HV pulse */ WAIT(500); /* Wait 500 us for HV dissipation after mass erase */ DR_SHIFT14(0x0510); /* Setup CR register - set VERIFY1 */ WAIT(50); /* Wait 50us for setup the reference voltage high*/ /* The next command sets start address for internal Flash address counter. After that operations with autoincrement are provided - they are faster. The first read out value is ignored. Write data is not interesting - 0x0000 is sent*/ DAR_SHIFT28(0x0000,0x0000); DR_SHIFT14(0x1510); /* Setup CR register set autoincrement */ DR_SHIFT16(Ign_Data); /* Dummy read */ /* Read array and compare the data with 0x0000 */ for (ADDR=0x0000;ADDR<=FLendADDR;ADDR++) DR_SHIFT16(DataOut[ADDR]); if DataOut!= 0x0000 repeat the erase sequence max. 2 times; DR_SHIFT14(0x0500); /* Setup CR register - set default FSEL & FTEST */ WAIT(100); /* Wait 100us before read*/ 9/12

10 5.3.2 JTAG Page Erase Sequence /* */ /* INPUT: PstrtADDR - page start address */ /* PendADDR - page end address */ /* OUTPUT: none */ /* Variable: ADDR current flash address */ /* */ IR_SHIFT(0xA2); /* Setup IR register access to CR*/ DR_SHIFT14(0x0540); /* Setup CR register - set ERASE */ IR_SHIFT(0xA4); /* Setup IR register - access to DR for writing */ DAR_SHIFT28(PADDR,0x0000); /* Set page address and any data, ignore output values */ DR_SHIFT14(0x0548); /* Setup CR register - enable HV pulse */ WAIT(10000); /* Wait 10 ms for page erase */ DR_SHIFT14(0x0540); /* Setup CR register - reset HV pulse */ WAIT(100); /* Wait 100 us for HV dissipation after page erase */ DR_SHIFT14(0x0500); /* Setup CR register set default FSEL & FTEST*/ DR_SHIFT14(0x0510); /* Setup CR register - set VERIFY1 */ WAIT(50); /* Wait 50us for setup the reference voltage high*/ /* The next command sets start address for internal Flash address counter. After that operations with autoincrement are provided - they are faster. The first read out value is ignored. Write data is not interesting - 0x0000 is sent*/ DAR_SHIFT28(PstrtADDR,0x0000); DR_SHIFT14(0x1510); /* Setup CR register set autoincrement */ DR_SHIFT16(Ign_Data); /* Dummy read */ /* Read array and compare the data with 0x0000 */ for (ADDR=PstrtADDR;ADDR<=PendADDR;ADDR++) DR_SHIFT16(DataOut[ADDR]); if DataOut!= 0x0000 repeat the erase sequence max. 2 times; DR_SHIFT14(0x0500); /* Setup CR register - set default FSEL & FTEST */ WAIT(100); /* Wait 100us before read*/ 10/12

11 5.3.3 JTAG Programming sequence /* */ /* INPUT: word line start address (WlstrtADDR), */ /* word line end address (WlendADDR), */ /* input data array (data[addr]) */ /* OUTPUT: read out data array (DataOut[ADDR]) */ /* */ STRT_CP: DR_SHIFT14(0x0580); /* Setup CR register word line programming */ IR_SHIFT(0xA4); /* Setup IR register - access to DR for writing */ /* First data shift command sets also start address for internal Flash address counter. After that operations with autoincrement are provided */ DAR_SHIFT28(WLstrtADDR, data[wlstrtaddr]); DR_SHIFT14(0x1580); /* Setup CR register - set autoincrement*/ IR_SHIFT(0xA4); /* Setup IR register - access to DR for writing */ /* Enter from 0 to 7 values for word line - first value was already entered before */ for (ADDR=WLstrtADDR+1; ADDR<=WLendADDR; ADDR++) DR_SHIFT16(data[ADDR]); DR_SHIFT14(0x0588); /* Setup CR register - enable HV pulse */ WAIT(300); /* Wait 300 us for word line programming */ DR_SHIFT14(0x0580); /* Setup CR register - reset HV pulse */ WAIT(10); /* Wait 10us for HV dissipation after programming*/ DR_SHIFT14(0x05A0); /* Setup CR register - set VERIFY */ DR_SHIFT14(0x0520); /* Setup CR register - reset PGM */ /* The next dummy read command will set start address for internal Flash address counter. After that operations with autoincrement are provided - they are faster. The first read out value is ignored. It comes from previous address. Write data will be ignored, 0x0000 is sent*/ DAR_SHIFT28(WLstrtADDR,0x0000); DR_SHIFT14(0x1520); /* Setup CR register - set AUTOINC and VERIFY*/ DR_SHIFT16(Ign_Data); /* Dummy read */ /* Read upto 8 values for wordline and compare it with expected value*/ for (ADDR=WLstrtADDR; ADDR<=WLendADDR; ADDR++) DR_SHIFT16(DataOut[ADDR]); if DataOut!= expected data repeat the sequence from STRT_CP for max.5 time DR_SHIFT14(0x0500); /* Setup CR register - set default FSEL & FTEST */ WAIT(20); or GOTO STRT_CP; /* Wait 20us before read or repeat the sequence above for the next word line */ 11/12

12 Usage Restrictions Elmos Semiconductor AG provide the E Demonstration Board simply and solely for IC evaluation purposes in laboratory. The Kit or any part of the Kit must not be used for other purposes or within non laboratory environments. Especially the use or the integration in production systems, appliances or other installations is prohibited. The pcb s are delivered to customer are for the temporary purpose of testing, evaluation and development of the Elmos IC s only. Elmos will not assume any liability for additional applications of the pcb. Disclaimer Elmos Semiconductor AG shall not be liable for any damages arising out of defects resulting from (1) delivered hardware or software, (2) non observance of instructions contained in this document, or (3) misuse, abuse, use under abnormal conditions or alteration by anyone other than Elmos Semiconductor AG. To the extend permitted by law Elmos Semiconductor AG hereby expressively disclaims and user expressively waives any and all warranties of merchantability and of fitness for a particular purpose, statutory warranty of non-infringement and any other warranty or product liability that may arise by reason of usage of trade, custom or course of dealing. Elmos Semiconductor AG Headquarters Heinrich-Hertz-Str Dortmund Germany Phone + 49 (0) Fax + 49 (0) sales-germany@elmos.com Note Elmos Semiconductor AG (below Elmos) reserves the right to make changes to the product contained in this publication without notice. Elmos assumes no responsibility for the use of any circuits described herein, conveys no licence under any patent or other right, and makes no representation that the circuits are free of patent infringement. While the information in this publication has been checked, no responsibility, however, is assumed for inaccuracies. Elmos does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications. Copyright 2015 Elmos Reproduction, in part or whole, without the prior written consent of Elmos, is prohibited. 12/12

E Mux Demonstration Board AN 0141 Jul 10, 2015

E Mux Demonstration Board AN 0141 Jul 10, 2015 1 What you get: 1. One or more demonstration boards 2. Board description (this document) 3. USB Stick or CD - with driver for elmos LIN converter - GUI - flash and auto-addressing software 2 What you need