Micron MT54V512H18EF-10 9Mb QDR SRAM Circuit Analysis

Transcription

1 May 14, 2002 Micron MT54V512H18EF-10 9Mb QDR SRAM Circuit Analysis Table of Contents Introduction... Page 1 List of Figures... Page 4 Device Summary Sheet... Page 12 Top Level Diagram...Tab 1 Data Path...Tab 2 Address Path...Tab 3 Control Clocks...Tab 4 Voltage Generators...Tab 5 Column Redundancy...Tab 6 Data Output Impedance Control...Tab 7 Test Mode...Tab 8 Signal Naming Conventions and Symbol Definitions...Tab 9 Signal Cross-Reference List...Tab 10 For questions, comments, or mor e i nformation about thi s r eport, or f or any additional technical needs concerning semiconductor technology, please call a Sales Represetnative at Chipworks. Rev. F1.0

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3 Micron MT54V512H18EF Kx18 QDR SRAM Page 4 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Die Photograph Pinout Die Architecture Gate Definitions NOTL Definitions I NOTL Definitions II NOTL Definitions III NOTL Definitions IV NOTL Definition V NOTH Definitions I NOTH Definitions II NOTH Definitions III NOTH Definitions IV NOTH Definitions V NOTH Definition VI Latch1 Definitions Latch2 Definitions Latch3 and Latch4 Definitions Latch5 Definition DFF Definitions DFFR Definition DFFM Definitions Data Input Protection Address and Clock Input Protection Power Supply Protection

4 Micron MT54V512H18EF Kx18 QDR SRAM Page {VREF} and Options Input Protection {ZQ} Input Protection Test Input Protection {TDO} Output Protection Bitmap Top Level Diagram Data Path Block Shared Sense Amplifiers Sector Sense Amplifiers Bitline Sense Amplifier Redundant Sector Sense Amplifiers Redundant Bitline Sense Amplifier Data Bus Sense Amplifiers Data Bus Sense Amplifier Redundant Data Bus Sense Amplifier Data Byte Input/Output Local Data Input/Output Read Data Bus Latches Data Output Select Data Output Pipeline Data Gated Buffer I Data Gated Buffer II Data Output Driver Pull-up Programmable Load Pull-down Programmable Load Data Input Buffer Data Input Register Recent Data Return Switch

5 Micron MT54V512H18EF Kx18 QDR SRAM Page Write Data Bus Switches Write Data Bus Switch Block Write Drivers Sector Write Drivers Write Driver Redundant Sector Write Drivers Redundant Write Driver Test Data Output Path Address Path Address Input Input Buffer Address Input Latches Address Predecoders and Match Detector Read Address Predecoders Write Address Predecoders Address Registers and Comparators Address Match Detector Address Buffers Read Block Select Buffers I Read Block Select Buffers II Read Sector Select Buffers I Read Sector Select Buffers II Read Row Address Buffers Read Column Address Buffers Write Block Select Buffers Write Sector Select Buffers Write Address Buffers Sector Decoder for Read Redundant Sector Decoder for Read

6 Micron MT54V512H18EF Kx18 QDR SRAM Page Sector Decoder for Write Redundant Sector Decoder for Write Row Decoders Master Row Decoder for Read Redundant Master Row Decoder for Read Master Row Decoder for Write Redundant Master Row Decoder for Write Sector Row Decoder Wordline Drivers I Redundant Wordline Drivers I Wordline Drivers II Redundant Wordline Drivers II Column Decoders Sector Column Decoder for Read Redundant Sector Column Decoder for Read Sector Column Decoder for Write Redundant Sector Column Decoder for Write Redundant Row Programming Control Clocks Clock Input Synchronizer Clock Input Buffer I Clock Toggle Latch Unused {K#} Buffer Clock Input Buffer II {C} and {C#} Status Detector Clock Distribution Buffers Read/Write Controls Input RW Input Latch Byte Write Controls Input

7 Micron MT54V512H18EF Kx18 QDR SRAM Page {BW#} Input Buffer Byte Write Input Latch Read/Write Cycle Control Read/Write Initialization Control Programmable Delay Line Read/Write Burst Control Sense Clocks Sense Enable Data Bus Sense Amplifier Control Data Bus Sampling Clock Read Burst Clocks Data Output Enable Burst Counter Data Output Clocks Write Burst Clocks Write Burst Control Register Additional Address Register Data Input Register Clocks Early/Actual Write Clocks Data Coherency Control Low Power Mode Enable Voltage Generators Power-up Reset Circuitry Bias Generator P-well Bias Generator Cell Array Power Supply Reference Voltage Source

8 Micron MT54V512H18EF Kx18 QDR SRAM Page Column Redundancy Segment Column Redundancy Address Factor Latches Redundant Column Segment Decoder Redundant Column Segment Select Read Column Redundancy Read Redundancy Select for {D} Read Redundancy Select for {Q} Write Column Redundancy Write Redundancy Select Data Output Impedance Control Impedance Matching Regulator Pull-up Reference Load Pull-down Reference Load Comparator Input Switch Programmable Voltage Reference Voltage Comparator Pull-up Adjust Register Adjust Register Cell Pull-down Adjust Register Resistor Status Detector ZQ Main Control bit Counter T Flip-Flop Epoch Decoder Cycle Control Result Output Control Impedance Control Output Stage

9 Micron MT54V512H18EF Kx18 QDR SRAM Page Result Latched Multiplexer Result Output Register Delay Register II Delay Register I Test Mode TAP Controller {TMS} and {TCK} Input Buffers TAP State Machine TAP Decoder {TDI} Input Buffer Registers and Input/Output Select Input Select Instruction Registers Instruction Register Instruction Decoder Test Instruction Register Register Cell Bypass Register Bit Identification Register Boundary Scan Register Boundary Scan Cell Programming Circuitry Delay Line Programming Circuitry Redundant Row Programming Circuitry Redundant Row Programming Redundant Column Programming Circuitry Redundant Column Segment Programming Redundant Write Data Bus Programming Circuitry Redundant Write Data Bus Programming

10 Micron MT54V512H18EF Kx18 QDR SRAM Page Redundant Read Data Bus Programming Circuitry Redundant Read Data Bus Programming ZQ Programming Circuitry Fuse/Serial Programming Cell Bit SN Register SN Programming Cell SN Output Cell Global Master Fuses Output Select {TDO} Output Buffer A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2 A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.2.2 Symbol Definitions 3 A.2.3 Symbol Definitions - 4 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation