1 Megabit Serial Flash EEPROM SST45LF010

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1 EEPROM FEATURES: Single.0-.V Read and Write Operations Serial Interface Architecture SPI Compatible: Mode 0 and Mode Byte Serial Read with Single Command Superior Reliability Endurance: 00,000 Cycles (typical) Greater than 00 years Data Retention Low Power Consumption: Active Current: 0 ma (typical) Standby Current: 0 µa (typical) Sector or Chip-Erase Capability Uniform KByte sectors Fast Erase and Byte-Program: Chip-Erase Time: 0 ms (typical) Sector-Erase Time: ms (typical) Byte-Program Time: µs (typical) PRODUCT DESCRIPTION The is a Mbit serial flash memory manufactured with SST s proprietary, high performance CMOS SuperFlash technology. The Mbit of memory is organized as sectors of 0 Bytes. The memory is accessed for Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data input (), serial data output (), serial clock (), write protect (), chip enable (), and hardware reset (RESET#). The device is offered in -pin IC package. See Figure for the pinout. Device Operation The uses bus cycles of bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table. All instructions are synchronized off a high to low transition of. The first low to high transition on will initiate the instruction sequence. Inputs will be accepted on the rising edge of starting with the most significant bit. Any low to high transition on before the input instruction completes will terminate any instruction in progress and return the device to the standby mode. Automatic Write Timing Internal V PP Generation End-of-Write Detection Software Status 0 MHz Max Clock Frequency Hardware Reset Pin (RESET#) Resets the device to Standby Mode CMOS I/O Compatibility Hardware Data Protection Protects and unprotects the device from Write operation Packages Available -Pin IC (.mm x mm) Read The Read operation outputs the data in order from the initial accessed address. While is input, the address will be incremented automatically until end (top) of the address space (FFFFH), then the internal address pointer automatically increments to beginning (bottom) of the address space (00000H), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on. Sector/Chip-Erase Operation The Sector-Erase operation clears all bits in the selected sector to FF. The Chip-Erase instruction clears all bits in the device to FF. Byte-Program Operation The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state ( FF ) when initiating a Program operation. The data is input from bit to bit 0 in order. Software Status Operation The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a 0 an Erase or Program operation is in progress, the device is busy. If bit 0 is at a the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. - /00

2 Reset Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the RESET# pin. The device will remain in reset condition as long as RESET# is low. Minimum reset time is 0µs. See Figure for reset timing diagram. RESET# is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on is required to start the next operation. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to RESET# during the power-on process then changing to a logic level high when V DD has reached the correct voltage level will provide additional protection against accidental writes during power on. Read SST ID/Read Device ID The Read SST ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the Megabit Serial Flash manufacturer assigned device identification codes. These codes may be used to determine the actual device resident in the system. TABLE : PRODUCT IDENTIFICATION TABLE Byte Data Manufacturer s Code 0000 H BF H Device Code 000 H H PGM T.0 Write Protect The pin provides inadvertent write protection. The pin must be held high for any Erase or Program operation. The pin is don t care for all other operations. In typical use, the pin is connected to V SS with a standard pull-down resistor. is then driven high whenever an Erase or Program operation is required. If the pin is tied to V DD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The pin has an internal pull-up and could remain unconnected when not used. FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X - Decoder SuperFlash Cell Array Y - Decoder Control Logic I/O Buffers and Data Latches Serial Interface RESET# ILL B.

3 RESET# VDD Standard Pinout Top View Die Up VSS FIGURE : PIN ASGNMENTS FOR -PIN IC ILL F0. TABLE : PIN DESCRIPTION Symbol Pin Name Functions Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Chip Enable The device is enabled by a high to low transition on. Write Protect To protect the device from unintentional Write (Erase or Program) operations. When is low, all Erase and Program commands are ignored. When is high, the device may be erased or programmed. This pin has an internal pull-up and could remain unconnected when not used. RESET# Reset A high to low transition on RESET# will terminate any operation in progress and reset the internal logic to the standby mode. The device will remain in the reset condition as long as the RESET# is low. Operations may only occur when RESET# is high. This pin has an internal pull-up and could remain unconnected when not used. V DD Power Supply To provide power supply (.0-.V). Ground V SS PGM T. 0

4 TABLE : DEVICE OPERATION INSTRUCTIONS Bus Cycle and after Operation/Type Command Address () Address Address Data Dummy Data Read FFH A-A A-A A-A0 X X Dout Sector-Erase () 0H A-A A-A X D0H X Chip-Erase 0H X X X D0H X Byte-Program 0H A-A A-A A-A0 Din X Software-Status FH Dout Read SST ID 0H X X A0=0 BFH Read Device ID 0H X X A0= H Notes:. A-A are Don't Care.. A-A are used to determine sector address, A - A are don't care. T PGM T. TABLE : DEVICE OPERATION TABLE Operation RESET# Read X Dout Low X High Sector-Erase X X Low High High Chip-Erase X X Low High High Byte-Program Din X Low High High Software-Status X Dout Low X High Reset X X X X Low Read SST ID X Dout Low X High Read Device ID X Dout Low X High Notes:. A high to low transition on will be required to start any device operation except for Reset.. The RESET# low will return the device to standby and terminate any Erase or Program operation in progress. PGM T.

5 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias... - C to + C Storage Temperature... - C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V DD + 0.V Transient Voltage (<0 ns) on Any Pin to Ground Potential V to V DD +.0V Package Power Dissipation Capability (Ta = C)....0W Surface Mount Lead Soldering Temperature ( Seconds)... 0 C Output Short Circuit Current ()... 0 ma OPERATING RANGE Range Ambient Temp V DD Commercial 0 C to +0 C.V ± 0.V Industrial -0 C to + C.V ± 0.V AC CONDITIONS OF TEST Input Rise/Fall Time... ns Output Load... C L = 0 pf See Figures and TABLE : DC OPERATING CHARACTERISTICS VDD =.0-.V Limits Symbol Parameter Min Max Units Test Conditions Power Supply Current f = 0 MHz I DD Read 0 ma = V IL, V DD = V DD Max. Program and Erase 0 ma = V IL, V DD = V DD Max. I SB Standby Current µa = V IHC, V DD = V DD Max. I LI Input Leakage Current µa V IN =GND to V DD, V DD = V DD Max. I LO Output Leakage Current µa V OUT =GND to V DD, V DD = V DD Max. I IL Input Low Current () 0 µa, RESET# = GND V IL Input Low Voltage 0. V V DD = V DD Min. V IH Input High Voltage 0. V DD V V DD = V DD Max. V IHC Input High Voltage (CMOS) V DD-0. V V DD = V DD Max. V OL Output Low Voltage 0. V I OL = 00 µa, V DD = V DD Min. V OH Output High Voltage V DD-0. V I OH = -00 µa, V DD = V DD Min. Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. () This parameter only applies to and RESET# pins. 0

6 TABLE : CAPACITANCE (Ta = C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C () OUT Output Pin Capacitance V OUT = 0V pf C () IN Input Capacitance V IN = 0v pf TABLE : RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N () END Endurance 0,000 Cycles JEDEC Standard A T () DR Data Retention 00 Years JEDEC Standard A0 V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LTH Latch Up 00 + I DD ma JEDEC Standard Note: () This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : AC OPERATING CHARACTERISTICS, VDD =.0-.V Limits Symbol Parameter Min Max Units F CLK Serial Clock Frequency 0 MHz T H Serial Clock High Time ns T L Serial Clock Low Time ns T CES Setup Time 0 ns T CEH Hold Time 0 ns T CPH High Time 0 ns T CHZ High to High-Z Output ns T CLZ Low to Low-Z Output 0 ns T RLZ RESET# Low to High-Z Output ns T DS Data In Setup Time 0 ns T DH Data In Hold Time 0 ns T OH Output Hold from Change 0 ns T V Output Valid from ns T WPS Write Protect Setup Time 0 ns T WPH Write Protect Hold Time 0 ns T SE Sector-Erase ms T SCE Chip-Erase 00 ms T BP Byte-Program 0 µs T RST Reset Pulse Width 0 µs T REC Reset Recovery Time µs T PURST Reset Time After Power-Up 0 µs

7 V IHT INPUT V IT REFERENCE POINTS V OT OUTPUT V ILT ILL F0. AC test inputs are driven at V IHT (0. V DD) for a logic and V ILT (0. V DD) for a logic 0. Measurement reference points for inputs and outputs are at V IT (0. V DD) and V OT (0. V DD) Input rise and fall times (0% «0%) are < ns. Note: VIT VINPUT Test VOT VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT LOW Test FIGURE : AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT ILL F0. CL 0 FIGURE : A TEST LOAD EXAMPLE

8 T CPH T CES T H T L T CEH T DS T DH DATA VALID HIGH-Z HIGH-Z ILL F0. FIGURE : SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW - MODE 0) T H T L T CEH T CLZ T OH T CHZ DATA VALID T V ILL F0. FIGURE : SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW - MODE 0)

9 TCPH T CES TL T H TCEH TDS T DH DATA VALID HIGH-Z HIGH-Z ILL F.0 FIGURE : SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK HIGH - MODE ) 0 T H T L T CEH T CLZ T OH DATA VALID T CHZ T V ILL F. FIGURE : SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK HIGH - MODE )

10 T WPS T WPH T SE 0 0 SELF-TIMED SECTOR- ERASE CYCLE 0H ADD. ADD. X D0H X HIGH IMPEDANCE ILL F0. FIGURE : SECTOR-ERASE TIMING DIAGRAM T WPS T WPH T SCE 0 0 SELF-TIMED CHIP- ERASE CYCLE 0H X X X D0H X HIGH IMPEDANCE ILL F0.0 FIGURE : CHIP-ERASE TIMING DIAGRAM 0

11 T WPS T WPH 0 0 T BP SELF-TIMED BYTE- PROGRAM CYCLE 0H ADD. ADD. ADD. Din X MSB LSB HIGH IMPEDANCE ILL F0. FIGURE 0: BYTE-PROGRAM TIMING DIAGRAM FFH ADD. ADD. ADD. X X HIGH IMPEDANCE N N+ N+ Dout Dout Dout MSB MSB MSB ILL F0. FIGURE : READ TIMING DIAGRAM

12 0 0 0H X X ADD HIGH IMPEDANCE MSB Dout LSB Note:. SST Manufacturer Code = BFH is read with A0=0 Device Code = H is read with A0= ILL F. FIGURE : READ-ID TIMING DIAGRAM 0 0 FH HIGH IMPEDANCE DATA DATA DATA MSB MSB MSB ILL F. FIGURE : FTWARE-STATUS TIMING DIAGRAM

13 ... TREC TCES RESET# TRST HIGH IMPEDANCE... TRLZ HIGH IMPEDANCE... FIGURE : RESET TIMING DIAGRAM (INACTIVE CLOCK POLARITY LOW SHOWN) ILL F0. V DD T PURST RESET# T REC 0 FIGURE : POWER-ON RESET TIMING DIAGRAM T WPS ILL F. T WPH T CPH T CES T CEH ILL F. FIGURE : WRITE PROTECT TIMING DIAGRAM

14 Device Speed Suffix Suffix - XXX - XX - XX Package Modifier A = pins Package Type S = IC Temperature Range C = Commercial = 0 to 0 C Minimum Endurance = 0,000 cycles Operating Frequency 0 = 0 MHz Device Density 00 = Megabit Voltage Range L =.0-.V Valid combinations -0-C-SA Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

15 PACKAGING DIAGRAMS Pin # Identifier.0. Note: places... BSC Complies with JEDEC publication MS-0 AA dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm places 0.soic-SA-ILL. -PIN SMALL OUTLINE INTEGRATED CIRCUIT PACKAGE (IC) SST PACKAGE CODE: SA 0

16 Silicon Storage Technology, Inc. Sonora Court Sunnyvale, CA 0 Telephone 0--0 Fax or Literature FaxBack --, International --

8 Mbit SPI Serial Flash SST25VF080

8 Mbit SPI Serial Flash SST25VF080 FEATURES: 8 Mbit SPI Serial Flash 8 Mb Serial Peripheral Interface (SPI) flash memory Single Voltage Read and Write Operations 2.7-3.6V for Serial Interface Architecture SPI Compatible: Mode 0 and Mode