WITH the need of industry for more and more smaller

Size: px
Start display at page:

Download "WITH the need of industry for more and more smaller"

Transcription

1 1 Minimum Cost Layout Decomposition and Legalization for Triple Patterning Lithography Wenxing Zhu, Xingquan Li, Ziran Zhu Abstract With the need of 16/11nm cells, triple patterning lithography (TPL) has been concerned in lithography industry. Basing on a new projection method for identifying conflicts, we solve the TPL layout decomposition problem in two steps. First, we formulate in this paper the TPL layout decomposition problem as a minimum cost coloring problem, and it is relaxed to a nonlinear 0-1 programming problem. Second, legalization methods are introduced to legalize a solution of the nonlinear 0-1 programming problem to a feasible one. At the legalization step, we prior utilize one-stitch insertions to eliminate conflicts. For very few independent components, a backtrack coloring algorithm is also used at this step to obtain a better relaxation coloring solution. At last, to improve scalability of our decomposition method, two graph reduction methods are adopted. We test our decomposition approach on the ISCAS-85 & 89 benchmarks. Comparisons of experimental results show that our approach achieves optimal costs better than those of state-ofthe-art decomposers. Moreover, our decomposition approach is faster than most of the decomposers on the tested benchmarks. Index Terms Triple patterning lithography, layout decomposition, minimum cost coloring, legalization. (a) (c) (b) (d) Fig. 1. TPL layout decomposition. (a) An example of three masks assignment. (b) An example of layout with conflict. (c) An example of layout with stitch insertion for eliminating conflict. I. INTRODUCTION WITH the need of industry for more and more smaller cells, the current 193nm ArF lithography technology cannot meet the need of the IC industry for 16/11nm lithography cells. Extreme Ultra-Violet (EUV) lithography is considered as a promising technology for next-generation lithography. However, due to the mask material, light source and other device problems, EUV still cannot be put into IC manufacture. Consequently, layout decomposition technology (LDT) has become the preferred, which decomposes an initial layout into multiple masks for use in multiple exposure lithography. LDT can meet the need of sub-22nm cells, and is considered of great values in research and industrial applications [1], [2], [3]. Layout decomposition for triple patterning lithography (T- PL) is that, an initial layout is decomposed into three masks. Fig. 1(a) shows an example of decomposing a layout to three masks. For TPL, the rule of minimum coloring spacing is that, if two features are within the minimum coloring spacing min cs, then they should be assigned to different masks; otherwise a conflict occurs between the two features. As shown in Fig. 1(b), according to the rule of minimum coloring spacing, a conflict occurs between features a and d. Conflicts can be eliminated by inserting stitches. That is, a feature may be split into several touching sub-features by inserting stitches. Wenxing Zhu, Xingquan Li and Ziran Zhu are with the Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou , China ( wxzhu@fzu.edu.cn). As shown in Fig. 1(c), a stitch is inserted into feature d. Since both conflict and stitch will affect the effect of lithography, especially the conflict, a crucial issue in TPL is to achieve the minimum numbers of conflicts and stitches. Before introducing previous works on TPL layout decomposition, it is necessary to introduce some researches on Double Pattering Lithography (DPL). Generally, DPL layout decomposer transforms the layout decomposition problem into the 2-coloring problem. Kahng et. al [3] and Yuan et. al [4] constructed Integer Linear Programming (ILP) models, where the number of conflicts and the number of stitches are minimized simultaneously. Xu et. al [5] and Tang et. al [6] used many graph division methods in DPL for reducing the scale of the problem. A sufficient condition for identifying the native conflicts was proposed by Fang et. al [7]. The method by Tang et. al [6] achieved the most up-to-date results, which is based on a polynomial time minimum cut algorithm. For the 16/11nm cells, DPL technology has reached its limit, and TPL has appeared as a new technology. TPL was proposed probably firstly by Cork et. al [8] for contact array layout. The TPL layout decomposition problem and the balanced density TPL layout decomposition problem are NP-complete, which were proved by Yu et. al [9], [10]. Hence almost of algorithms for the TPL layout decomposition problem belong to heuristic methods. Cork et. al [8] adopted a 3-SAT algorithm to solve the TPL layout decomposition problem. Yu et. al [9] formulated the TPL problem as an integer linear program (ILP), and proposed

2 2 a semi-definite programming relaxation of the problem for finding a solution. The heuristic method by Fang et. al [11] used the edge projection method to identify conflicts, and then all edges of the conflict graph were weighted. At present, the heuristic graph matching method proposed by Kuang et. al [12] achieved the fastest running time, in which numerous graph division methods were introduced for reducing the graph vertex number. For standard cells, a polynomial time algorithm based on row structure was proposed by Tian et. al [13]. This was improved substantially by Chien et. al [14] by considering conflicts. Some researches focused on extended TPL layout decomposition problems. Yu et. al [15] proposed a coherent framework for detailed placement to enable TPL friendly design. Recently, some decomposers [16], [17], [18] concerned on LELE-end-cutting for TPL. For the TPL layout decomposition problem, the methods by Yu et. al [9], [10] used continuous relaxation of the problem, and rounded the obtained infeasible solution to a feasible one. The other methods [11], [12], [13] operated in the feasible solution space only. Most of previous works on TPL layout decomposition encountered one or more issues as follows: (1) use the line projection method to identify conflicts, which cannot identify native conflicts; (2) stitch position is not locally optimal. In this paper, we propose a minimum-cost layout decomposition approach for TPL, which is a discrete relaxation based method. Our work obtains a decomposition solution in two steps, as shown in Fig. 2. The first step focuses on finding a discrete relaxation solution. Due to the graph reduction methods used in this paper, the solution space is extremely reduced, and we can fast find a solution with the minimum cost in the first step. At the second step, the minimum-cost solution is legalized to a feasible solution. From the experimental results, we find that our two-step approach is fast and effective. The main contributions of this paper are as follows: A new non-conflict feature removal method is proposed for graph reduction. A new conflict identification method is proposed for identifying native conflicts in TPL layout, which is a surface projection based method. We obtain a lower bound on the decomposition cost of TPL by discrete relaxation. The discrete relaxation problem significantly reduce solution space of the TPL layout decomposition problem by ignoring stitch insertions. We present an optimal one-stitch insertion method to eliminate conflicts. This method is used to legalize a solution of the discrete relaxation problem. Experimental results show that our method is fast and effective, compared with the state-of-the-art decomposers. Specifically, for some test benchmarks, we can prove that our results are optimal. The rest of this paper is organized as follows. Problem formulation and overview for TPL layout decomposition are stated in Section II. Section III introduces the minimum cost coloring problem. Section IV describes our legalization process. Section V explains the graph reduction methods used in our decomposition method. Experimental results will be showed in Section VI, and Section VII concludes our work. Fig. 2. Contours of cost Discrete feasible region C C* Optimal solution (2) Legalization direction (1) Discrete relaxation solution Geometrical representation of our two step approach. II. PRELIMINARIES In this section, we present the problem formulation of TPL layout decomposition, and show the difference of one-stitch and multi-stitch insertions. Overview of our decomposition flow is presented at last. A. Problem formulation Firstly we introduce two definitions as follows. Definition 1 (conflict graph, CG). The conflict graph is defined as an undirected graph G(V, E), where V represents the set of vertices, and v V represents a feature. E is the set of edges, and e = (i, j) E exists between two features i and j, if the distance between them is less than min cs. Definition 2 (sub-feature). Stitches are inserted into a feature, and the feature will be split into several parts, namely sub-features. TPL Stitch Insertion and Color Assignment Problem Given: Layout L, the minimum coloring spacing min cs, the minimum feature size min fs. Find: Optimal stitch insertions in features and color assignment of features and sub-features. The primary objective is the minimum number of conflicts, and the secondary objective is the minimum number of stitches. The constraints are: (i) two features within the minimum coloring spacing min cs should be assigned different colors; (ii) all sub-features must be lager than the minimum feature size min fs. (a) (b) Fig. 3. An illustration of stitch insertion. (a) An example of multi-stitch insertion. (b) An example of one-stitch insertion.

3 3 Layout TABLE I NOTATIONS Optimal Onestitch Insertion Backtrack Coloring Global Coloring Conflict Graph Construction Graph Reduction Minimum Cost Coloring Legalization Output Masks Vertex With Degree Less Than 3 Removal Contained Vertex Removal Independent Component Calculation CF NCF CAF C 1, C 2, C 3 R 4 UCF UNCF RV W OSF A 1, A 2, A 3 The set of conflict features The set of non-conflict features The set of conflict adjacent features The color classes The set of uncolored vertices The set of uncolored conflict features The set of uncolored non-conflict features The set of removed vertices The set of uncolored non-conflict features without one-stitch insertion The total area of features with the same color Fig. 4. Our TPL layout decomposition flow. B. One-stitch and multi-stitch insertions For a layout, there are many different stitch insertion strategies. Here, we show the difference between one-stitch and multi-stitch insertions. For a feature, if the number of stitches in the feature is one, then it is called a one-stitch insertion; if the number of stitches on the feature is more than one, then it is called a multi-stitch insertion. For example, in the layout shown in Fig. 3(a), two stitches are inserted into feature d. Hence we call feature d has a multi-stitch insertion. In Fig. 3(b), a stitch is inserted into features b and e, respectively. Hence, we call features b and e have a one-stitch insertion, respectively. Figs. 3(a) and 3(b) have two different stitch insertion strategies. Both of them can eliminate conflicts, and have the equal number of stitches. In this paper, one-stitch insertion strategy is priory considered when the costs of two kinds of insertion strategies are equal. We will design an optimal onestitch insertion algorithm in Section IV. C. Overview of decomposition flow Fig. 4 illustrates the decomposition flow chart. First, according to the rule of minimum coloring spacing, we transform an initial layout to a conflict graph by our new projection method. And then, we adopt two graph reduction methods to remove some non-conflict features. After that, the large scale problem is reduced to numerous small subproblems. At the minimum cost coloring step, the conflict features are further identified by our projection method. During coloring, in order to emphasize the conflict features, we assign larger weights to conflict features than non-conflict features. Then, a nonlinear 0-1 program is solved for obtaining a discrete relaxation solution. At the legalization step, stitch insertion and backtrack coloring algorithms are respectively used to legalize the discrete relaxation solution. Finally, we use a density balance aware global coloring approach to color other non-conflict features. Fig. 5 illustrates a layout decomposition example, which presents the main steps of our approach. Details of the decomposition process are described in the following sections. (a) (c) (e) (b) (f) (d) Fig. 5. A sample of our decomposition flow. (a) Input layout. (b) Identification of conflicts by the surface projection method. (c) Weighting vertices of the conflict graph and obtaining a discrete relaxation solution. (d) One-stitch insertion to eliminate conflicts. (e) A feasible coloring solution. (f) The final mask assignment. A. Identifying conflicts III. MINIMUM COST COLORING The first conflict identification method was proposed by Kahng et. al [4]. It has been utilized popularly for DPL and TPL layout decompositions. However, most previous works only consider the edge projection of each feature on its adjacent features. Fig. 5(a) shows an example of the edge projection of feature b on feature a. Here, we propose a new conflict identification method, namely, the surface projection method. In order to present the method accurately, we introduce two definitions: conflict

4 4 region CR and conflict rectangle CRT. As illustrated in Fig. 5(b), the shaded region of feature b is called a conflict region, and the smallest rectangle enclosing the intersection of feature a and the conflict region of feature b is a conflict rectangle. Definition 3 (conflict region, CR). The conflict region of a feature is defined as a 2D region around the feature, which is within the minimum coloring spacing min cs of the feature. Definition 4 (conflict rectangle, CRT ). The conflict rectangle on feature a by feature b is defined as the minimum rectangle enclosing the intersection of feature a and the conflict region of feature b. Before presenting the method for identifying conflicts, some relevant terms are shown as follows. Definition 5 (triple conflict rectangle, T CRT ). The triple conflict rectangle on feature a is defined as a rectangle, which is an intersection of three or more conflict rectangles on feature a. Some adjacent features of feature a create these conflict rectangles, and these adjacent features are called conflict adjacent features (CAF ) of feature a. Definition 6 (conflict feature, CF ). Feature a is called a conflict feature if it satisfies the two conditions as follows: (1) there is a triple conflict rectangle T CRT on feature a; (2) the graph composed of feature a and its conflict adjacent features (CAF ) is not 3-colorable. By Definition 6, we can identify that the feature c in Fig. 5(b) is a conflict feature. There is a triple conflict rectangle on it, and the graph composed of feature c and its conflict adjacent features a, b and d, is a K 4 graph, which is not 3- colorable. Hence our surface projection method can be used to identify conflict features. However, the edge projection method only considers boundary projection, which cannot be used to find conflict features. As the feature c in Fig. 5(a) shows, the edge projection cannot find the triple conflict rectangle T CRT on it. Hence, our surface projection method can be used to identify native conflicts, but the edge projection method cannot. Lemma 1. Suppose that feature a is a conflict feature, and features a 1, a 2,..., a k+1 are the sub-features of feature a, where k is the number of stitches inserted into feature a. Then at least one of features a 1, a 2,..., a k+1 is still a conflict feature. Proof: If feature a is a conflict feature, then it has at least a T CRT. We insert k stitches into feature a and split it into sub-features a 1, a 2,..., a k+1. Suppose that we first insert stitch s 1 into feature a and split it into two parts a 1 and a 2. Then there are two possible results: 1) if stitch s 1 cuts across the T CRT on feature a, we have that both sub-features a 1 and a 2 contain T CRT ; 2) otherwise, only one of a 1 and a 2 contains T CRT. Next, stitches are inserted into feature a step by step. At last, feature a is split into k+1 sub-features a 1, a 2,..., a k+1. Obviously, the number of sub-features containing T CRT is nondecreasing. Hence, at least one of the sub-features a i contains T CRT, and the sub-graph consisting of the subfeature a i and the conflict adjacent features CAF of feature a is not 3-colorable. By Definition 6, this completes the proof. Assume that C 1, C 2, C 3 and R 4 are the color classes of 3-coloring of the vertices of the conflict graph. For color class C k, if i, j C k, then e ij E, k = 1, 2, 3; otherwise a conflict number occurs between features i and j, and e ij is a conflict edge. Due to conflicting with other features, some features are uncolored, and they belong to color class R 4. That means we should color vertices of the conflict graph as many as possible using the three colors, such that any two adjacent features are assigned different colors. As Fig. 5(c) shows, vertices a, b and c are colored, but vertex d is uncolored. Hence vertices a, b and c belong to the color classes C 1, C 2 and C 3, respectively, and vertex d belongs to R 4. For convenience of description, we introduce two sets, U CF and U N CF, where U CF is the set of uncolored conflict features, and UNCF is the set of uncolored nonconflict features. Theorem 1. For every feature a U CF, there exists at least a conflict which cannot be eliminated by inserting stitches. Proof: Suppose that feature a belongs to UCF. Then a is a conflict feature, a R 4, and at least a conflict will occur at feature a. By Lemma 1, if stitches are inserted into feature a, we can deduce that one or more sub-features of feature a are conflict features, and there still exist conflicts. Hence, at least a conflict occurs at feature a which cannot be eliminated by inserting stitches. Theorem 1 provides a sufficient condition for finding conflicts. Thus, to find potential conflicts in a layout, it is important to identify the conflict features before coloring. Identifying the conflict features can be done by the BFS algorithm, which traverses all vertices, and finds all conflict features. The runtime complexity is O(n), where n is the number of features in the layout. After finding all conflict features, we weight all features and formulate a nonlinear 0-1 program for assigning colors to them. B. Mathematical formulation of minimum cost coloring Suppose that we color vertices of the conflict graph using three colors, such that any two adjacent features are assigned different colors, or leave some vertices uncolored. Then the initial conflict graph G(V, E) is split into four sub-graphs G 1 (C 1, E 1 ), G 2 (C 2, E 2 ), G 3 (C 3, E 3 ), G 4 (R 4, E 4 ), where E 1 = E 2 = E 3 =, and C 1 C 2 C 3 R 4 = V. For every feature i R 4, i.e., i is uncolored, we insert s i (s i 0) stitches into feature i, and assign colors with the minimum number of conflicts to feature i or its sub-features. Then feature i or its sub-features and the corresponding edges are added to the subgraphs G 1 (C 1, E 1 ), G 2 (C 2, E 2 ), or G 3 (C 3, E 3 ). After all vertices in R 4 are split and added to subgraphs, we get three new subgraphs G 0 1(C 0 1, E 0 1), G 0 2(C 0 2, E 0 2),

5 5 and G 0 3(C3, 0 E3). 0 If i, j Ck 0 and e ij Ek 0, then a conflict number occurs between i and j, and the number of total edges in G 0 1, G 0 2 and G 0 3 is the conflict number. Thus we get the conflict number C and the stitch number S as C = Ek, 0 S = s i. i R 4 k=1,2,3 Since there are many different ways of inserting stitches into every feature i R 4, they must be exhausted for finding the minimum value C + α S, when calculating the objective function value in the following minimum cost coloring problem. Minimum-Cost Coloring Problem Given: A layout with a series of features, and the minimum coloring spacing min cs. Find: Optimal color assignment C 1, C 2, C 3 and R 4 of features. The objective is the minimum cost C + α S. The constraints are that, any two features within the minimum coloring spacing min cs should be assigned different colors. Mathematically, the problem can be formulated as the following weighted objective minimization problem: min C + α S (1a) s.t. e ij E, i, j C k (k = 1, 2, 3), (1b) where constant α is a weight parameter. In this paper, we take α = 0.1, which is as that in Yu et al. [9]. Problem (1) is not easy to solve, since it is an NP-hard problem and there are different ways of inserting stitches into every feature i R 4. In the following, we formulate a nonlinear 0-1 program whose optimal value provides a lower bound on the optimal value of problem (1). The problem size of the nonlinear 0-1 program is significantly less than that of the TPL layout decomposition problem, due to ignoring stitch insertions. Let (x i1, x i2 ) be a two dimensional binary variable, which is used to express the color of vertex i. When (x i1, x i2 ) = (0, 1), it means i C 1 ; similarly, when (x i1, x i2 ) = (1, 0), it means i C 2 ; and when (x i1, x i2 ) = (1, 1), it means i C 3. However, when (x i1, x i2 ) = (0, 0), it means that vertex i is uncolored, i.e., i R 4. By Theorem 1, we know each conflict feature provides at least a conflict number which cannot be eliminated by inserting stitches. While conflicts occurring at non-conflict features may be totally eliminated by inserting stitches. Hence, in our color assignment problem, the conflict features should be prior colored to minimize the number of conflicts. This could be made by assigning larger weights to the conflict features, which is as follows. Let w i be the weight of vertex i, where { 1, if i is a conflict feature; w i = α, if i is not a conflict feature. Then the color assignment problem for a graph with weighted vertices is formulated as the nonlinear 0-1 programming model as follows. min w i (1 x i1 )(1 x i2 ) i V (2a) s.t. x i2 x i1 + x j2 x j1 1, e ij E; (2b) x i1 x i2 + x j1 x j2 1, e ij E; (2c) x i1 + x i2 + x j1 + x j2 3, e ij E; (2d) (x i1, x i2 ) {0, 1} {0, 1}, i V. (2e) In the objective function, (1 x i1 )(1 x i2 ) = { 0, if i R4 ; 1, if i R 4. Hence Objective (2a) is minimizing the total weight of the vertices in R 4. Constraints (2b)-(2d) are used to force that, if e ij E, then vertices i and j should not be in the same color classes C 1, C 2 and C 3, respectively. For any optimal solution (C 1, C 2, C 3, R 4 ) of problem (1), if a feature in R 4 does not adjacent to all features in some color class C i, then we move the feature to C i. Obviously, this operation does not change the objective value, and we obtain another optimal solution of problem (1). Hence in the following part of this section, we suppose without loss of generality that, for any optimal solution of problem (1), every feature in R 4 is adjacent to some feature in C i, for all i {1, 2, 3}. Thus a feature in R 4 either contributes conflicts or must be inserted stitches. To eliminate conflicts, we insert stitches into the features in R 4. After stitch insertions, some features in R 4 are conflict free, and we call them Not Occurring Conflict Features (NOCF ). However, conflicts may still occur at some features in R 4 after stitch insertions, i.e., conflicts may not be totally eliminated by inserting stitches, we call these features Occurring Conflict Features (OCF ). Obviously, OCF NOCF = R 4, and OCF + NOCF = R 4. Problem (1) and program (2) have the following relations. Lemma 2. At any optimal solution (C 1, C 2, C 3, R 4 ) of problem (1), the objective value in (2a) is less than or equal to the objective value in (1a). Proof: Given any optimal solution x = (C 1, C 2, C 3, R 4 ) of problem (1), it is easy to deduce that UNCF UCF = R 4, and UNCF + UCF = R 4. According to Theorem 1, we know that every feature in UCF contributes at least a conflict number. Hence UCF OCF C. Let Y = C UCF. Obviously, Y 0. Moreover, every feature i NOCF must be inserted s i 1 stitches to eliminate conflicts. So NOCF S, and UNCF + UCF C = R 4 C R 4 OCF = NOCF S. Furthermore, since α = 0.1, we have UCF + α UNCF UCF + α UNCF + (1 α) Y = UCF + Y + α( UNCF Y ) = C + α( UNCF + UCF C ) C + α S.

6 6 According to the value of w i, it is easily known that UCF + α UNCF = i V w i (1 x i1 )(1 x i2 ). Hence, for any optimal solution x = (C 1, C 2, C 3, R 4 ) of problem (1), it holds that w i (1 x i1 )(1 x i2 ) C + α S. i V Theorem 2. The optimal value of program (2) is a lower bound on the optimal value of problem (1). Proof: Let F (x) = C +α S and G(x) = i V w i(1 x i1 )(1 x i2 ). Suppose that x = (C 1, C 2, C 3, R 4) is an optimal solution of problem (1), and x = (C 1, C 2, C 3, R 4) is an optimal solution of program (2). Then G(x ) G(x ). Moreover, by Lemma 2, G(x ) F (x ). Thus G(x ) G(x ) F (x ). Hence, the optimal value of program (2) is a lower bound on the optimal value of problem (1). Theorem 3. Let x = (C 1, C 2, C 3, R 4 ) be an optimal solution of program (2). If every feature i UNCF can be inserted only s i = 1 stitch to eliminate conflicts, and every feature i U CF contributes only a conflict number, then x = (C 1, C 2, C 3, R 4 ) is also an optimal solution of problem (1). Proof: If every feature i UNCF can be inserted only s i = 1 stitch to eliminate conflicts, and every feature i UCF contributes only a conflict number, then U CF = OCF and UNCF = NOCF. Thus C = OCF = UCF, and S = s i = NOCF = UNCF. So and i NOCF UCF + α UNCF = C + α S, UCF + α UNCF = i V w i (1 x i1 )(1 x i2 ). Hence by Theorem 2, x = (C 1, C 2, C 3, R 4 ) is also an optimal solution of problem (1). The above results indicate that program (2) is a discrete relaxation of problem (1). Program (2) is a nonlinear 0-1 program, which is generally difficult to solve for large scale cases. However, the graph reduction techniques proposed in Section V can reduce the conflict graph to many small size independent components. Thus program (2) on the small size independent components can be solved easily. Specifically, we use the Branch and Bound method in the software package GUROBI [19] to solve the problem. The minimum-cost coloring is the first step of decomposition of the conflict graph after graph reduction, whose goal is to obtain a relaxation solution (C 1, C 2, C 3, R 4 ) with the minimum cost. The second step is legalization shown in Section IV. If there exist some features in R 4, then we try to find a stitch insertion trick on each of them, or we try to find another coloring solution (C 1, C 2, C 3, R 4) with a better stitch insertion plan. These works are done in the legalization step. IV. LEGALIZATION For every independent component of the conflict graph got by the graph reduction techniques proposed in Section V, program (2) obtains a relaxation coloring solution. Then, in order to obtain a feasible solution of TPL layout decomposition, the discrete relaxation solution should be legalized. For an independent component G, the legalization proceeds as follows. If in the relaxation coloring solution (C 1, C 2, C 3, R 4 ) of G, R 4, then to eliminate conflicts, we introduce optimal one-stitch insertions on the features in R 4. Details of optimal one-stitch insertion are described in Section IV.A. Furthermore, if there exits a feature i U N CF which cannot be inserted only s i = 1 stitch to eliminate conflicts, then the solution obtained from the relaxation coloring solution may not be optimal. In this case, we propose a backtrack coloring method to obtain another better relaxation solution (C 1, C 2, C 3, R 4). And then we consider optimal one-stitch insertion on the new relaxation solution. The details are shown in Section IV.B. A. Optimal one-stitch insertion Due to conflicts, the features in the set R 4 of a relaxation solution are uncolored. And the features would be inserted stitches to eliminate conflicts, as feature d shown in Fig. 5(c). Since our objective is that, these features should be colored with the minimum weighted conflict number and stitch insertion number, we should find stitch insertions into the features in R 4 before coloring. An algorithm for finding all candidate one-stitch insertions on a feature a is shown as Algorithm 1. Algorithm 1: Candidate one-stitch insertions Input: feature a in R 4, and its adjacent features and their colors; Output: all candidate one-stitch insertions on a; 1: for every adjacent feature of feature a do 2: calculate the CRT s on feature a caused by its adjacent features, and store CRT s in CRT Set; 3: end for 4: for every CRT CRT Set do 5: CSEs=genCSE(CRT ); 6: store CSEs in CSESet; 7: end for 8: for every CSE CSESet do 9: if splitting feature a into two conjoint parts along CSE satisfies Conditions 1, 2 and 3, then store the CSE into candidate one-stitch set COSSet; 10: end for In the algorithm, firstly we find all conflict rectangles (CRT s) on feature a (Line 2). A CRT consists of four edges,

7 7 each edge of CRT generates a Checking Stitch Edge (CSE). A CSE of feature a is a line segment whose two endpoints are on the boundary of feature a, and feature a could be split into two conjoint parts along the CSE. Generation of a candidate one-stitch insertion must satisfy the following three conditions: Condition 1. The size of anyone of the two conjoint parts should be larger than the minimum feature size min fs ; Condition 2. A candidate one-stitch insertion is not near a corner of feature a; Condition 3. If feature a UNCF, then conflict does not occur at both of the two generated sub-features, i.e., they can be colored without conflict occurring; otherwise, if a UCF, then conflict does not occur at one of the two generated subfeatures. Conditions 1 and 2 are due to that, a very small sub-feature is easy to generate overlay error and a corner stitch may cause significant side effect on printability [3], [7]. Condition 3 is a necessary condition for producing a legal triple patterning layout decomposition. In the algorithm, the function gencse(crt) refers to generating four CSEs of a conflict rectangle CRT (Lines 4-7). If along a CSE the feature a could be split into two conjoint parts satisfying the three conditions, then the CSE is a candidate one-stitch insertion (Lines 8-10). After obtaining all candidate one-stitch insertions, we find an optimal stitch in COSSet for feature a, and split feature a along the optimal stitch into sub-features a 1 and a 2. And then we color features a 1 and a 2 such that their colors do not conflict the colors of their adjacent features. The optimal one-stitch is based on a criterion cut cost for evaluating every stitch, which is the increased number of edges of the conflict graph after splitting feature a along the stitch. Note that, two sub-features a 1 and a 2 of feature a got by splitting feature a along stitch s will be assigned different colors. Suppose that b i is an uncolored feature and adjacent to feature a, i.e., e abi E. If e a1b i E and e a2b i E, then splitting feature a along stitch s will increase the degree of feature b i by 1, and we let cut cost bi = 1. So the function cut cost(s) of stitch s is formulated as cut cost(s) = cut cost bi, where cut cost bi = e abi E { 1, ea1bi E and e a2b i E; 0, otherwise. Obviously, cut cost(s) 0. An optimal one-stitch is with the minimum cut cost(s). Our empirical experience indicates that most of features in UNCF have optimal one-stitches with cut cost(s) = 0. For every feature in R 4, Algorithm 1 is used to find all candidate one-stitch insertions, and all optimal one-stitch insertions are found based on the above criterion. After that, features in R 4 with optimal one-stitch insertions are split along their optimal one-stitches respectively, and the obtained subfeatures are colored legally. Then the conflict graph G, the sets C 1, C 2, C 3 and R 4 are updated accordingly. If conditions of Theorem 3 are satisfied, then the obtained coloring solution is (a) (c) Fig. 6. Samples of backtrack coloring. (a)(c) Initial illegal coloring solutions. (b)(d) Feasible solutions after backtracking. optimal for problem (1), and then we perform the process in Section IV.C; otherwise, we perform the process of backtrack coloring in Section IV.B, and then the process in Section IV.C. In fact, our computational experiments indicate that, only very few independent components need backtrack coloring. B. Backtrack coloring Let x = (C 1, C 2, C 3, R 4 ) be a relaxation color assignment of independent component G got by program (2). We introduce a set W OSF to represent the features in UNCF which cannot be inserted only s i = 1 stitch to eliminate conflicts. We try to find a better relaxation coloring solution x = (C1, C2, C3, R4) of G by Algorithm 2, and then insert stitches into the features in R4. The Algorithm 2 is illustrated as follows. At first, we scan all 3-coloring solutions of the 3-colorable graph G m (lines 2-7). For every new coloring solution (C 1, C 2, C 3, R 4 ), we enumerate the candidate one-stitch insertions on features in R 4 by Algorithm 1, and check whether the criterion W OSF = is satisfied or not (line 3). If a solution x with W OSF = is found, then by Theorem 3, it is easy to verify that x is optimal for problem (1); otherwise, all colorings of G will be scanned to find an optimal one (lines 11-19), and we have another break criterion to end the scan (line 14). The criterion means that, if the algorithm has found a solution with cost i R 4 w i, which is the optimal value of program (2), then it is optimal for problem (1) and it does not need to scan further. Note that stitch insertions should be found before calculating cost(x ) = C + α S (line 12). Here, we consider multi-stitch insertions more than one-stitch insertions. Main steps for finding candidate multi-stitch insertions are similar to those in Algorithm 1, and the details are omitted here. Fig. 6 shows two examples of backtrack coloring. C. Density balance aware global coloring The graph reduction step is performed before the minimum cost coloring step, during which some vertices are removed. Hence these removed vertices are uncolored at the minimum cost coloring step and the legalization step. Let RV be the set of removed vertices. In order to obtain the final solution, these vertices need to be assigned colors. (b) (d)

8 8 Algorithm 2: Backtrack coloring Input: independent component G and coloring solution x = (C 1, C 2, C 3, R 4 ) by program (2); Output: another coloring solution x of G; 1: G m = G/R 4 ; 2: for every legal 3-coloring y = (C 1, C 2, C 3) of G m do 3: if there exist one-stitch insertions such that W OSF = then 4: x = (C 1, C 2, C 3, R 4 ); 5: break; 6: end if 7: end for 8: if W OSF = then 9: return x ; 10: else 11: for all coloring x = (C 1, C 2, C 3, R 4) of G with R 4 R 4 do 12: calculate the decomposition cost of x : cost(x ) = C + α S ; 13: if find a less cost solution x then 14: if cost(x ) == i R 4 w i then 15: x = x ; Break; 16: end if 17: x = x ; 18: end if 19: end for 20: return x ; 21: end if In this part, we color the removed vertices (removed features) in the set RV in the reverse order of removing them at the graph reduction step. Suppose that feature a is a removed feature in RV. Then there are three cases: 1) all adjacent features of feature a have no stitches; 2) there are some adjacent features of feature a having stitches, but all stitches are optimal stitches with cut cost(s) = 0; 3) there are some stitches with cut cost(s) > 0 on some adjacent features of feature a. For the first two cases, since the degree of feature a is unchanged, and according to our graph reduction methods (Section V), it is easy to color feature a using one of the three colors. However, for the third case, since the stitches with cut cost > 0 increase the degree of feature a, coloring feature a legally may become hard. In this case the backtrack coloring algorithm and stitch finding approach presented in Section IV will be called for finding a legal coloring of feature a. For example, look at the feature e in Fig. 7(c). If feature d is inserted a stitch with cut cost e = 1, then the degree of feature e will become three, and it may generate a conflict when color feature e. For this case, in order to obtain the minimum cost coloring solution of the independent component, which includes feature a, the backtrack coloring algorithm and stitch finding approach presented at Section IV, will be called again. On the other hand, since the well balanced decomposition is benefit for the manufacturing process [10], [21], density (a) (c) Fig. 7. An example of graph reduction. (a) The initial graph. (b)(c)(d) The remainder graphs after removing vertices with degree less than 3. balance is considered at our global coloring. It is observed that there are many features whose colors are optional during coloring, we call them color-optional-features. The total area of features with the same color is utilized to balance density. We define the feature density proportion of the three colors as (A 1 : A 2 : A 3 ), where A i (i = 1, 2, 3) is the total area of features with the same color. During the process of global coloring, a color-optional-feature will be assigned a color with the current smallest feature density. This strategy benefits the balance of feature densities of the three colors. V. GRAPH REDUCTION For finding a coloring solution fast, independent components of the conflict graph will be computed before coloring. We adopt two non-conflict feature removal methods for this purpose: vertex with degree less than three removal [9], [11], [12]; contained vertex removal. The removed vertices are added to the set RV, and after coloring the other vertices, we color all vertices in RV one by one. Details of the two non-conflict feature removal methods are as follows. A. Vertex with degree less than three removal The vertex with degree less than three removal technique has been adopted in [9], [11], [12], and has achieved great success in graph reduction for the TPL decomposition problem. If a vertex has degree less than three, then after coloring the other vertices, this vertex can easily be colored using one of the three colors without conflict occurring. Motivated by this observation, we remove a vertex with degree less than three in the initial conflict graph, and remove another vertex with degree less than three in the remainder graph. This process is repeated many times until there are no vertices with degree less than three in the remainder graph. As Fig. 7, after removing the first vertex with degree less than three, the remainder graph is showed as Fig. 7(b). Continuing to remove vertices with degree less than three, the final remainder graph is showed as Fig. 7(d). The running time complexity of removing all vertices with degree less than three is O( V ), where V is the number of vertices of the graph. As removal of a vertex with degree less than three does not change 3-colorable of the initial conflict graph, an obvious (b) (d)

9 9 induction can show that repeatedly many times of removal does not change 3-colorable of the initial conflict graph. B. Contained vertex removal Contained vertex removal is performed after vertex with degree less than three removal. Firstly we introduce the definition of contained vertex [20]. Given a graph G(V, E), for every pair of vertices i, j V, suppose that e ij / V and A(i) A(j), where A(i) and A(j) are the set of adjacent vertices of vertices i and j, respectively. We call that vertex i is contained in vertex j, and call vertex i a contained vertex. In Fig. 7(a), vertex g is a contained vertex, since e ge V, and A(g) = {d, f} A(e) = {b, d, f}. According to the definition of contained vertex, we can assign the color of vertex j to vertex i, which does not make any conflicts. Hence we find all contained vertices in the remainder graph after the vertex with degree less than three removal, and remove them before coloring. The running time complexity of removing all contained vertices is O( V 2 ), where V is the number of vertices in the remainder graph. VI. EXPERIMENTAL RESULTS In order to evaluate our TPL decomposition method, we test the algorithm on the ISCAS-85 & 89 benchmarks provided by Yu et al. [9]. The circuit sizes of the benchmarks range from 1109 to 168K. The algorithm was programmed in C++ and run on a personal computer with 2.4GHz CPU, 16GB memory and the Linux operating system. For program (2), we modified the non-linear IP solver code of GUROBI [19] as our nonlinear 0-1 program solver. For comparing with previous TPL decomposers, we set the parameter values the same as those in previous works. More precisely, the minimum coloring spacing min cs was set as 120nm for benchmarks C432-C7552, and as 100nm for benchmarks S1488-S15850; the minimum feature size min fs was set as 10nm, and the weight parameter α was set as 0.1. The test results are listed in Table II. TABLE II TEST RESULTS OF OUR DECOMPOSITION METHOD Benchs #IC #RIC Ratio #UCF #UNCF #WOSF Den C C C C C C C C C C S S S S S A. Analysis of our test results In Table II, the data in the columns #IC and #RIC are the numbers of independent components of the initial graphs, and the numbers of independent components of the remainder graphs after graph reduction, respectively. The data in the column ratio are the ratios between the numbers of edges and the numbers of vertices in the remainder independent components, respectively. From Table II, the data in the column #RIC are small, compared with the data in the column #IC. Specifically, the average #RIC is only 1.1% of #IC. Hence we can conclude that our graph reduction methods are effective. The data in the column #UCF of Table II are the numbers of uncolored conflict features by our algorithm on the benchmarks. By Theorem 1, we know that #UCF is a lower bound on the conflict number for TPL. The data in the column #C of Table III are the total conflict numbers found by our algorithm on the benchmarks. Comparing #UCF with #C, we find both of them are equal for every benchmark. Hence, our decomposition method found results with the minimum conflict numbers for these benchmarks. The data in the columns #UNCF and #WOSF of Table II are the numbers of uncolored non-conflict features, and the numbers of uncolored non-conflict features without onestitch insertion, respectively. According to Theorem 3, if every feature i UNCF could be inserted s i = 1 stitch to eliminate conflicts, and every feature i U CF contributes only a conflict number, then we have obtained a minimum cost solution. Table II shows that most of benchmarks C432- C5315 and S1488-S38417 are with #WOSF=0, i.e., we have achieved optimal decomposition costs for these benchmarks. Furthermore, we define den = max {A 1, A 2, A 3 } min {A 1, A 2, A 3 } as our density balance measurement. From the column Den in Table II, it can be seen that most of benchmarks have Den close to 1, i.e., the total areas of the obtained three masks are almost equal. So the densities of our results are well balanced. B. Comparing with other TPL decomposers In Table III, we list the test results of our algorithm and the state-of-the-art TPL decomposers [10], [11], [12], on the benchmarks C432-C7552 and S1488-S15850 with min cs = 120/100nm. The test results of the state-of-theart TPL decomposers [10], [11], [12] are quoted from the respective publications directly. In the table, the data in the columns #C and #S denote the numbers of conflicts and the numbers of stitches of the final results, respectively. And the data in the column Cost are calculated in the same way as in problem (1) and references [10], [11], [12]. The data in the columns CPU(s) are the running times of our algorithm and the decomposers [10], [11], [12], respectively. It must be noted that: 1) the experimental results listed in [10], [11], [12] are without density balance; 2) their decomposers were implemented on computers with better configurations than ours. In spite of these, we still compare our test results with theirs. From Table III, we can see that our method achieves the best TPL decomposition result for every benchmark among the compared decomposers. The last row in Table III lists the average #C, #S, Cost and runtime;

10 10 TABLE III EXPERIMENTAL RESULT COMPARISONS min cs = 120 / 100nm From [11] From [12] From [10] Ours Benchs #C #S Cost CPU(s) #C #S Cost CPU(s) #C #S Cost CPU(s) #C #S Cost CPU(s) C C C C C C C C C C S S S S S Avg Ratio TABLE IV STATISTICS AND COMPARISONS ON DENSE LAYOUT min cs = 120nm Statistics From [9] From [21] Ours benchs #UCF #UNCF #WOSF #C #S Cost #C #S Cost #C #S Cost S S S S S Avg Ratio and lists the Cost, runtime ratios based on the results of our TPL decomposition. Comparing with the results achieved by Kuang et al. [12], which is the fastest decomposer, we reduce the average number of conflicts by 12%, and the average cost by 8%. For the state-of-the-art decomposer proposed by Yu et al. [10], the average cost is 2% more than ours, and the running time is 9 times more than ours. These comparisons validate the effectiveness of our method. To show stability of our approach, we have performed an additional experiment by testing our method on benchmarks S1488-S15850 with minimum coloring spacing min cs = 120nm. It is obvious that the conflict graphs of these benchmarks are more dense. The test results of our method and the compared decomposers are listed in Table IV, where the data in column Statistics are by our decomposition method. Also, we list in the last row of Table IV the average #C, #S and Cost, and the #C, #S and Cost ratios based on the results of our decomposition. From Table IV, we can see that our method achieves average decomposition cost less than [9] and [21] by 63% and 105%, respectively. Comparing the number of uncolored conflict features #UCF and the number of conflicts #C by our method in Table IV, we can see the two statistics are almost equal. Hence our approach is more stable and effective on dense layouts among the compared decomposers. C. Scalability of our approach To analyze scalability of our decomposition method, in Fig. 8 we draw a figure to present the relationship between the number of features and the running time of our decomposition method. The figure is based on our computational results in Table III. In the figure, the bottom dotted line is the plot of function y = 0.7x; the up dotted line is the plot of function y = 1.1x; and our runtime picture is the middle solid line. This fully illustrates that our minimum-cost decomposition method is almost a liner-time algorithm in practice. Fig. 8. Running time (s) Runtime complexity Number of nodes Running time vs the number of vertices. VII. CONCLUSIONS In this paper, we have proposed a minimum cost coloring method for TPL layout decomposition. We designed a surface runtime 0.7X 1.1X x 10 4

11 11 projection method to locate potential native conflicts among the features. The conflict graph was constructed based on the surface projection method, rather than based on the edge projection method. Then the TPL layout decomposition was modeled as a minimum cost coloring problem. To solve the problem fast, we converted the TPL layout decomposition problem to a relaxed version by ignoring stitch insertions. After that, a nonlinear 0-1 program was proposed to obtain a relaxation solution, and then the relaxation solution was legalized to a feasible solution with stitch insertions by our legalization method. The optimal value of the nonlinear 0-1 programming problem provides a lower bound on the optimal value of the minimum cost coloring problem, and in some cases both of the two problems are equivalent. In our decomposition method, legalization is based on carefully adopted techniques, e.g., the optimal one-stitch insertion, backtrack coloring. To reduce graph size, two graph reduction methods were used. Experiments on tested benchmarks show that our decomposition method is efficient and effective, compared with the state-of-the-art decomposers. ACKNOWLEDGMENTS The authors are thankful to Prof. David Z. Pan and Dr. B. Yu for introducing the area of design for manufacturing with advanced lithography, and helpful discussions on some research topics. [13] H. Tian, H. Zhang, Q. Ma, Z. Xiao, and D. F. Wong, A polynomial time triple patterning algorithm for cell based row-structure layout, in Proceedings of the IEEE/ACM International Conference on Computer- Aided Design (ICCAD), pp , [14] H.-A. Chien, S.-Y. Han, Y.-H. Chen, and T.-C. Wang, A cell-based row-structure layout decomposer for triple patterning lithography, in Proceedings of the International Symposium on Physical Design (ISPD), pp , [15] B. Yu, X. Xu, J. R. Gao, Y. Lin, Z. Li, C. Alpert, and D. Z. Pan, Methodology for standard cell compliance and detailed placement for triple patterning lithography, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp , [16] B. J. Lin, Lithography till the end of Moore s law, in Proceedings of the International Symposium on Physical Design (ISPD), pp. 1-2, [17] Y. Kohira, T. Matsui, and Y. Yokoyama, Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography, in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp , [18] B. Yu, S. Roy, J. R. Gao, and D. Z. Pan, Triple patterning lithography layout decomposition using end-cutting, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14, no. 1, , [19] GUROBI, [20] C. Lucet, F. Mendes, and A. Moukrim, Pre-processing and lineardecomposition algorithm to solve the k-colorability problem, Lecture Notes in Computer Science, vol. 3059, pp , [21] Y. Zhang, W. S. Luk, H. Zhou, C. Yan, and X. Zeng, Layout decomposition with pairwise coloring for multiple patterning lithography, in Proceedings of the IEEE/ACM International Conference on Computer- Aided Design (ICCAD), pp , REFERENCES [1] ITRS. [Online]. Available: [2] Y. Borodovsky, Lithography 2009 overview of opportunities, in Semicon West, [3] A. B. Kahng, C. H. Park, X. Xu, and H. Yao, Layout decomposition for double patterning lithography, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp , [4] K. Yuan, J. S. Yang, and D. Z. Pan, Double patterning layout decomposition for simultaneous conflict and stitch minimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 2, pp , [5] Y. Xu and C. Chu, GREMA: graph reduction based efficient mask assignment for double patterning technology, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (IC- CAD), pp , [6] X. Tang and M. Cho, Optimal layout decomposition for double patterning technology, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 9-13, [7] S. Y. Fang, S. Y. Chen, and Y. W. Chang, Native-conflict and stitch-aware wire perturbation for double patterning technology, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 5, pp , [8] C. Cork, J. C. Madre, and L. Barnes, Comparison of triple-patterning decomposition algorithms using aperiodic tiling patterns, in Proceedings of SPIE, Photomask and NGL Mask Technology XV, vol. 7028, [9] B. Yu, K. Yuan, B. Zhang, D. Ding, and D. Z. Pan, Layout decomposition for triple patterning lithography, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 3, pp , [10] B. Yu, Y. H. Lin, G. Luk-Pat, D. Ding, K. Lucas, and D. Z. Pan, A highperformance triple patterning layout decomposer with balanced density, in Proceedings of the IEEE/ACM International Conference on Computer- Aided Design (ICCAD), pp , [11] S. Y. Fang, Y. W. Chang, and W. Y. Chen, A novel layout decomposition algorithm for triple patterning lithography, in Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp , [12] J. Kuang and E. F. Young, An efficient layout decomposition approach for triple patterning lithography, in Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2013.

arxiv: v1 [cs.oh] 2 Aug 2014

arxiv: v1 [cs.oh] 2 Aug 2014 Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting Bei Yu a 1, Subhendu Roy a, Jhih-Rong Gao b, David Z. Pan a a ECE Department, University of Texas at Austin, Austin, Texas, United

More information

Double Patterning-Aware Detailed Routing with Mask Usage Balancing

Double Patterning-Aware Detailed Routing with Mask Usage Balancing Double Patterning-Aware Detailed Routing with Mask Usage Balancing Seong-I Lei Department of Computer Science National Tsing Hua University HsinChu, Taiwan Email: d9762804@oz.nthu.edu.tw Chris Chu Department

More information

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization Kun Yuan, Jae-Seo Yang, David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin

More information

A Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing

A Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing A Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing Qiang Ma Hui Kong Martin D. F. Wong Evangeline F. Y. Young Department of Electrical and Computer Engineering,

More information

Bridging the Gap from Mask to Physical Design for Multiple Patterning Lithography

Bridging the Gap from Mask to Physical Design for Multiple Patterning Lithography Invited Paper Bridging the Gap from Mask to Physical Design for Multiple Patterning Lithography Bei Yu, Jhih-Rong Gao, Xiaoqing Xu, and David Z. Pan ECE Dept. University of Texas at Austin, Austin, TX

More information

A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition

A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition Rani S. Ghaida 1, Kanak B. Agarwal 2, Lars W. Liebmann 3, Sani R. Nassif 2, Puneet Gupta 1 1 UCLA, Electrical Engineering Dept. 2

More information

On Refining Standard Cell Placement for Self-aligned Double Patterning *

On Refining Standard Cell Placement for Self-aligned Double Patterning * On Refining Standard Cell Placement for Self-aligned Double Patterning * Ye-Hong Chen, Sheng-He Wang and Ting-Chi Wang Department of Computer Science, National Tsing Hua University, Hsinchu City 30013,

More information

Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method

Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method Xianhua Ke, Hao Jiang, Wen Lv, and Shiyuan Liu * State Key Laboratory of Digital Manufacturing

More information

TRIPLE patterning lithography (TPL) is regarded as

TRIPLE patterning lithography (TPL) is regarded as IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016 1319 Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based

More information

Obstacle-Aware Longest-Path Routing with Parallel MILP Solvers

Obstacle-Aware Longest-Path Routing with Parallel MILP Solvers , October 20-22, 2010, San Francisco, USA Obstacle-Aware Longest-Path Routing with Parallel MILP Solvers I-Lun Tseng, Member, IAENG, Huan-Wen Chen, and Che-I Lee Abstract Longest-path routing problems,

More information

A Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning

A Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning A Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning Xiaoqing Xu a, Brian Cline b, Greg Yeric b, Bei Yu a and David Z. Pan a a ECE Dept. University

More information

Design for Manufacturability: From Ad Hoc Solution To Extreme Regular Design

Design for Manufacturability: From Ad Hoc Solution To Extreme Regular Design Design for Manufacturability: From Ad Hoc Solution To Extreme Regular Design Bei Yu Department of Computer Science and Engineering The Chinese University of Hong Kong 1 Introduction and Motivation In very

More information

On the Rectangle Escape Problem

On the Rectangle Escape Problem CCCG 2013, Waterloo, Ontario, August 8 10, 2013 On the Rectangle Escape Problem Sepehr Assadi Ehsan Emamjomeh-Zadeh Sadra Yazdanbod Hamid Zarrabi-Zadeh Abstract Motivated by a PCB routing application,

More information

On the Rectangle Escape Problem

On the Rectangle Escape Problem On the Rectangle Escape Problem A. Ahmadinejad S. Assadi E. Emamjomeh-Zadeh S. Yazdanbod H. Zarrabi-Zadeh Abstract Motivated by the bus escape routing problem in printed circuit boards, we study the following

More information

An Optimal Algorithm for Layer Assignment of Bus Escape RoutingonPCBs

An Optimal Algorithm for Layer Assignment of Bus Escape RoutingonPCBs .3 An Optimal Algorithm for Layer Assignment of Bus Escape RoutingonPCBs Qiang Ma Evangeline F. Y. Young Martin D. F. Wong Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign

More information

Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning

Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning R1-16 SASIMI 2015 Proceedings Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning Takeshi Ihara and Atsushi Takahashi Chikaaki Kodama Department of Communications and Computer

More information

Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography

Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography Xiaoqing Xu Brian Cline Greg Yeric Bei Yu David Z. Pan J. Micro/Nanolith. MEMS MOEMS 15(2),

More information

TRIAD: A Triple Patterning Lithography Aware Detailed Router

TRIAD: A Triple Patterning Lithography Aware Detailed Router RIAD: A riple Patterning Lithography Aware Detailed Router Yen-Hung Lin 1,Bei Yu 2, David Z. Pan 2, and Yih-Lang Li 1 1 Department of Computer Science, National Chiao ung University, Hsinchu, aiwan 2 Department

More information

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques. Alexey Lvov Gus Tellez Gi-Joon Nam

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques. Alexey Lvov Gus Tellez Gi-Joon Nam On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques Alexey Lvov Gus Tellez Gi-Joon Nam Background and motivation Manaufacturing difficulty 22nm:

More information

Faster parameterized algorithms for Minimum Fill-In

Faster parameterized algorithms for Minimum Fill-In Faster parameterized algorithms for Minimum Fill-In Hans L. Bodlaender Pinar Heggernes Yngve Villanger Technical Report UU-CS-2008-042 December 2008 Department of Information and Computing Sciences Utrecht

More information

Detailed Routing for Spacer-Is-Metal Type Self-Aligned Double/Quadruple Patterning Lithography

Detailed Routing for Spacer-Is-Metal Type Self-Aligned Double/Quadruple Patterning Lithography Detailed Routing for Spacer-Is-Metal Type Self-Aligned Double/Quadruple Patterning Lithography Yixiao Ding Department of Electrical and Computer Engineering Iowa State University Ames, IA 50010, USA yxding@iastate.edu

More information

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement Minimum Implant Area-Aware Placement and Threshold Voltage Refinement Seong-I Lei Wai-Kei Ma Chris Chu Department of Computer Science Department of Computer Science Department of Electrical and Computer

More information

A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization

A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization Yuzhe Ma, Jhih-Rong Gao 2, Jian Kuang 2, Jin Miao 2, and Bei Yu CSE Department, The Chinese University of Hong Kong, NT,

More information

726 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 5, MAY 2015

726 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 5, MAY 2015 726 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 5, MAY 2015 Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography

More information

On the Rectangle Escape Problem

On the Rectangle Escape Problem CCCG 2013, Waterloo, Ontario, August 8 10, 2013 On the Rectangle Escape Problem Sepehr Assadi Ehsan Emamjomeh-Zadeh Sadra Yazdanbod Hamid Zarrabi-Zadeh Abstract Motivated by a bus routing application,

More information

TCG-Based Multi-Bend Bus Driven Floorplanning

TCG-Based Multi-Bend Bus Driven Floorplanning TCG-Based Multi-Bend Bus Driven Floorplanning Tilen Ma Department of CSE The Chinese University of Hong Kong Shatin, N.T. Hong Kong Evangeline F.Y. Young Department of CSE The Chinese University of Hong

More information

Self-Aligned Double Patterning-Aware Detailed Routing with Double Via Insertion and Via Manufacturability Consideration

Self-Aligned Double Patterning-Aware Detailed Routing with Double Via Insertion and Via Manufacturability Consideration SUBMIT TO IEEE TRANSACTION ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS FOR REVIEW 1 Self-Aligned Double Patterning-Aware Detailed Routing with Double Via Insertion and Via Manufacturability

More information

6.896 Topics in Algorithmic Game Theory March 1, Lecture 8

6.896 Topics in Algorithmic Game Theory March 1, Lecture 8 6.896 Topics in Algorithmic Game Theory March 1, 2010 Lecture 8 Lecturer: Constantinos Daskalakis Scribe: Alan Deckelbaum, Anthony Kim NOTE: The content of these notes has not been formally reviewed by

More information

/ Approximation Algorithms Lecturer: Michael Dinitz Topic: Linear Programming Date: 2/24/15 Scribe: Runze Tang

/ Approximation Algorithms Lecturer: Michael Dinitz Topic: Linear Programming Date: 2/24/15 Scribe: Runze Tang 600.469 / 600.669 Approximation Algorithms Lecturer: Michael Dinitz Topic: Linear Programming Date: 2/24/15 Scribe: Runze Tang 9.1 Linear Programming Suppose we are trying to approximate a minimization

More information

A New Graph Theoretic, Multi Objective Layout Decomposition Framework for Double Patterning Lithography

A New Graph Theoretic, Multi Objective Layout Decomposition Framework for Double Patterning Lithography A New Graph Theoretic, Multi Objective Layout Decomposition Framework for Double Patterning Lithography Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, and David Z. Pan Dept. of ECE, The University of

More information

Faster parameterized algorithms for Minimum Fill-In

Faster parameterized algorithms for Minimum Fill-In Faster parameterized algorithms for Minimum Fill-In Hans L. Bodlaender Pinar Heggernes Yngve Villanger Abstract We present two parameterized algorithms for the Minimum Fill-In problem, also known as Chordal

More information

Basic Idea. The routing problem is typically solved using a twostep

Basic Idea. The routing problem is typically solved using a twostep Global Routing Basic Idea The routing problem is typically solved using a twostep approach: Global Routing Define the routing regions. Generate a tentative route for each net. Each net is assigned to a

More information

Stitch Aware Detailed Placement for Multiple E-Beam Lithography

Stitch Aware Detailed Placement for Multiple E-Beam Lithography Stitch Aware Detailed Placement for Multiple E-Beam Lithography Yibo Lin 1, Bei Yu 2, Yi Zou 1,3, Zhuo Li 4, Charles J. Alpert 4, and David Z. Pan 1 1 ECE Department, University of Texas at Austin 2 CSE

More information

12.1 Formulation of General Perfect Matching

12.1 Formulation of General Perfect Matching CSC5160: Combinatorial Optimization and Approximation Algorithms Topic: Perfect Matching Polytope Date: 22/02/2008 Lecturer: Lap Chi Lau Scribe: Yuk Hei Chan, Ling Ding and Xiaobing Wu In this lecture,

More information

11.1 Facility Location

11.1 Facility Location CS787: Advanced Algorithms Scribe: Amanda Burton, Leah Kluegel Lecturer: Shuchi Chawla Topic: Facility Location ctd., Linear Programming Date: October 8, 2007 Today we conclude the discussion of local

More information

Unit 8: Coping with NP-Completeness. Complexity classes Reducibility and NP-completeness proofs Coping with NP-complete problems. Y.-W.

Unit 8: Coping with NP-Completeness. Complexity classes Reducibility and NP-completeness proofs Coping with NP-complete problems. Y.-W. : Coping with NP-Completeness Course contents: Complexity classes Reducibility and NP-completeness proofs Coping with NP-complete problems Reading: Chapter 34 Chapter 35.1, 35.2 Y.-W. Chang 1 Complexity

More information

Overlapping-aware Throughput-driven Stencil Planning for E-Beam Lithography

Overlapping-aware Throughput-driven Stencil Planning for E-Beam Lithography Overlapping-aware Throughput-driven Stencil Planning for E-Beam Lithography Jian Kuang and Evangeline F.Y. Young Department of Computer Science and Engineering The Chinese University of Hong Kong, Shatin,

More information

Power-Mode-Aware Buffer Synthesis for Low-Power Clock Skew Minimization

Power-Mode-Aware Buffer Synthesis for Low-Power Clock Skew Minimization This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Power-Mode-Aware Buffer Synthesis for Low-Power

More information

An Automated System for Checking Lithography Friendliness of Standard Cells

An Automated System for Checking Lithography Friendliness of Standard Cells An Automated System for Checking Lithography Friendliness of Standard Cells I-Lun Tseng, Senior Member, IEEE, Yongfu Li, Senior Member, IEEE, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, and Jonathan

More information

E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System

E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System Bei Yu, Kun Yuan*, Jhih-Rong Gao, and David Z. Pan ECE Dept. University of Texas at Austin, TX *Cadence Inc., CA Supported in

More information

Algorithms for Euclidean TSP

Algorithms for Euclidean TSP This week, paper [2] by Arora. See the slides for figures. See also http://www.cs.princeton.edu/~arora/pubs/arorageo.ps Algorithms for Introduction This lecture is about the polynomial time approximation

More information

Discrete Optimization. Lecture Notes 2

Discrete Optimization. Lecture Notes 2 Discrete Optimization. Lecture Notes 2 Disjunctive Constraints Defining variables and formulating linear constraints can be straightforward or more sophisticated, depending on the problem structure. The

More information

15-854: Approximations Algorithms Lecturer: Anupam Gupta Topic: Direct Rounding of LP Relaxations Date: 10/31/2005 Scribe: Varun Gupta

15-854: Approximations Algorithms Lecturer: Anupam Gupta Topic: Direct Rounding of LP Relaxations Date: 10/31/2005 Scribe: Varun Gupta 15-854: Approximations Algorithms Lecturer: Anupam Gupta Topic: Direct Rounding of LP Relaxations Date: 10/31/2005 Scribe: Varun Gupta 15.1 Introduction In the last lecture we saw how to formulate optimization

More information

On Covering a Graph Optimally with Induced Subgraphs

On Covering a Graph Optimally with Induced Subgraphs On Covering a Graph Optimally with Induced Subgraphs Shripad Thite April 1, 006 Abstract We consider the problem of covering a graph with a given number of induced subgraphs so that the maximum number

More information

9.1 Cook-Levin Theorem

9.1 Cook-Levin Theorem CS787: Advanced Algorithms Scribe: Shijin Kong and David Malec Lecturer: Shuchi Chawla Topic: NP-Completeness, Approximation Algorithms Date: 10/1/2007 As we ve already seen in the preceding lecture, two

More information

CS 473: Algorithms. Ruta Mehta. Spring University of Illinois, Urbana-Champaign. Ruta (UIUC) CS473 1 Spring / 36

CS 473: Algorithms. Ruta Mehta. Spring University of Illinois, Urbana-Champaign. Ruta (UIUC) CS473 1 Spring / 36 CS 473: Algorithms Ruta Mehta University of Illinois, Urbana-Champaign Spring 2018 Ruta (UIUC) CS473 1 Spring 2018 1 / 36 CS 473: Algorithms, Spring 2018 LP Duality Lecture 20 April 3, 2018 Some of the

More information

A Reduction of Conway s Thrackle Conjecture

A Reduction of Conway s Thrackle Conjecture A Reduction of Conway s Thrackle Conjecture Wei Li, Karen Daniels, and Konstantin Rybnikov Department of Computer Science and Department of Mathematical Sciences University of Massachusetts, Lowell 01854

More information

On Pioneering Nanometer-Era Routing Problems

On Pioneering Nanometer-Era Routing Problems On Pioneering Nanometer-Era Routing Problems An Appreciation of Professor CL Liu s visionary approach to Physical Design Tong Gao and Prashant Saxena Synopsys, Inc. ISPD 2012 Synopsys 2012 1 Introduction

More information

A Row-and-Column Generation Method to a Batch Machine Scheduling Problem

A Row-and-Column Generation Method to a Batch Machine Scheduling Problem The Ninth International Symposium on Operations Research and Its Applications (ISORA 10) Chengdu-Jiuzhaigou, China, August 19 23, 2010 Copyright 2010 ORSC & APORC, pp. 301 308 A Row-and-Column Generation

More information

Bottleneck Steiner Tree with Bounded Number of Steiner Vertices

Bottleneck Steiner Tree with Bounded Number of Steiner Vertices Bottleneck Steiner Tree with Bounded Number of Steiner Vertices A. Karim Abu-Affash Paz Carmi Matthew J. Katz June 18, 2011 Abstract Given a complete graph G = (V, E), where each vertex is labeled either

More information

Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths

Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu and Chung-Kuan Cheng University of California at San Diego La Jolla,

More information

Solutions for Operations Research Final Exam

Solutions for Operations Research Final Exam Solutions for Operations Research Final Exam. (a) The buffer stock is B = i a i = a + a + a + a + a + a 6 + a 7 = + + + + + + =. And the transportation tableau corresponding to the transshipment problem

More information

Chapter 2 A Second-Order Algorithm for Curve Parallel Projection on Parametric Surfaces

Chapter 2 A Second-Order Algorithm for Curve Parallel Projection on Parametric Surfaces Chapter 2 A Second-Order Algorithm for Curve Parallel Projection on Parametric Surfaces Xiongbing Fang and Hai-Yin Xu Abstract A second-order algorithm is presented to calculate the parallel projection

More information

Approximating Fault-Tolerant Steiner Subgraphs in Heterogeneous Wireless Networks

Approximating Fault-Tolerant Steiner Subgraphs in Heterogeneous Wireless Networks Approximating Fault-Tolerant Steiner Subgraphs in Heterogeneous Wireless Networks Ambreen Shahnaz and Thomas Erlebach Department of Computer Science University of Leicester University Road, Leicester LE1

More information

NP-Hardness. We start by defining types of problem, and then move on to defining the polynomial-time reductions.

NP-Hardness. We start by defining types of problem, and then move on to defining the polynomial-time reductions. CS 787: Advanced Algorithms NP-Hardness Instructor: Dieter van Melkebeek We review the concept of polynomial-time reductions, define various classes of problems including NP-complete, and show that 3-SAT

More information

Local Search Approximation Algorithms for the Complement of the Min-k-Cut Problems

Local Search Approximation Algorithms for the Complement of the Min-k-Cut Problems Local Search Approximation Algorithms for the Complement of the Min-k-Cut Problems Wenxing Zhu, Chuanyin Guo Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou

More information

Self-aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography

Self-aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography Self-aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography Jhih-Rong Gao, Bei Yu and David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at

More information

Advanced multi-patterning and hybrid lithography techniques. Fedor G Pikus, J. Andres Torres

Advanced multi-patterning and hybrid lithography techniques. Fedor G Pikus, J. Andres Torres Advanced multi-patterning and hybrid lithography techniques Fedor G Pikus, J. Andres Torres Outline Need for advanced patterning technologies Multipatterning (MP) technologies What is multipatterning?

More information

Hybrid hotspot detection using regression model and lithography simulation

Hybrid hotspot detection using regression model and lithography simulation Hybrid hotspot detection using regression model and lithography simulation Taiki Kimura 1a, Tetsuaki Matsunawa a, Shigeki Nojima a and David Z. Pan b a Toshiba Corp. Semiconductor & Storage Products Company,

More information

Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid

Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid Yu Zhong Martin D. F. Wong Dept. of Electrical and Computer Engineering Dept. of Electrical and Computer Engineering Univ. of

More information

Self-Aligned Double Patterning Lithography Aware Detailed Routing with Color Pre-Assignment

Self-Aligned Double Patterning Lithography Aware Detailed Routing with Color Pre-Assignment IEEE TRANSACTION ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1 Self-Aligned Double Patterning Lithography Aware Detailed Routing with Color Pre-Assignment Yixiao Ding, Student Member, IEEE,

More information

MOST attention in the literature of network codes has

MOST attention in the literature of network codes has 3862 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 56, NO. 8, AUGUST 2010 Efficient Network Code Design for Cyclic Networks Elona Erez, Member, IEEE, and Meir Feder, Fellow, IEEE Abstract This paper introduces

More information

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability Chung-Wei Lin 1, Ming-Chao Tsai 2, Kuang-Yao Lee 2, Tai-Chen Chen 1, Ting-Chi Wang 2, and Yao-Wen Chang 1 1

More information

Tree Structure and Algorithms for Physical Design

Tree Structure and Algorithms for Physical Design Tree Structure and Algorithms for Physical Design Chung Kuan Cheng, Ronald Graham, Ilgweon Kang, Dongwon Park and Xinyuan Wang CSE and ECE Departments UC San Diego Outline: Introduction Ancestor Trees

More information

Vertical decomposition of a lattice using clique separators

Vertical decomposition of a lattice using clique separators Vertical decomposition of a lattice using clique separators Anne Berry, Romain Pogorelcnik, Alain Sigayret LIMOS UMR CNRS 6158 Ensemble Scientifique des Cézeaux Université Blaise Pascal, F-63 173 Aubière,

More information

The Full Survey on The Euclidean Steiner Tree Problem

The Full Survey on The Euclidean Steiner Tree Problem The Full Survey on The Euclidean Steiner Tree Problem Shikun Liu Abstract The Steiner Tree Problem is a famous and long-studied problem in combinatorial optimization. However, the best heuristics algorithm

More information

A Framework for Double Patterning-Enabled Design

A Framework for Double Patterning-Enabled Design A Framework for Double Patterning-Enabled Design Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta UCLA, Electrical Engineering Dept. IBM Corp., Austin Research

More information

PACKING DIGRAPHS WITH DIRECTED CLOSED TRAILS

PACKING DIGRAPHS WITH DIRECTED CLOSED TRAILS PACKING DIGRAPHS WITH DIRECTED CLOSED TRAILS PAUL BALISTER Abstract It has been shown [Balister, 2001] that if n is odd and m 1,, m t are integers with m i 3 and t i=1 m i = E(K n) then K n can be decomposed

More information

3 INTEGER LINEAR PROGRAMMING

3 INTEGER LINEAR PROGRAMMING 3 INTEGER LINEAR PROGRAMMING PROBLEM DEFINITION Integer linear programming problem (ILP) of the decision variables x 1,..,x n : (ILP) subject to minimize c x j j n j= 1 a ij x j x j 0 x j integer n j=

More information

3 No-Wait Job Shops with Variable Processing Times

3 No-Wait Job Shops with Variable Processing Times 3 No-Wait Job Shops with Variable Processing Times In this chapter we assume that, on top of the classical no-wait job shop setting, we are given a set of processing times for each operation. We may select

More information

Introduction VLSI PHYSICAL DESIGN AUTOMATION

Introduction VLSI PHYSICAL DESIGN AUTOMATION VLSI PHYSICAL DESIGN AUTOMATION PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Introduction Main steps in VLSI physical design 1. Partitioning and Floorplanning l 2. Placement 3.

More information

General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs

General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs Hongbing Fan Dept. of omputer Science University of Victoria Victoria B anada V8W P6 Jiping Liu Dept. of Math. & omp. Sci. University

More information

Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement

Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement Chris C.N. Chu and Evangeline F.Y. Young Abstract Many previous works on floorplanning with non-rectangular modules [,,,,,,,,,,,

More information

Chordal deletion is fixed-parameter tractable

Chordal deletion is fixed-parameter tractable Chordal deletion is fixed-parameter tractable Dániel Marx Institut für Informatik, Humboldt-Universität zu Berlin, Unter den Linden 6, 10099 Berlin, Germany. dmarx@informatik.hu-berlin.de Abstract. It

More information

An Edge-Swap Heuristic for Finding Dense Spanning Trees

An Edge-Swap Heuristic for Finding Dense Spanning Trees Theory and Applications of Graphs Volume 3 Issue 1 Article 1 2016 An Edge-Swap Heuristic for Finding Dense Spanning Trees Mustafa Ozen Bogazici University, mustafa.ozen@boun.edu.tr Hua Wang Georgia Southern

More information

The Ordered Covering Problem

The Ordered Covering Problem The Ordered Covering Problem Uriel Feige Yael Hitron November 8, 2016 Abstract We introduce the Ordered Covering (OC) problem. The input is a finite set of n elements X, a color function c : X {0, 1} and

More information

Lecture 7. s.t. e = (u,v) E x u + x v 1 (2) v V x v 0 (3)

Lecture 7. s.t. e = (u,v) E x u + x v 1 (2) v V x v 0 (3) COMPSCI 632: Approximation Algorithms September 18, 2017 Lecturer: Debmalya Panigrahi Lecture 7 Scribe: Xiang Wang 1 Overview In this lecture, we will use Primal-Dual method to design approximation algorithms

More information

A CSP Search Algorithm with Reduced Branching Factor

A CSP Search Algorithm with Reduced Branching Factor A CSP Search Algorithm with Reduced Branching Factor Igor Razgon and Amnon Meisels Department of Computer Science, Ben-Gurion University of the Negev, Beer-Sheva, 84-105, Israel {irazgon,am}@cs.bgu.ac.il

More information

Crosslink Insertion for Variation-Driven Clock Network Construction

Crosslink Insertion for Variation-Driven Clock Network Construction Crosslink Insertion for Variation-Driven Clock Network Construction Fuqiang Qian, Haitong Tian, Evangeline Young Department of Computer Science and Engineering The Chinese University of Hong Kong {fqqian,

More information

A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages

A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages Yoshiaki KURATA Yoichi TOMIOKA Yukihide KOHIRA Atsushi TAKAHASHI Tokyo Institute of Technology Dept. of Communications

More information

DpRouter: A Fast and Accurate Dynamic- Pattern-Based Global Routing Algorithm

DpRouter: A Fast and Accurate Dynamic- Pattern-Based Global Routing Algorithm DpRouter: A Fast and Accurate Dynamic- Pattern-Based Global Routing Algorithm Zhen Cao 1,Tong Jing 1, 2, Jinjun Xiong 2, Yu Hu 2, Lei He 2, Xianlong Hong 1 1 Tsinghua University 2 University of California,

More information

arxiv: v1 [cs.dm] 21 Dec 2015

arxiv: v1 [cs.dm] 21 Dec 2015 The Maximum Cardinality Cut Problem is Polynomial in Proper Interval Graphs Arman Boyacı 1, Tinaz Ekim 1, and Mordechai Shalom 1 Department of Industrial Engineering, Boğaziçi University, Istanbul, Turkey

More information

6 Randomized rounding of semidefinite programs

6 Randomized rounding of semidefinite programs 6 Randomized rounding of semidefinite programs We now turn to a new tool which gives substantially improved performance guarantees for some problems We now show how nonlinear programming relaxations can

More information

Graphs and Network Flows IE411. Lecture 21. Dr. Ted Ralphs

Graphs and Network Flows IE411. Lecture 21. Dr. Ted Ralphs Graphs and Network Flows IE411 Lecture 21 Dr. Ted Ralphs IE411 Lecture 21 1 Combinatorial Optimization and Network Flows In general, most combinatorial optimization and integer programming problems are

More information

Interleaving Schemes on Circulant Graphs with Two Offsets

Interleaving Schemes on Circulant Graphs with Two Offsets Interleaving Schemes on Circulant raphs with Two Offsets Aleksandrs Slivkins Department of Computer Science Cornell University Ithaca, NY 14853 slivkins@cs.cornell.edu Jehoshua Bruck Department of Electrical

More information

Eulerian disjoint paths problem in grid graphs is NP-complete

Eulerian disjoint paths problem in grid graphs is NP-complete Discrete Applied Mathematics 143 (2004) 336 341 Notes Eulerian disjoint paths problem in grid graphs is NP-complete Daniel Marx www.elsevier.com/locate/dam Department of Computer Science and Information

More information

Chapter 10 Part 1: Reduction

Chapter 10 Part 1: Reduction //06 Polynomial-Time Reduction Suppose we could solve Y in polynomial-time. What else could we solve in polynomial time? don't confuse with reduces from Chapter 0 Part : Reduction Reduction. Problem X

More information

Linear Programming Duality and Algorithms

Linear Programming Duality and Algorithms COMPSCI 330: Design and Analysis of Algorithms 4/5/2016 and 4/7/2016 Linear Programming Duality and Algorithms Lecturer: Debmalya Panigrahi Scribe: Tianqi Song 1 Overview In this lecture, we will cover

More information

Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits

Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits Suchandra Banerjee Anand Ratna Suchismita Roy mailnmeetsuchandra@gmail.com pacific.anand17@hotmail.com suchismita27@yahoo.com

More information

The Encoding Complexity of Network Coding

The Encoding Complexity of Network Coding The Encoding Complexity of Network Coding Michael Langberg Alexander Sprintson Jehoshua Bruck California Institute of Technology Email: mikel,spalex,bruck @caltech.edu Abstract In the multicast network

More information

An Efficient Algorithm for Computing Non-overlapping Inversion and Transposition Distance

An Efficient Algorithm for Computing Non-overlapping Inversion and Transposition Distance An Efficient Algorithm for Computing Non-overlapping Inversion and Transposition Distance Toan Thang Ta, Cheng-Yao Lin and Chin Lung Lu Department of Computer Science National Tsing Hua University, Hsinchu

More information

Scan Scheduling Specification and Analysis

Scan Scheduling Specification and Analysis Scan Scheduling Specification and Analysis Bruno Dutertre System Design Laboratory SRI International Menlo Park, CA 94025 May 24, 2000 This work was partially funded by DARPA/AFRL under BAE System subcontract

More information

LAYOUT DECOMPOSITION FOR TRIPLE PATTERNING LITHOGRAPHY HAITONG TIAN DISSERTATION

LAYOUT DECOMPOSITION FOR TRIPLE PATTERNING LITHOGRAPHY HAITONG TIAN DISSERTATION c 2016 Haitong Tian LAYOUT DECOMPOSITION FOR TRIPLE PATTERNING LITHOGRAPHY BY HAITONG TIAN DISSERTATION Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical

More information

Treewidth and graph minors

Treewidth and graph minors Treewidth and graph minors Lectures 9 and 10, December 29, 2011, January 5, 2012 We shall touch upon the theory of Graph Minors by Robertson and Seymour. This theory gives a very general condition under

More information

Monotone Paths in Geometric Triangulations

Monotone Paths in Geometric Triangulations Monotone Paths in Geometric Triangulations Adrian Dumitrescu Ritankar Mandal Csaba D. Tóth November 19, 2017 Abstract (I) We prove that the (maximum) number of monotone paths in a geometric triangulation

More information

GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology

GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology REMA: raph Reduction Based Efficient Mask Assignment for Double Patterning Technology ABSTRACT Yue Xu Electrical and Computer Engineering owa State University Ames, A 50011 yuexu@iastate.edu Double patterning

More information

2386 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 6, JUNE 2006

2386 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 6, JUNE 2006 2386 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 6, JUNE 2006 The Encoding Complexity of Network Coding Michael Langberg, Member, IEEE, Alexander Sprintson, Member, IEEE, and Jehoshua Bruck,

More information

Maximizing edge-ratio is NP-complete

Maximizing edge-ratio is NP-complete Maximizing edge-ratio is NP-complete Steven D Noble, Pierre Hansen and Nenad Mladenović February 7, 01 Abstract Given a graph G and a bipartition of its vertices, the edge-ratio is the minimum for both

More information

Theorem 2.9: nearest addition algorithm

Theorem 2.9: nearest addition algorithm There are severe limits on our ability to compute near-optimal tours It is NP-complete to decide whether a given undirected =(,)has a Hamiltonian cycle An approximation algorithm for the TSP can be used

More information

Planning for Local Net Congestion in Global Routing

Planning for Local Net Congestion in Global Routing Planning for Local Net Congestion in Global Routing Hamid Shojaei, Azadeh Davoodi, and Jeffrey Linderoth* Department of Electrical and Computer Engineering *Department of Industrial and Systems Engineering

More information